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authorMartin Schwidefsky <schwidefsky@de.ibm.com>2006-09-28 10:56:43 -0400
committerMartin Schwidefsky <schwidefsky@de.ibm.com>2006-09-28 10:56:43 -0400
commit94c12cc7d196bab34aaa98d38521549fa1e5ef76 (patch)
tree8e0cec0ed44445d74a2cb5160303d6b4dfb1bc31 /arch/s390/math-emu/math.c
parent25d83cbfaa44e1b9170c0941c3ef52ca39f54ccc (diff)
[S390] Inline assembly cleanup.
Major cleanup of all s390 inline assemblies. They now have a common coding style. Quite a few have been shortened, mainly by using register asm variables. Use of the EX_TABLE macro helps as well. The atomic ops, bit ops and locking inlines new use the Q-constraint if a newer gcc is used. That results in slightly better code. Thanks to Christian Borntraeger for proof reading the changes. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'arch/s390/math-emu/math.c')
-rw-r--r--arch/s390/math-emu/math.c126
1 files changed, 62 insertions, 64 deletions
diff --git a/arch/s390/math-emu/math.c b/arch/s390/math-emu/math.c
index b4957c84e4d6..6b9aec5a2c18 100644
--- a/arch/s390/math-emu/math.c
+++ b/arch/s390/math-emu/math.c
@@ -1564,52 +1564,52 @@ static int emu_tceb (struct pt_regs *regs, int rx, long val) {
1564} 1564}
1565 1565
1566static inline void emu_load_regd(int reg) { 1566static inline void emu_load_regd(int reg) {
1567 if ((reg&9) != 0) /* test if reg in {0,2,4,6} */ 1567 if ((reg&9) != 0) /* test if reg in {0,2,4,6} */
1568 return; 1568 return;
1569 asm volatile ( /* load reg from fp_regs.fprs[reg] */ 1569 asm volatile( /* load reg from fp_regs.fprs[reg] */
1570 " bras 1,0f\n" 1570 " bras 1,0f\n"
1571 " ld 0,0(%1)\n" 1571 " ld 0,0(%1)\n"
1572 "0: ex %0,0(1)" 1572 "0: ex %0,0(1)"
1573 : /* no output */ 1573 : /* no output */
1574 : "a" (reg<<4),"a" (&current->thread.fp_regs.fprs[reg].d) 1574 : "a" (reg<<4),"a" (&current->thread.fp_regs.fprs[reg].d)
1575 : "1" ); 1575 : "1");
1576} 1576}
1577 1577
1578static inline void emu_load_rege(int reg) { 1578static inline void emu_load_rege(int reg) {
1579 if ((reg&9) != 0) /* test if reg in {0,2,4,6} */ 1579 if ((reg&9) != 0) /* test if reg in {0,2,4,6} */
1580 return; 1580 return;
1581 asm volatile ( /* load reg from fp_regs.fprs[reg] */ 1581 asm volatile( /* load reg from fp_regs.fprs[reg] */
1582 " bras 1,0f\n" 1582 " bras 1,0f\n"
1583 " le 0,0(%1)\n" 1583 " le 0,0(%1)\n"
1584 "0: ex %0,0(1)" 1584 "0: ex %0,0(1)"
1585 : /* no output */ 1585 : /* no output */
1586 : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].f) 1586 : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].f)
1587 : "1" ); 1587 : "1");
1588} 1588}
1589 1589
1590static inline void emu_store_regd(int reg) { 1590static inline void emu_store_regd(int reg) {
1591 if ((reg&9) != 0) /* test if reg in {0,2,4,6} */ 1591 if ((reg&9) != 0) /* test if reg in {0,2,4,6} */
1592 return; 1592 return;
1593 asm volatile ( /* store reg to fp_regs.fprs[reg] */ 1593 asm volatile( /* store reg to fp_regs.fprs[reg] */
1594 " bras 1,0f\n" 1594 " bras 1,0f\n"
1595 " std 0,0(%1)\n" 1595 " std 0,0(%1)\n"
1596 "0: ex %0,0(1)" 1596 "0: ex %0,0(1)"
1597 : /* no output */ 1597 : /* no output */
1598 : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].d) 1598 : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].d)
1599 : "1" ); 1599 : "1");
1600} 1600}
1601 1601
1602 1602
1603static inline void emu_store_rege(int reg) { 1603static inline void emu_store_rege(int reg) {
1604 if ((reg&9) != 0) /* test if reg in {0,2,4,6} */ 1604 if ((reg&9) != 0) /* test if reg in {0,2,4,6} */
1605 return; 1605 return;
1606 asm volatile ( /* store reg to fp_regs.fprs[reg] */ 1606 asm volatile( /* store reg to fp_regs.fprs[reg] */
1607 " bras 1,0f\n" 1607 " bras 1,0f\n"
1608 " ste 0,0(%1)\n" 1608 " ste 0,0(%1)\n"
1609 "0: ex %0,0(1)" 1609 "0: ex %0,0(1)"
1610 : /* no output */ 1610 : /* no output */
1611 : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].f) 1611 : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].f)
1612 : "1" ); 1612 : "1");
1613} 1613}
1614 1614
1615int math_emu_b3(__u8 *opcode, struct pt_regs * regs) { 1615int math_emu_b3(__u8 *opcode, struct pt_regs * regs) {
@@ -2089,23 +2089,22 @@ int math_emu_ldr(__u8 *opcode) {
2089 2089
2090 if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */ 2090 if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */
2091 /* we got an exception therfore ry can't be in {0,2,4,6} */ 2091 /* we got an exception therfore ry can't be in {0,2,4,6} */
2092 __asm__ __volatile ( /* load rx from fp_regs.fprs[ry] */ 2092 asm volatile( /* load rx from fp_regs.fprs[ry] */
2093 " bras 1,0f\n" 2093 " bras 1,0f\n"
2094 " ld 0,0(%1)\n" 2094 " ld 0,0(%1)\n"
2095 "0: ex %0,0(1)" 2095 "0: ex %0,0(1)"
2096 : /* no output */ 2096 : /* no output */
2097 : "a" (opc & 0xf0), 2097 : "a" (opc & 0xf0), "a" (&fp_regs->fprs[opc & 0xf].d)
2098 "a" (&fp_regs->fprs[opc & 0xf].d) 2098 : "1");
2099 : "1" );
2100 } else if ((opc & 0x9) == 0) { /* test if ry in {0,2,4,6} */ 2099 } else if ((opc & 0x9) == 0) { /* test if ry in {0,2,4,6} */
2101 __asm__ __volatile ( /* store ry to fp_regs.fprs[rx] */ 2100 asm volatile ( /* store ry to fp_regs.fprs[rx] */
2102 " bras 1,0f\n" 2101 " bras 1,0f\n"
2103 " std 0,0(%1)\n" 2102 " std 0,0(%1)\n"
2104 "0: ex %0,0(1)" 2103 "0: ex %0,0(1)"
2105 : /* no output */ 2104 : /* no output */
2106 : "a" ((opc & 0xf) << 4), 2105 : "a" ((opc & 0xf) << 4),
2107 "a" (&fp_regs->fprs[(opc & 0xf0)>>4].d) 2106 "a" (&fp_regs->fprs[(opc & 0xf0)>>4].d)
2108 : "1" ); 2107 : "1");
2109 } else /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */ 2108 } else /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */
2110 fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf]; 2109 fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf];
2111 return 0; 2110 return 0;
@@ -2120,23 +2119,22 @@ int math_emu_ler(__u8 *opcode) {
2120 2119
2121 if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */ 2120 if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */
2122 /* we got an exception therfore ry can't be in {0,2,4,6} */ 2121 /* we got an exception therfore ry can't be in {0,2,4,6} */
2123 __asm__ __volatile ( /* load rx from fp_regs.fprs[ry] */ 2122 asm volatile( /* load rx from fp_regs.fprs[ry] */
2124 " bras 1,0f\n" 2123 " bras 1,0f\n"
2125 " le 0,0(%1)\n" 2124 " le 0,0(%1)\n"
2126 "0: ex %0,0(1)" 2125 "0: ex %0,0(1)"
2127 : /* no output */ 2126 : /* no output */
2128 : "a" (opc & 0xf0), 2127 : "a" (opc & 0xf0), "a" (&fp_regs->fprs[opc & 0xf].f)
2129 "a" (&fp_regs->fprs[opc & 0xf].f) 2128 : "1");
2130 : "1" );
2131 } else if ((opc & 0x9) == 0) { /* test if ry in {0,2,4,6} */ 2129 } else if ((opc & 0x9) == 0) { /* test if ry in {0,2,4,6} */
2132 __asm__ __volatile ( /* store ry to fp_regs.fprs[rx] */ 2130 asm volatile( /* store ry to fp_regs.fprs[rx] */
2133 " bras 1,0f\n" 2131 " bras 1,0f\n"
2134 " ste 0,0(%1)\n" 2132 " ste 0,0(%1)\n"
2135 "0: ex %0,0(1)" 2133 "0: ex %0,0(1)"
2136 : /* no output */ 2134 : /* no output */
2137 : "a" ((opc & 0xf) << 4), 2135 : "a" ((opc & 0xf) << 4),
2138 "a" (&fp_regs->fprs[(opc & 0xf0) >> 4].f) 2136 "a" (&fp_regs->fprs[(opc & 0xf0) >> 4].f)
2139 : "1" ); 2137 : "1");
2140 } else /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */ 2138 } else /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */
2141 fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf]; 2139 fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf];
2142 return 0; 2140 return 0;