aboutsummaryrefslogtreecommitdiffstats
path: root/arch/s390/kernel/reipl64.S
diff options
context:
space:
mode:
authorHeiko Carstens <heiko.carstens@de.ibm.com>2006-09-28 10:56:37 -0400
committerMartin Schwidefsky <schwidefsky@de.ibm.com>2006-09-28 10:56:37 -0400
commit25d83cbfaa44e1b9170c0941c3ef52ca39f54ccc (patch)
tree30d9bbc0a1051b837313edfafc40ffa6c5fbfedc /arch/s390/kernel/reipl64.S
parent52149ba6b0ddf3e9d965257cc0513193650b3ea8 (diff)
[S390] Whitespace cleanup.
Huge s390 assembly files whitespace cleanup. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'arch/s390/kernel/reipl64.S')
-rw-r--r--arch/s390/kernel/reipl64.S93
1 files changed, 46 insertions, 47 deletions
diff --git a/arch/s390/kernel/reipl64.S b/arch/s390/kernel/reipl64.S
index 95bd1e234f63..de7435054f7c 100644
--- a/arch/s390/kernel/reipl64.S
+++ b/arch/s390/kernel/reipl64.S
@@ -4,7 +4,7 @@
4 * S390 version 4 * S390 version
5 * Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation 5 * Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com) 6 * Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com)
7 Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) 7 Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
8 */ 8 */
9 9
10#include <asm/lowcore.h> 10#include <asm/lowcore.h>
@@ -32,46 +32,46 @@ do_reipl_asm: basr %r13,0
32 stctg %c0,%c0,.Lregsave-.Lpg0(%r13) 32 stctg %c0,%c0,.Lregsave-.Lpg0(%r13)
33 ni .Lregsave+4-.Lpg0(%r13),0xef 33 ni .Lregsave+4-.Lpg0(%r13),0xef
34 lctlg %c0,%c0,.Lregsave-.Lpg0(%r13) 34 lctlg %c0,%c0,.Lregsave-.Lpg0(%r13)
35 lgr %r1,%r2 35 lgr %r1,%r2
36 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13) 36 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
37 stsch .Lschib-.Lpg0(%r13) 37 stsch .Lschib-.Lpg0(%r13)
38 oi .Lschib+5-.Lpg0(%r13),0x84 38 oi .Lschib+5-.Lpg0(%r13),0x84
39.Lecs: xi .Lschib+27-.Lpg0(%r13),0x01 39.Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
40 msch .Lschib-.Lpg0(%r13) 40 msch .Lschib-.Lpg0(%r13)
41 lghi %r0,5 41 lghi %r0,5
42.Lssch: ssch .Liplorb-.Lpg0(%r13) 42.Lssch: ssch .Liplorb-.Lpg0(%r13)
43 jz .L001 43 jz .L001
44 brct %r0,.Lssch 44 brct %r0,.Lssch
45 bas %r14,.Ldisab-.Lpg0(%r13) 45 bas %r14,.Ldisab-.Lpg0(%r13)
46.L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13) 46.L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
47.Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13) 47.Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
48.Lcont: c %r1,__LC_SUBCHANNEL_ID 48.Lcont: c %r1,__LC_SUBCHANNEL_ID
49 jnz .Ltpi 49 jnz .Ltpi
50 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13) 50 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
51 jnz .Ltpi 51 jnz .Ltpi
52 tsch .Liplirb-.Lpg0(%r13) 52 tsch .Liplirb-.Lpg0(%r13)
53 tm .Liplirb+9-.Lpg0(%r13),0xbf 53 tm .Liplirb+9-.Lpg0(%r13),0xbf
54 jz .L002 54 jz .L002
55 bas %r14,.Ldisab-.Lpg0(%r13) 55 bas %r14,.Ldisab-.Lpg0(%r13)
56.L002: tm .Liplirb+8-.Lpg0(%r13),0xf3 56.L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
57 jz .L003 57 jz .L003
58 bas %r14,.Ldisab-.Lpg0(%r13) 58 bas %r14,.Ldisab-.Lpg0(%r13)
59.L003: spx .Lnull-.Lpg0(%r13) 59.L003: spx .Lnull-.Lpg0(%r13)
60 st %r1,__LC_SUBCHANNEL_ID 60 st %r1,__LC_SUBCHANNEL_ID
61 lhi %r1,0 # mode 0 = esa 61 lhi %r1,0 # mode 0 = esa
62 slr %r0,%r0 # set cpuid to zero 62 slr %r0,%r0 # set cpuid to zero
63 sigp %r1,%r0,0x12 # switch to esa mode 63 sigp %r1,%r0,0x12 # switch to esa mode
64 lpsw 0 64 lpsw 0
65.Ldisab: sll %r14,1 65.Ldisab: sll %r14,1
66 srl %r14,1 # need to kill hi bit to avoid specification exceptions. 66 srl %r14,1 # need to kill hi bit to avoid specification exceptions.
67 st %r14,.Ldispsw+12-.Lpg0(%r13) 67 st %r14,.Ldispsw+12-.Lpg0(%r13)
68 lpswe .Ldispsw-.Lpg0(%r13) 68 lpswe .Ldispsw-.Lpg0(%r13)
69 .align 8 69 .align 8
70.Lclkcmp: .quad 0x0000000000000000 70.Lclkcmp: .quad 0x0000000000000000
71.Lall: .quad 0x00000000ff000000 71.Lall: .quad 0x00000000ff000000
72.Lregsave: .quad 0x0000000000000000 72.Lregsave: .quad 0x0000000000000000
73.Lnull: .long 0x0000000000000000 73.Lnull: .long 0x0000000000000000
74 .align 16 74 .align 16
75/* 75/*
76 * These addresses have to be 31 bit otherwise 76 * These addresses have to be 31 bit otherwise
77 * the sigp will throw a specifcation exception 77 * the sigp will throw a specifcation exception
@@ -81,26 +81,26 @@ do_reipl_asm: basr %r13,0
81 * 31bit lpswe instruction a fact they appear to have 81 * 31bit lpswe instruction a fact they appear to have
82 * ommited from the pop. 82 * ommited from the pop.
83 */ 83 */
84.Lnewpsw: .quad 0x0000000080000000 84.Lnewpsw: .quad 0x0000000080000000
85 .quad .Lpg1 85 .quad .Lpg1
86.Lpcnew: .quad 0x0000000080000000 86.Lpcnew: .quad 0x0000000080000000
87 .quad .Lecs 87 .quad .Lecs
88.Lionew: .quad 0x0000000080000000 88.Lionew: .quad 0x0000000080000000
89 .quad .Lcont 89 .quad .Lcont
90.Lwaitpsw: .quad 0x0202000080000000 90.Lwaitpsw: .quad 0x0202000080000000
91 .quad .Ltpi 91 .quad .Ltpi
92.Ldispsw: .quad 0x0002000080000000 92.Ldispsw: .quad 0x0002000080000000
93 .quad 0x0000000000000000 93 .quad 0x0000000000000000
94.Liplccws: .long 0x02000000,0x60000018 94.Liplccws: .long 0x02000000,0x60000018
95 .long 0x08000008,0x20000001 95 .long 0x08000008,0x20000001
96.Liplorb: .long 0x0049504c,0x0040ff80 96.Liplorb: .long 0x0049504c,0x0040ff80
97 .long 0x00000000+.Liplccws 97 .long 0x00000000+.Liplccws
98.Lschib: .long 0x00000000,0x00000000 98.Lschib: .long 0x00000000,0x00000000
99 .long 0x00000000,0x00000000 99 .long 0x00000000,0x00000000
100 .long 0x00000000,0x00000000 100 .long 0x00000000,0x00000000
101 .long 0x00000000,0x00000000 101 .long 0x00000000,0x00000000
102 .long 0x00000000,0x00000000 102 .long 0x00000000,0x00000000
103 .long 0x00000000,0x00000000 103 .long 0x00000000,0x00000000
104.Liplirb: .long 0x00000000,0x00000000 104.Liplirb: .long 0x00000000,0x00000000
105 .long 0x00000000,0x00000000 105 .long 0x00000000,0x00000000
106 .long 0x00000000,0x00000000 106 .long 0x00000000,0x00000000
@@ -109,4 +109,3 @@ do_reipl_asm: basr %r13,0
109 .long 0x00000000,0x00000000 109 .long 0x00000000,0x00000000
110 .long 0x00000000,0x00000000 110 .long 0x00000000,0x00000000
111 .long 0x00000000,0x00000000 111 .long 0x00000000,0x00000000
112