[S390] Fix tlb flushing with idte.

The clear-by-asce operation of the idte instruction gets an asce
(address-space-control-element) as argument to specify which TLBs
need to get flushed. The current code passes a plain pointer to
the start of the pgd without the additional bits which would make
the pointer an asce. The current machines don't mind the difference
but a future model might want to use the designation type control
bits in the asce as a filter for the TLBs to flush.

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index a87b1976d409..79dccd206a6e 100644
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -157,7 +157,7 @@ startup_continue:
         .long   0xb2b10000              # store facility list
         tm      0xc8,0x08               # check bit for clearing-by-ASCE
         bno     0f-.LPG1(%r13)
-        lhi     %r1,2094
+        lhi     %r1,2048
         lhi     %r2,0
         .long   0xb98e2001
         oi      7(%r12),0x80            # set IDTE flag