[S390] Convert machine feature detection code to C.

From: Heiko Carstens <heiko.carstens@de.ibm.com>
From: Carsten Otte <cotte@de.ibm.com>

This lets us use defines for the magic bits in machine flags instead
of using plain numbers all over the place.
In addition on newer machines features/facilities are indicated by the
result of the stfl instruction. So we use these bits instead of trying
to execute new instructions and check wether we get an exception or
not.
Also the mvpg instruction is always available when in zArch mode,
whereas the idte instruction is only available in zArch mode. This
results in some minor optimizations.

Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Carsten Otte <cotte@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>

1 files changed, 0 insertions, 62 deletions

diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index 79dccd206a6e..9c2c6f7d37e7 100644
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -125,68 +125,6 @@ startup_continue:
 # and create a kernel NSS if the SAVESYS= parm is defined
 #
         brasl   %r14,startup_init
-                                        # set program check new psw mask
-        mvc     __LC_PGM_NEW_PSW(8),.Lpcmsk-.LPG1(%r13)
-        larl    %r12,machine_flags
-#
-# find out if we have the MVPG instruction
-#
-        la      %r1,0f-.LPG1(%r13)      # set program check address
-        stg     %r1,__LC_PGM_NEW_PSW+8
-        sgr     %r0,%r0
-        lghi    %r1,0
-        lghi    %r2,0
-        mvpg    %r1,%r2                 # test MVPG instruction
-        oi      7(%r12),16              # set MVPG flag
-0:
-
-#
-# find out if the diag 0x44 works in 64 bit mode
-#
-        la      %r1,0f-.LPG1(%r13)      # set program check address
-        stg     %r1,__LC_PGM_NEW_PSW+8
-        diag    0,0,0x44                # test diag 0x44
-        oi      7(%r12),32              # set diag44 flag
-0:
-
-#
-# find out if we have the IDTE instruction
-#
-        la      %r1,0f-.LPG1(%r13)      # set program check address
-        stg     %r1,__LC_PGM_NEW_PSW+8
-        .long   0xb2b10000              # store facility list
-        tm      0xc8,0x08               # check bit for clearing-by-ASCE
-        bno     0f-.LPG1(%r13)
-        lhi     %r1,2048
-        lhi     %r2,0
-        .long   0xb98e2001
-        oi      7(%r12),0x80            # set IDTE flag
-0:
-
-#
-# find out if the diag 0x9c is available
-#
-        la      %r1,0f-.LPG1(%r13)      # set program check address
-        stg     %r1,__LC_PGM_NEW_PSW+8
-        stap    __LC_CPUID+4            # store cpu address
-        lh      %r1,__LC_CPUID+4
-        diag    %r1,0,0x9c              # test diag 0x9c
-        oi      6(%r12),1               # set diag9c flag
-0:
-
-#
-# find out if we have the MVCOS instruction
-#
-        la      %r1,0f-.LPG1(%r13)      # set program check address
-        stg     %r1,__LC_PGM_NEW_PSW+8
-        .short  0xc800                  # mvcos 0(%r0),0(%r0),%r0
-        .short  0x0000
-        .short  0x0000
-0:      tm      0x8f,0x13               # special-operation exception?
-        bno     1f-.LPG1(%r13)          # if yes, MVCOS is present
-        oi      6(%r12),2               # set MVCOS flag
-1:
-
         lpswe   .Lentry-.LPG1(13)       # jump to _stext in primary-space,
                                         # virtual and never return ...
         .align  16