[S390] Convert machine feature detection code to C.

From: Heiko Carstens <heiko.carstens@de.ibm.com>
From: Carsten Otte <cotte@de.ibm.com>

This lets us use defines for the magic bits in machine flags instead
of using plain numbers all over the place.
In addition on newer machines features/facilities are indicated by the
result of the stfl instruction. So we use these bits instead of trying
to execute new instructions and check wether we get an exception or
not.
Also the mvpg instruction is always available when in zArch mode,
whereas the idte instruction is only available in zArch mode. This
results in some minor optimizations.

Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Carsten Otte <cotte@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>

1 files changed, 0 insertions, 61 deletions

diff --git a/arch/s390/kernel/head31.S b/arch/s390/kernel/head31.S
index dc364c1419af..a816e2de32b9 100644
--- a/arch/s390/kernel/head31.S
+++ b/arch/s390/kernel/head31.S
@@ -57,61 +57,6 @@ startup_continue:
 #
         l       %r14,.Lstartup_init-.LPG1(%r13)
         basr    %r14,%r14
-
-        l       %r12,.Lmflags-.LPG1(%r13) # get address of machine_flags
-#
-# find out if we have an IEEE fpu
-#
-        mvc     __LC_PGM_NEW_PSW(8),.Lpcfpu-.LPG1(%r13)
-        efpc    %r0,0                   # test IEEE extract fpc instruction
-        oi      3(%r12),2               # set IEEE fpu flag
-.Lchkfpu:
-
-#
-# find out if we have the CSP instruction
-#
-       mvc       __LC_PGM_NEW_PSW(8),.Lpccsp-.LPG1(%r13)
-       la        %r0,0
-       lr       %r1,%r0
-       la       %r2,4
-       csp      %r0,%r2                 # Test CSP instruction
-       oi       3(%r12),8               # set CSP flag
-.Lchkcsp:
-
-#
-# find out if we have the MVPG instruction
-#
-       mvc      __LC_PGM_NEW_PSW(8),.Lpcmvpg-.LPG1(%r13)
-       sr       %r0,%r0
-       la       %r1,0
-       la       %r2,0
-       mvpg     %r1,%r2                 # Test CSP instruction
-       oi       3(%r12),16              # set MVPG flag
-.Lchkmvpg:
-
-#
-# find out if we have the IDTE instruction
-#
-        mvc     __LC_PGM_NEW_PSW(8),.Lpcidte-.LPG1(%r13)
-        .long   0xb2b10000              # store facility list
-        tm      0xc8,0x08               # check bit for clearing-by-ASCE
-        bno     .Lchkidte-.LPG1(%r13)
-        lhi     %r1,2094
-        lhi     %r2,0
-        .long   0xb98e2001
-        oi      3(%r12),0x80            # set IDTE flag
-.Lchkidte:
-
-#
-# find out if the diag 0x9c is available
-#
-        mvc     __LC_PGM_NEW_PSW(8),.Lpcdiag9c-.LPG1(%r13)
-        stap    __LC_CPUID+4            # store cpu address
-        lh      %r1,__LC_CPUID+4
-        diag    %r1,0,0x9c              # test diag 0x9c
-        oi      2(%r12),1               # set diag9c flag
-.Lchkdiag9c:
-
         lpsw  .Lentry-.LPG1(13)         # jump to _stext in primary-space,
                                         # virtual and never return ...
         .align  8
@@ -132,13 +77,7 @@ startup_continue:
         .long   0                       # cr13: home space segment table
         .long   0xc0000000              # cr14: machine check handling off
         .long   0                       # cr15: linkage stack operations
-.Lpcfpu:.long   0x00080000,0x80000000 + .Lchkfpu
-.Lpccsp:.long   0x00080000,0x80000000 + .Lchkcsp
-.Lpcmvpg:.long  0x00080000,0x80000000 + .Lchkmvpg
-.Lpcidte:.long  0x00080000,0x80000000 + .Lchkidte
-.Lpcdiag9c:.long 0x00080000,0x80000000 + .Lchkdiag9c
 .Lmchunk:.long  memory_chunk
-.Lmflags:.long  machine_flags
 .Lbss_bgn:  .long __bss_start
 .Lbss_end:  .long _end
 .Lparmaddr: .long PARMAREA