s390: add support for transactional memory

Allow user-space processes to use transactional execution (TX).
If the TX facility is available user space programs can use
transactions for fine-grained serialization based on the data
objects that are referenced during a transaction. This is
useful for lockless data structures and speculative compiler
optimizations.

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c
index 4bc67db63522..7b6ad271155d 100644
--- a/arch/s390/kernel/dis.c
+++ b/arch/s390/kernel/dis.c
@@ -317,6 +317,9 @@ enum {
         LONG_INSN_RISBLG,
         LONG_INSN_RINEXT,
         LONG_INSN_RIEMIT,
+        LONG_INSN_TABORT,
+        LONG_INSN_TBEGIN,
+        LONG_INSN_TBEGINC,
 };
 
 static char *long_insn_name[] = {
@@ -334,6 +337,9 @@ static char *long_insn_name[] = {
         [LONG_INSN_RISBLG] = "risblk",
         [LONG_INSN_RINEXT] = "rinext",
         [LONG_INSN_RIEMIT] = "riemit",
+        [LONG_INSN_TABORT] = "tabort",
+        [LONG_INSN_TBEGIN] = "tbegin",
+        [LONG_INSN_TBEGINC] = "tbeginc",
 };
 
 static struct insn opcode[] = {
@@ -609,6 +615,9 @@ static struct insn opcode_b2[] = {
         { "lpswe", 0xb2, INSTR_S_RD },
         { "srnmt", 0xb9, INSTR_S_RD },
         { "lfas", 0xbd, INSTR_S_RD },
+        { "etndg", 0xec, INSTR_RRE_R0 },
+        { { 0, LONG_INSN_TABORT }, 0xfc, INSTR_S_RD },
+        { "tend", 0xf8, INSTR_S_RD },
 #endif
         { "stidp", 0x02, INSTR_S_RD },
         { "sck", 0x04, INSTR_S_RD },
@@ -1165,6 +1174,7 @@ static struct insn opcode_e3[] = {
         { "stfh", 0xcb, INSTR_RXY_RRRD },
         { "chf", 0xcd, INSTR_RXY_RRRD },
         { "clhf", 0xcf, INSTR_RXY_RRRD },
+        { "ntstg", 0x25, INSTR_RXY_RRRD },
 #endif
         { "lrv", 0x1e, INSTR_RXY_RRRD },
         { "lrvh", 0x1f, INSTR_RXY_RRRD },
@@ -1188,6 +1198,8 @@ static struct insn opcode_e5[] = {
         { "mvhhi", 0x44, INSTR_SIL_RDI },
         { "mvhi", 0x4c, INSTR_SIL_RDI },
         { "mvghi", 0x48, INSTR_SIL_RDI },
+        { { 0, LONG_INSN_TBEGIN }, 0x60, INSTR_SIL_RDU },
+        { { 0, LONG_INSN_TBEGINC }, 0x61, INSTR_SIL_RDU },
 #endif
         { "lasp", 0x00, INSTR_SSE_RDRD },
         { "tprot", 0x01, INSTR_SSE_RDRD },