[POWERPC] Uartlite: Fix reg io to access documented register size

The Uartlite data sheet defines the registers as 32 bit wide.  This
patch changes the register access to use 32 bit transfers and eliminates
the magic +3 offset which is currently required to make the device
work.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: John Williams <jwilliams@itee.uq.edu.au>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/ppc/syslib/virtex_devices.c b/arch/ppc/syslib/virtex_devices.c
index ace4ec08de51..270ad3acfb59 100644
--- a/arch/ppc/syslib/virtex_devices.c
+++ b/arch/ppc/syslib/virtex_devices.c
@@ -28,7 +28,7 @@
         .num_resources = 2, \
         .resource = (struct resource[]) { \
                 { \
-                        .start = XPAR_UARTLITE_##num##_BASEADDR + 3, \
+                        .start = XPAR_UARTLITE_##num##_BASEADDR, \
                         .end = XPAR_UARTLITE_##num##_HIGHADDR, \
                         .flags = IORESOURCE_MEM, \
                 }, \