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authorAndy Fleming <afleming@freescale.com>2005-10-28 20:46:27 -0400
committerPaul Mackerras <paulus@samba.org>2005-10-29 00:42:28 -0400
commitb37665e0ba1d3f05697bfae249b09a2e9cc95132 (patch)
tree22c80609e3254524038d5b690f1f886b0987f58d /arch/ppc
parentdd03d25fac90ee6f394874fb4e6995866304e4ba (diff)
[PATCH] ppc32: 85xx PHY Platform Update
This patch updates the 85xx platform code to support the new PHY Layer. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <Kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc')
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.c30
-rw-r--r--arch/ppc/platforms/85xx/mpc8560_ads.c25
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.c34
-rw-r--r--arch/ppc/platforms/85xx/sbc8560.c22
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.c21
-rw-r--r--arch/ppc/syslib/mpc85xx_devices.c17
-rw-r--r--arch/ppc/syslib/mpc85xx_sys.c44
7 files changed, 119 insertions, 74 deletions
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c
index 7dc8a68acfd0..7e952c1228cb 100644
--- a/arch/ppc/platforms/85xx/mpc8540_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8540_ads.c
@@ -52,6 +52,10 @@
52 52
53#include <syslib/ppc85xx_setup.h> 53#include <syslib/ppc85xx_setup.h>
54 54
55static const char *GFAR_PHY_0 = "phy0:0";
56static const char *GFAR_PHY_1 = "phy0:1";
57static const char *GFAR_PHY_3 = "phy0:3";
58
55/* ************************************************************************ 59/* ************************************************************************
56 * 60 *
57 * Setup the architecture 61 * Setup the architecture
@@ -63,6 +67,7 @@ mpc8540ads_setup_arch(void)
63 bd_t *binfo = (bd_t *) __res; 67 bd_t *binfo = (bd_t *) __res;
64 unsigned int freq; 68 unsigned int freq;
65 struct gianfar_platform_data *pdata; 69 struct gianfar_platform_data *pdata;
70 struct gianfar_mdio_data *mdata;
66 71
67 /* get the core frequency */ 72 /* get the core frequency */
68 freq = binfo->bi_intfreq; 73 freq = binfo->bi_intfreq;
@@ -89,34 +94,35 @@ mpc8540ads_setup_arch(void)
89 invalidate_tlbcam_entry(num_tlbcam_entries - 1); 94 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
90#endif 95#endif
91 96
97 /* setup the board related info for the MDIO bus */
98 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
99
100 mdata->irq[0] = MPC85xx_IRQ_EXT5;
101 mdata->irq[1] = MPC85xx_IRQ_EXT5;
102 mdata->irq[2] = -1;
103 mdata->irq[3] = MPC85xx_IRQ_EXT5;
104 mdata->irq[31] = -1;
105 mdata->paddr += binfo->bi_immr_base;
106
92 /* setup the board related information for the enet controllers */ 107 /* setup the board related information for the enet controllers */
93 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 108 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
94 if (pdata) { 109 if (pdata) {
95 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 110 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
96 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 111 pdata->bus_id = GFAR_PHY_0;
97 pdata->phyid = 0;
98 /* fixup phy address */
99 pdata->phy_reg_addr += binfo->bi_immr_base;
100 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 112 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
101 } 113 }
102 114
103 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 115 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
104 if (pdata) { 116 if (pdata) {
105 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 117 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
106 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 118 pdata->bus_id = GFAR_PHY_1;
107 pdata->phyid = 1;
108 /* fixup phy address */
109 pdata->phy_reg_addr += binfo->bi_immr_base;
110 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 119 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
111 } 120 }
112 121
113 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC); 122 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);
114 if (pdata) { 123 if (pdata) {
115 pdata->board_flags = 0; 124 pdata->board_flags = 0;
116 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 125 pdata->bus_id = GFAR_PHY_3;
117 pdata->phyid = 3;
118 /* fixup phy address */
119 pdata->phy_reg_addr += binfo->bi_immr_base;
120 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6); 126 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);
121 } 127 }
122 128
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c
index 8841fd7da6ee..208433f1e93a 100644
--- a/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -56,6 +56,10 @@
56#include <syslib/ppc85xx_setup.h> 56#include <syslib/ppc85xx_setup.h>
57 57
58 58
59static const char *GFAR_PHY_0 = "phy0:0";
60static const char *GFAR_PHY_1 = "phy0:1";
61static const char *GFAR_PHY_3 = "phy0:3";
62
59/* ************************************************************************ 63/* ************************************************************************
60 * 64 *
61 * Setup the architecture 65 * Setup the architecture
@@ -68,6 +72,7 @@ mpc8560ads_setup_arch(void)
68 bd_t *binfo = (bd_t *) __res; 72 bd_t *binfo = (bd_t *) __res;
69 unsigned int freq; 73 unsigned int freq;
70 struct gianfar_platform_data *pdata; 74 struct gianfar_platform_data *pdata;
75 struct gianfar_mdio_data *mdata;
71 76
72 cpm2_reset(); 77 cpm2_reset();
73 78
@@ -86,24 +91,28 @@ mpc8560ads_setup_arch(void)
86 mpc85xx_setup_hose(); 91 mpc85xx_setup_hose();
87#endif 92#endif
88 93
94 /* setup the board related info for the MDIO bus */
95 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
96
97 mdata->irq[0] = MPC85xx_IRQ_EXT5;
98 mdata->irq[1] = MPC85xx_IRQ_EXT5;
99 mdata->irq[2] = -1;
100 mdata->irq[3] = MPC85xx_IRQ_EXT5;
101 mdata->irq[31] = -1;
102 mdata->paddr += binfo->bi_immr_base;
103
89 /* setup the board related information for the enet controllers */ 104 /* setup the board related information for the enet controllers */
90 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 105 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
91 if (pdata) { 106 if (pdata) {
92 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 107 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
93 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 108 pdata->bus_id = GFAR_PHY_0;
94 pdata->phyid = 0;
95 /* fixup phy address */
96 pdata->phy_reg_addr += binfo->bi_immr_base;
97 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 109 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
98 } 110 }
99 111
100 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 112 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
101 if (pdata) { 113 if (pdata) {
102 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 114 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
103 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 115 pdata->bus_id = GFAR_PHY_1;
104 pdata->phyid = 1;
105 /* fixup phy address */
106 pdata->phy_reg_addr += binfo->bi_immr_base;
107 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 116 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
108 } 117 }
109 118
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
index eda659916f24..a21156967a5e 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -391,6 +391,9 @@ mpc85xx_cds_pcibios_fixup(void)
391 391
392TODC_ALLOC(); 392TODC_ALLOC();
393 393
394static const char *GFAR_PHY_0 = "phy0:0";
395static const char *GFAR_PHY_1 = "phy0:1";
396
394/* ************************************************************************ 397/* ************************************************************************
395 * 398 *
396 * Setup the architecture 399 * Setup the architecture
@@ -402,6 +405,7 @@ mpc85xx_cds_setup_arch(void)
402 bd_t *binfo = (bd_t *) __res; 405 bd_t *binfo = (bd_t *) __res;
403 unsigned int freq; 406 unsigned int freq;
404 struct gianfar_platform_data *pdata; 407 struct gianfar_platform_data *pdata;
408 struct gianfar_mdio_data *mdata;
405 409
406 /* get the core frequency */ 410 /* get the core frequency */
407 freq = binfo->bi_intfreq; 411 freq = binfo->bi_intfreq;
@@ -445,44 +449,42 @@ mpc85xx_cds_setup_arch(void)
445 invalidate_tlbcam_entry(num_tlbcam_entries - 1); 449 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
446#endif 450#endif
447 451
452 /* setup the board related info for the MDIO bus */
453 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
454
455 mdata->irq[0] = MPC85xx_IRQ_EXT5;
456 mdata->irq[1] = MPC85xx_IRQ_EXT5;
457 mdata->irq[2] = -1;
458 mdata->irq[3] = -1;
459 mdata->irq[31] = -1;
460 mdata->paddr += binfo->bi_immr_base;
461
448 /* setup the board related information for the enet controllers */ 462 /* setup the board related information for the enet controllers */
449 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 463 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
450 if (pdata) { 464 if (pdata) {
451 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 465 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
452 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 466 pdata->bus_id = GFAR_PHY_0;
453 pdata->phyid = 0;
454 /* fixup phy address */
455 pdata->phy_reg_addr += binfo->bi_immr_base;
456 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 467 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
457 } 468 }
458 469
459 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 470 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
460 if (pdata) { 471 if (pdata) {
461 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 472 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
462 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 473 pdata->bus_id = GFAR_PHY_1;
463 pdata->phyid = 1;
464 /* fixup phy address */
465 pdata->phy_reg_addr += binfo->bi_immr_base;
466 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 474 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
467 } 475 }
468 476
469 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1); 477 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);
470 if (pdata) { 478 if (pdata) {
471 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 479 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
472 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 480 pdata->bus_id = GFAR_PHY_0;
473 pdata->phyid = 0;
474 /* fixup phy address */
475 pdata->phy_reg_addr += binfo->bi_immr_base;
476 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 481 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
477 } 482 }
478 483
479 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2); 484 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);
480 if (pdata) { 485 if (pdata) {
481 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 486 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
482 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 487 pdata->bus_id = GFAR_PHY_1;
483 pdata->phyid = 1;
484 /* fixup phy address */
485 pdata->phy_reg_addr += binfo->bi_immr_base;
486 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 488 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
487 } 489 }
488 490
diff --git a/arch/ppc/platforms/85xx/sbc8560.c b/arch/ppc/platforms/85xx/sbc8560.c
index c76760a781c1..b4ee1707a836 100644
--- a/arch/ppc/platforms/85xx/sbc8560.c
+++ b/arch/ppc/platforms/85xx/sbc8560.c
@@ -91,6 +91,9 @@ sbc8560_early_serial_map(void)
91} 91}
92#endif 92#endif
93 93
94static const char *GFAR_PHY_25 = "phy0:25";
95static const char *GFAR_PHY_26 = "phy0:26";
96
94/* ************************************************************************ 97/* ************************************************************************
95 * 98 *
96 * Setup the architecture 99 * Setup the architecture
@@ -102,6 +105,7 @@ sbc8560_setup_arch(void)
102 bd_t *binfo = (bd_t *) __res; 105 bd_t *binfo = (bd_t *) __res;
103 unsigned int freq; 106 unsigned int freq;
104 struct gianfar_platform_data *pdata; 107 struct gianfar_platform_data *pdata;
108 struct gianfar_mdio_data *mdata;
105 109
106 /* get the core frequency */ 110 /* get the core frequency */
107 freq = binfo->bi_intfreq; 111 freq = binfo->bi_intfreq;
@@ -126,24 +130,26 @@ sbc8560_setup_arch(void)
126 invalidate_tlbcam_entry(num_tlbcam_entries - 1); 130 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
127#endif 131#endif
128 132
133 /* setup the board related info for the MDIO bus */
134 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
135
136 mdata->irq[25] = MPC85xx_IRQ_EXT6;
137 mdata->irq[26] = MPC85xx_IRQ_EXT7;
138 mdata->irq[31] = -1;
139 mdata->paddr += binfo->bi_immr_base;
140
129 /* setup the board related information for the enet controllers */ 141 /* setup the board related information for the enet controllers */
130 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 142 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
131 if (pdata) { 143 if (pdata) {
132 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 144 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
133 pdata->interruptPHY = MPC85xx_IRQ_EXT6; 145 pdata->bus_id = GFAR_PHY_25;
134 pdata->phyid = 25;
135 /* fixup phy address */
136 pdata->phy_reg_addr += binfo->bi_immr_base;
137 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 146 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
138 } 147 }
139 148
140 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 149 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
141 if (pdata) { 150 if (pdata) {
142 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 151 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
143 pdata->interruptPHY = MPC85xx_IRQ_EXT7; 152 pdata->bus_id = GFAR_PHY_26;
144 pdata->phyid = 26;
145 /* fixup phy address */
146 pdata->phy_reg_addr += binfo->bi_immr_base;
147 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 153 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
148 } 154 }
149 155
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
index 20940f4044f4..1e1b85f8193a 100644
--- a/arch/ppc/platforms/85xx/stx_gp3.c
+++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -91,6 +91,9 @@ static u8 gp3_openpic_initsenses[] __initdata = {
91 0x0, /* External 11: */ 91 0x0, /* External 11: */
92}; 92};
93 93
94static const char *GFAR_PHY_2 = "phy0:2";
95static const char *GFAR_PHY_4 = "phy0:4";
96
94/* 97/*
95 * Setup the architecture 98 * Setup the architecture
96 */ 99 */
@@ -100,6 +103,7 @@ gp3_setup_arch(void)
100 bd_t *binfo = (bd_t *) __res; 103 bd_t *binfo = (bd_t *) __res;
101 unsigned int freq; 104 unsigned int freq;
102 struct gianfar_platform_data *pdata; 105 struct gianfar_platform_data *pdata;
106 struct gianfar_mdio_data *mdata;
103 107
104 cpm2_reset(); 108 cpm2_reset();
105 109
@@ -118,23 +122,26 @@ gp3_setup_arch(void)
118 mpc85xx_setup_hose(); 122 mpc85xx_setup_hose();
119#endif 123#endif
120 124
125 /* setup the board related info for the MDIO bus */
126 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
127
128 mdata->irq[2] = MPC85xx_IRQ_EXT5;
129 mdata->irq[4] = MPC85xx_IRQ_EXT5;
130 mdata->irq[31] = -1;
131 mdata->paddr += binfo->bi_immr_base;
132
121 /* setup the board related information for the enet controllers */ 133 /* setup the board related information for the enet controllers */
122 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 134 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
123 if (pdata) { 135 if (pdata) {
124 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ 136 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
125 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 137 pdata->bus_id = GFAR_PHY_2;
126 pdata->phyid = 2;
127 pdata->phy_reg_addr += binfo->bi_immr_base;
128 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 138 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
129 } 139 }
130 140
131 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 141 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
132 if (pdata) { 142 if (pdata) {
133 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ 143 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
134 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 144 pdata->bus_id = GFAR_PHY_4;
135 pdata->phyid = 4;
136 /* fixup phy address */
137 pdata->phy_reg_addr += binfo->bi_immr_base;
138 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 145 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
139 } 146 }
140 147
diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c
index bbc5ac0de878..2ede677a0a53 100644
--- a/arch/ppc/syslib/mpc85xx_devices.c
+++ b/arch/ppc/syslib/mpc85xx_devices.c
@@ -25,19 +25,20 @@
25/* We use offsets for IORESOURCE_MEM since we do not know at compile time 25/* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup 26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
27 */ 27 */
28struct gianfar_mdio_data mpc85xx_mdio_pdata = {
29 .paddr = MPC85xx_MIIM_OFFSET,
30};
28 31
29static struct gianfar_platform_data mpc85xx_tsec1_pdata = { 32static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
30 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | 33 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
31 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | 34 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
32 FSL_GIANFAR_DEV_HAS_MULTI_INTR, 35 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
33 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
34}; 36};
35 37
36static struct gianfar_platform_data mpc85xx_tsec2_pdata = { 38static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
37 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | 39 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
38 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | 40 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
39 FSL_GIANFAR_DEV_HAS_MULTI_INTR, 41 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
40 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
41}; 42};
42 43
43static struct gianfar_platform_data mpc85xx_etsec1_pdata = { 44static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
@@ -46,7 +47,6 @@ static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 47 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | 48 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, 49 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
50}; 50};
51 51
52static struct gianfar_platform_data mpc85xx_etsec2_pdata = { 52static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
@@ -55,7 +55,6 @@ static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
55 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 55 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
56 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | 56 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, 57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
58 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
59}; 58};
60 59
61static struct gianfar_platform_data mpc85xx_etsec3_pdata = { 60static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
@@ -64,7 +63,6 @@ static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
64 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 63 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
65 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | 64 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
66 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, 65 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
67 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
68}; 66};
69 67
70static struct gianfar_platform_data mpc85xx_etsec4_pdata = { 68static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
@@ -73,11 +71,10 @@ static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
73 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 71 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
74 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | 72 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
75 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, 73 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
76 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
77}; 74};
78 75
79static struct gianfar_platform_data mpc85xx_fec_pdata = { 76static struct gianfar_platform_data mpc85xx_fec_pdata = {
80 .phy_reg_addr = MPC85xx_ENET1_OFFSET, 77 .device_flags = 0,
81}; 78};
82 79
83static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = { 80static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
@@ -719,6 +716,12 @@ struct platform_device ppc_sys_platform_devices[] = {
719 }, 716 },
720 }, 717 },
721 }, 718 },
719 [MPC85xx_MDIO] = {
720 .name = "fsl-gianfar_mdio",
721 .id = 0,
722 .dev.platform_data = &mpc85xx_mdio_pdata,
723 .num_resources = 0,
724 },
722}; 725};
723 726
724static int __init mach_mpc85xx_fixup(struct platform_device *pdev) 727static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
diff --git a/arch/ppc/syslib/mpc85xx_sys.c b/arch/ppc/syslib/mpc85xx_sys.c
index 6e3184ab354f..cb68d8c58348 100644
--- a/arch/ppc/syslib/mpc85xx_sys.c
+++ b/arch/ppc/syslib/mpc85xx_sys.c
@@ -24,19 +24,19 @@ struct ppc_sys_spec ppc_sys_specs[] = {
24 .ppc_sys_name = "8540", 24 .ppc_sys_name = "8540",
25 .mask = 0xFFFF0000, 25 .mask = 0xFFFF0000,
26 .value = 0x80300000, 26 .value = 0x80300000,
27 .num_devices = 10, 27 .num_devices = 11,
28 .device_list = (enum ppc_sys_devices[]) 28 .device_list = (enum ppc_sys_devices[])
29 { 29 {
30 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_FEC, MPC85xx_IIC1, 30 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_FEC, MPC85xx_IIC1,
31 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 31 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
32 MPC85xx_PERFMON, MPC85xx_DUART, 32 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_MDIO,
33 }, 33 },
34 }, 34 },
35 { 35 {
36 .ppc_sys_name = "8560", 36 .ppc_sys_name = "8560",
37 .mask = 0xFFFF0000, 37 .mask = 0xFFFF0000,
38 .value = 0x80700000, 38 .value = 0x80700000,
39 .num_devices = 19, 39 .num_devices = 20,
40 .device_list = (enum ppc_sys_devices[]) 40 .device_list = (enum ppc_sys_devices[])
41 { 41 {
42 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, 42 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -45,14 +45,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
45 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1, 45 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
46 MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3, MPC85xx_CPM_SCC4, 46 MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3, MPC85xx_CPM_SCC4,
47 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3, 47 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3,
48 MPC85xx_CPM_MCC1, MPC85xx_CPM_MCC2, 48 MPC85xx_CPM_MCC1, MPC85xx_CPM_MCC2, MPC85xx_MDIO,
49 }, 49 },
50 }, 50 },
51 { 51 {
52 .ppc_sys_name = "8541", 52 .ppc_sys_name = "8541",
53 .mask = 0xFFFF0000, 53 .mask = 0xFFFF0000,
54 .value = 0x80720000, 54 .value = 0x80720000,
55 .num_devices = 13, 55 .num_devices = 14,
56 .device_list = (enum ppc_sys_devices[]) 56 .device_list = (enum ppc_sys_devices[])
57 { 57 {
58 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, 58 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -60,13 +60,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
60 MPC85xx_PERFMON, MPC85xx_DUART, 60 MPC85xx_PERFMON, MPC85xx_DUART,
61 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, 61 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C,
62 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, 62 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
63 MPC85xx_MDIO,
63 }, 64 },
64 }, 65 },
65 { 66 {
66 .ppc_sys_name = "8541E", 67 .ppc_sys_name = "8541E",
67 .mask = 0xFFFF0000, 68 .mask = 0xFFFF0000,
68 .value = 0x807A0000, 69 .value = 0x807A0000,
69 .num_devices = 14, 70 .num_devices = 15,
70 .device_list = (enum ppc_sys_devices[]) 71 .device_list = (enum ppc_sys_devices[])
71 { 72 {
72 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, 73 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -74,13 +75,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
74 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, 75 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
75 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, 76 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C,
76 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, 77 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
78 MPC85xx_MDIO,
77 }, 79 },
78 }, 80 },
79 { 81 {
80 .ppc_sys_name = "8555", 82 .ppc_sys_name = "8555",
81 .mask = 0xFFFF0000, 83 .mask = 0xFFFF0000,
82 .value = 0x80710000, 84 .value = 0x80710000,
83 .num_devices = 19, 85 .num_devices = 20,
84 .device_list = (enum ppc_sys_devices[]) 86 .device_list = (enum ppc_sys_devices[])
85 { 87 {
86 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, 88 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -91,13 +93,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
91 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, 93 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
92 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2, 94 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
93 MPC85xx_CPM_USB, 95 MPC85xx_CPM_USB,
96 MPC85xx_MDIO,
94 }, 97 },
95 }, 98 },
96 { 99 {
97 .ppc_sys_name = "8555E", 100 .ppc_sys_name = "8555E",
98 .mask = 0xFFFF0000, 101 .mask = 0xFFFF0000,
99 .value = 0x80790000, 102 .value = 0x80790000,
100 .num_devices = 20, 103 .num_devices = 21,
101 .device_list = (enum ppc_sys_devices[]) 104 .device_list = (enum ppc_sys_devices[])
102 { 105 {
103 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, 106 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -108,6 +111,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
108 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, 111 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
109 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2, 112 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
110 MPC85xx_CPM_USB, 113 MPC85xx_CPM_USB,
114 MPC85xx_MDIO,
111 }, 115 },
112 }, 116 },
113 /* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */ 117 /* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */
@@ -115,104 +119,112 @@ struct ppc_sys_spec ppc_sys_specs[] = {
115 .ppc_sys_name = "8548E", 119 .ppc_sys_name = "8548E",
116 .mask = 0xFFFF00F0, 120 .mask = 0xFFFF00F0,
117 .value = 0x80390010, 121 .value = 0x80390010,
118 .num_devices = 13, 122 .num_devices = 14,
119 .device_list = (enum ppc_sys_devices[]) 123 .device_list = (enum ppc_sys_devices[])
120 { 124 {
121 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, 125 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
122 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, 126 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
123 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 127 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
124 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, 128 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
129 MPC85xx_MDIO,
125 }, 130 },
126 }, 131 },
127 { 132 {
128 .ppc_sys_name = "8548", 133 .ppc_sys_name = "8548",
129 .mask = 0xFFFF00F0, 134 .mask = 0xFFFF00F0,
130 .value = 0x80310010, 135 .value = 0x80310010,
131 .num_devices = 12, 136 .num_devices = 13,
132 .device_list = (enum ppc_sys_devices[]) 137 .device_list = (enum ppc_sys_devices[])
133 { 138 {
134 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, 139 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
135 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, 140 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
136 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 141 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
137 MPC85xx_PERFMON, MPC85xx_DUART, 142 MPC85xx_PERFMON, MPC85xx_DUART,
143 MPC85xx_MDIO,
138 }, 144 },
139 }, 145 },
140 { 146 {
141 .ppc_sys_name = "8547E", 147 .ppc_sys_name = "8547E",
142 .mask = 0xFFFF00F0, 148 .mask = 0xFFFF00F0,
143 .value = 0x80390010, 149 .value = 0x80390010,
144 .num_devices = 13, 150 .num_devices = 14,
145 .device_list = (enum ppc_sys_devices[]) 151 .device_list = (enum ppc_sys_devices[])
146 { 152 {
147 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, 153 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
148 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, 154 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
149 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 155 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
150 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, 156 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
157 MPC85xx_MDIO,
151 }, 158 },
152 }, 159 },
153 { 160 {
154 .ppc_sys_name = "8547", 161 .ppc_sys_name = "8547",
155 .mask = 0xFFFF00F0, 162 .mask = 0xFFFF00F0,
156 .value = 0x80310010, 163 .value = 0x80310010,
157 .num_devices = 12, 164 .num_devices = 13,
158 .device_list = (enum ppc_sys_devices[]) 165 .device_list = (enum ppc_sys_devices[])
159 { 166 {
160 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, 167 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
161 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, 168 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
162 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 169 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
163 MPC85xx_PERFMON, MPC85xx_DUART, 170 MPC85xx_PERFMON, MPC85xx_DUART,
171 MPC85xx_MDIO,
164 }, 172 },
165 }, 173 },
166 { 174 {
167 .ppc_sys_name = "8545E", 175 .ppc_sys_name = "8545E",
168 .mask = 0xFFFF00F0, 176 .mask = 0xFFFF00F0,
169 .value = 0x80390010, 177 .value = 0x80390010,
170 .num_devices = 11, 178 .num_devices = 12,
171 .device_list = (enum ppc_sys_devices[]) 179 .device_list = (enum ppc_sys_devices[])
172 { 180 {
173 MPC85xx_eTSEC1, MPC85xx_eTSEC2, 181 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
174 MPC85xx_IIC1, MPC85xx_IIC2, 182 MPC85xx_IIC1, MPC85xx_IIC2,
175 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 183 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
176 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, 184 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
185 MPC85xx_MDIO,
177 }, 186 },
178 }, 187 },
179 { 188 {
180 .ppc_sys_name = "8545", 189 .ppc_sys_name = "8545",
181 .mask = 0xFFFF00F0, 190 .mask = 0xFFFF00F0,
182 .value = 0x80310010, 191 .value = 0x80310010,
183 .num_devices = 10, 192 .num_devices = 11,
184 .device_list = (enum ppc_sys_devices[]) 193 .device_list = (enum ppc_sys_devices[])
185 { 194 {
186 MPC85xx_eTSEC1, MPC85xx_eTSEC2, 195 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
187 MPC85xx_IIC1, MPC85xx_IIC2, 196 MPC85xx_IIC1, MPC85xx_IIC2,
188 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 197 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
189 MPC85xx_PERFMON, MPC85xx_DUART, 198 MPC85xx_PERFMON, MPC85xx_DUART,
199 MPC85xx_MDIO,
190 }, 200 },
191 }, 201 },
192 { 202 {
193 .ppc_sys_name = "8543E", 203 .ppc_sys_name = "8543E",
194 .mask = 0xFFFF00F0, 204 .mask = 0xFFFF00F0,
195 .value = 0x803A0010, 205 .value = 0x803A0010,
196 .num_devices = 11, 206 .num_devices = 12,
197 .device_list = (enum ppc_sys_devices[]) 207 .device_list = (enum ppc_sys_devices[])
198 { 208 {
199 MPC85xx_eTSEC1, MPC85xx_eTSEC2, 209 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
200 MPC85xx_IIC1, MPC85xx_IIC2, 210 MPC85xx_IIC1, MPC85xx_IIC2,
201 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 211 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
202 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, 212 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
213 MPC85xx_MDIO,
203 }, 214 },
204 }, 215 },
205 { 216 {
206 .ppc_sys_name = "8543", 217 .ppc_sys_name = "8543",
207 .mask = 0xFFFF00F0, 218 .mask = 0xFFFF00F0,
208 .value = 0x80320010, 219 .value = 0x80320010,
209 .num_devices = 10, 220 .num_devices = 11,
210 .device_list = (enum ppc_sys_devices[]) 221 .device_list = (enum ppc_sys_devices[])
211 { 222 {
212 MPC85xx_eTSEC1, MPC85xx_eTSEC2, 223 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
213 MPC85xx_IIC1, MPC85xx_IIC2, 224 MPC85xx_IIC1, MPC85xx_IIC2,
214 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 225 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
215 MPC85xx_PERFMON, MPC85xx_DUART, 226 MPC85xx_PERFMON, MPC85xx_DUART,
227 MPC85xx_MDIO,
216 }, 228 },
217 }, 229 },
218 { /* default match */ 230 { /* default match */