diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2006-07-01 22:29:22 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-02 16:58:48 -0400 |
commit | bc59d2800d535ff36dc9e6c5328b4a075076bbaa (patch) | |
tree | fc2c82e64004a769226b9de38184212bd2e351d9 /arch/ppc | |
parent | 6714465e83e784d65d0f4dbab7f2238574febfce (diff) |
[PATCH] irq-flags: PPC: Use the new IRQF_ constants
Use the new IRQF_ constants and remove the SA_INTERRUPT define
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc')
-rw-r--r-- | arch/ppc/8260_io/fcc_enet.c | 2 | ||||
-rw-r--r-- | arch/ppc/platforms/85xx/mpc8560_ads.c | 2 | ||||
-rw-r--r-- | arch/ppc/platforms/85xx/mpc85xx_cds_common.c | 2 | ||||
-rw-r--r-- | arch/ppc/platforms/85xx/stx_gp3.c | 2 | ||||
-rw-r--r-- | arch/ppc/platforms/85xx/tqm85xx.c | 2 | ||||
-rw-r--r-- | arch/ppc/platforms/hdpu.c | 4 | ||||
-rw-r--r-- | arch/ppc/platforms/radstone_ppc7d.c | 2 | ||||
-rw-r--r-- | arch/ppc/platforms/sbc82xx.c | 2 | ||||
-rw-r--r-- | arch/ppc/syslib/gt64260_pic.c | 6 | ||||
-rw-r--r-- | arch/ppc/syslib/ibm440gx_common.c | 2 | ||||
-rw-r--r-- | arch/ppc/syslib/m82xx_pci.c | 2 | ||||
-rw-r--r-- | arch/ppc/syslib/mv64360_pic.c | 8 | ||||
-rw-r--r-- | arch/ppc/syslib/open_pic.c | 15 |
13 files changed, 27 insertions, 24 deletions
diff --git a/arch/ppc/8260_io/fcc_enet.c b/arch/ppc/8260_io/fcc_enet.c index cd5f3faa4b20..e347fe88316d 100644 --- a/arch/ppc/8260_io/fcc_enet.c +++ b/arch/ppc/8260_io/fcc_enet.c | |||
@@ -2116,7 +2116,7 @@ init_fcc_startup(fcc_info_t *fip, struct net_device *dev) | |||
2116 | 2116 | ||
2117 | #ifdef PHY_INTERRUPT | 2117 | #ifdef PHY_INTERRUPT |
2118 | #ifdef CONFIG_ADS8272 | 2118 | #ifdef CONFIG_ADS8272 |
2119 | if (request_irq(PHY_INTERRUPT, mii_link_interrupt, SA_SHIRQ, | 2119 | if (request_irq(PHY_INTERRUPT, mii_link_interrupt, IRQF_SHARED, |
2120 | "mii", dev) < 0) | 2120 | "mii", dev) < 0) |
2121 | printk(KERN_CRIT "Can't get MII IRQ %d\n", PHY_INTERRUPT); | 2121 | printk(KERN_CRIT "Can't get MII IRQ %d\n", PHY_INTERRUPT); |
2122 | #else | 2122 | #else |
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c index 026ace320729..d90cd24d018e 100644 --- a/arch/ppc/platforms/85xx/mpc8560_ads.c +++ b/arch/ppc/platforms/85xx/mpc8560_ads.c | |||
@@ -131,7 +131,7 @@ static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs) | |||
131 | 131 | ||
132 | static struct irqaction cpm2_irqaction = { | 132 | static struct irqaction cpm2_irqaction = { |
133 | .handler = cpm2_cascade, | 133 | .handler = cpm2_cascade, |
134 | .flags = SA_INTERRUPT, | 134 | .flags = IRQF_DISABLED, |
135 | .mask = CPU_MASK_NONE, | 135 | .mask = CPU_MASK_NONE, |
136 | .name = "cpm2_cascade", | 136 | .name = "cpm2_cascade", |
137 | }; | 137 | }; |
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c index 139cf0d00855..75204588a3e7 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c +++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c | |||
@@ -136,7 +136,7 @@ static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs) | |||
136 | 136 | ||
137 | static struct irqaction cpm2_irqaction = { | 137 | static struct irqaction cpm2_irqaction = { |
138 | .handler = cpm2_cascade, | 138 | .handler = cpm2_cascade, |
139 | .flags = SA_INTERRUPT, | 139 | .flags = IRQF_DISABLED, |
140 | .mask = CPU_MASK_NONE, | 140 | .mask = CPU_MASK_NONE, |
141 | .name = "cpm2_cascade", | 141 | .name = "cpm2_cascade", |
142 | }; | 142 | }; |
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c index 224612412cbe..495aa79bb3a1 100644 --- a/arch/ppc/platforms/85xx/stx_gp3.c +++ b/arch/ppc/platforms/85xx/stx_gp3.c | |||
@@ -166,7 +166,7 @@ static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs) | |||
166 | 166 | ||
167 | static struct irqaction cpm2_irqaction = { | 167 | static struct irqaction cpm2_irqaction = { |
168 | .handler = cpm2_cascade, | 168 | .handler = cpm2_cascade, |
169 | .flags = SA_INTERRUPT, | 169 | .flags = IRQF_DISABLED, |
170 | .mask = CPU_MASK_NONE, | 170 | .mask = CPU_MASK_NONE, |
171 | .name = "cpm2_cascade", | 171 | .name = "cpm2_cascade", |
172 | }; | 172 | }; |
diff --git a/arch/ppc/platforms/85xx/tqm85xx.c b/arch/ppc/platforms/85xx/tqm85xx.c index 1c90f113cc8f..189ed4175f9f 100644 --- a/arch/ppc/platforms/85xx/tqm85xx.c +++ b/arch/ppc/platforms/85xx/tqm85xx.c | |||
@@ -190,7 +190,7 @@ static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs) | |||
190 | 190 | ||
191 | static struct irqaction cpm2_irqaction = { | 191 | static struct irqaction cpm2_irqaction = { |
192 | .handler = cpm2_cascade, | 192 | .handler = cpm2_cascade, |
193 | .flags = SA_INTERRUPT, | 193 | .flags = IRQF_DISABLED, |
194 | .mask = CPU_MASK_NONE, | 194 | .mask = CPU_MASK_NONE, |
195 | .name = "cpm2_cascade", | 195 | .name = "cpm2_cascade", |
196 | }; | 196 | }; |
diff --git a/arch/ppc/platforms/hdpu.c b/arch/ppc/platforms/hdpu.c index 71af4b488621..e0f112a1fd0b 100644 --- a/arch/ppc/platforms/hdpu.c +++ b/arch/ppc/platforms/hdpu.c | |||
@@ -837,7 +837,7 @@ static void smp_hdpu_setup_cpu(int cpu_nr) | |||
837 | mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff); | 837 | mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff); |
838 | mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff); | 838 | mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff); |
839 | request_irq(60, hdpu_smp_cpu0_int_handler, | 839 | request_irq(60, hdpu_smp_cpu0_int_handler, |
840 | SA_INTERRUPT, hdpu_smp0, 0); | 840 | IRQF_DISABLED, hdpu_smp0, 0); |
841 | } | 841 | } |
842 | 842 | ||
843 | if (cpu_nr == 1) { | 843 | if (cpu_nr == 1) { |
@@ -857,7 +857,7 @@ static void smp_hdpu_setup_cpu(int cpu_nr) | |||
857 | mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0); | 857 | mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0); |
858 | mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff); | 858 | mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff); |
859 | request_irq(28, hdpu_smp_cpu1_int_handler, | 859 | request_irq(28, hdpu_smp_cpu1_int_handler, |
860 | SA_INTERRUPT, hdpu_smp1, 0); | 860 | IRQF_DISABLED, hdpu_smp1, 0); |
861 | } | 861 | } |
862 | 862 | ||
863 | } | 863 | } |
diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c index 97d6c21091e0..3bb530af0297 100644 --- a/arch/ppc/platforms/radstone_ppc7d.c +++ b/arch/ppc/platforms/radstone_ppc7d.c | |||
@@ -1310,7 +1310,7 @@ static void ppc7d_init2(void) | |||
1310 | 1310 | ||
1311 | /* Hook up i8259 interrupt which is connected to GPP28 */ | 1311 | /* Hook up i8259 interrupt which is connected to GPP28 */ |
1312 | request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr, | 1312 | request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr, |
1313 | SA_INTERRUPT, "I8259 (GPP28) interrupt", (void *)0); | 1313 | IRQF_DISABLED, "I8259 (GPP28) interrupt", (void *)0); |
1314 | 1314 | ||
1315 | /* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */ | 1315 | /* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */ |
1316 | spin_lock_irqsave(&mv64x60_lock, flags); | 1316 | spin_lock_irqsave(&mv64x60_lock, flags); |
diff --git a/arch/ppc/platforms/sbc82xx.c b/arch/ppc/platforms/sbc82xx.c index 8cff1e303349..60b769c7f3fc 100644 --- a/arch/ppc/platforms/sbc82xx.c +++ b/arch/ppc/platforms/sbc82xx.c | |||
@@ -145,7 +145,7 @@ static irqreturn_t sbc82xx_i8259_demux(int irq, void *dev_id, struct pt_regs *re | |||
145 | 145 | ||
146 | static struct irqaction sbc82xx_i8259_irqaction = { | 146 | static struct irqaction sbc82xx_i8259_irqaction = { |
147 | .handler = sbc82xx_i8259_demux, | 147 | .handler = sbc82xx_i8259_demux, |
148 | .flags = SA_INTERRUPT, | 148 | .flags = IRQF_DISABLED, |
149 | .mask = CPU_MASK_NONE, | 149 | .mask = CPU_MASK_NONE, |
150 | .name = "i8259 demux", | 150 | .name = "i8259 demux", |
151 | }; | 151 | }; |
diff --git a/arch/ppc/syslib/gt64260_pic.c b/arch/ppc/syslib/gt64260_pic.c index 91096b38ae70..7fd550a7d586 100644 --- a/arch/ppc/syslib/gt64260_pic.c +++ b/arch/ppc/syslib/gt64260_pic.c | |||
@@ -297,7 +297,7 @@ gt64260_register_hdlrs(void) | |||
297 | 297 | ||
298 | /* Register CPU interface error interrupt handler */ | 298 | /* Register CPU interface error interrupt handler */ |
299 | if ((rc = request_irq(MV64x60_IRQ_CPU_ERR, | 299 | if ((rc = request_irq(MV64x60_IRQ_CPU_ERR, |
300 | gt64260_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0))) | 300 | gt64260_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, 0))) |
301 | printk(KERN_WARNING "Can't register cpu error handler: %d", rc); | 301 | printk(KERN_WARNING "Can't register cpu error handler: %d", rc); |
302 | 302 | ||
303 | mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); | 303 | mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); |
@@ -305,7 +305,7 @@ gt64260_register_hdlrs(void) | |||
305 | 305 | ||
306 | /* Register PCI 0 error interrupt handler */ | 306 | /* Register PCI 0 error interrupt handler */ |
307 | if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler, | 307 | if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler, |
308 | SA_INTERRUPT, PCI0_INTR_STR, (void *)0))) | 308 | IRQF_DISABLED, PCI0_INTR_STR, (void *)0))) |
309 | printk(KERN_WARNING "Can't register pci 0 error handler: %d", | 309 | printk(KERN_WARNING "Can't register pci 0 error handler: %d", |
310 | rc); | 310 | rc); |
311 | 311 | ||
@@ -314,7 +314,7 @@ gt64260_register_hdlrs(void) | |||
314 | 314 | ||
315 | /* Register PCI 1 error interrupt handler */ | 315 | /* Register PCI 1 error interrupt handler */ |
316 | if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler, | 316 | if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler, |
317 | SA_INTERRUPT, PCI1_INTR_STR, (void *)1))) | 317 | IRQF_DISABLED, PCI1_INTR_STR, (void *)1))) |
318 | printk(KERN_WARNING "Can't register pci 1 error handler: %d", | 318 | printk(KERN_WARNING "Can't register pci 1 error handler: %d", |
319 | rc); | 319 | rc); |
320 | 320 | ||
diff --git a/arch/ppc/syslib/ibm440gx_common.c b/arch/ppc/syslib/ibm440gx_common.c index 0440d8f4ce16..4b77e6c8c87f 100644 --- a/arch/ppc/syslib/ibm440gx_common.c +++ b/arch/ppc/syslib/ibm440gx_common.c | |||
@@ -149,7 +149,7 @@ void __init ibm440gx_l2c_enable(void){ | |||
149 | unsigned long flags; | 149 | unsigned long flags; |
150 | 150 | ||
151 | /* Install error handler */ | 151 | /* Install error handler */ |
152 | if (request_irq(87, l2c_error_handler, SA_INTERRUPT, "L2C", 0) < 0){ | 152 | if (request_irq(87, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0){ |
153 | printk(KERN_ERR "Cannot install L2C error handler, cache is not enabled\n"); | 153 | printk(KERN_ERR "Cannot install L2C error handler, cache is not enabled\n"); |
154 | return; | 154 | return; |
155 | } | 155 | } |
diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c index 63fa5b313396..d3fa264e179e 100644 --- a/arch/ppc/syslib/m82xx_pci.c +++ b/arch/ppc/syslib/m82xx_pci.c | |||
@@ -139,7 +139,7 @@ pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs) | |||
139 | 139 | ||
140 | static struct irqaction pq2pci_irqaction = { | 140 | static struct irqaction pq2pci_irqaction = { |
141 | .handler = pq2pci_irq_demux, | 141 | .handler = pq2pci_irq_demux, |
142 | .flags = SA_INTERRUPT, | 142 | .flags = IRQF_DISABLED, |
143 | .mask = CPU_MASK_NONE, | 143 | .mask = CPU_MASK_NONE, |
144 | .name = "PQ2 PCI cascade", | 144 | .name = "PQ2 PCI cascade", |
145 | }; | 145 | }; |
diff --git a/arch/ppc/syslib/mv64360_pic.c b/arch/ppc/syslib/mv64360_pic.c index a4244d468381..3f6d162f87cf 100644 --- a/arch/ppc/syslib/mv64360_pic.c +++ b/arch/ppc/syslib/mv64360_pic.c | |||
@@ -380,7 +380,7 @@ mv64360_register_hdlrs(void) | |||
380 | /* Clear old errors and register CPU interface error intr handler */ | 380 | /* Clear old errors and register CPU interface error intr handler */ |
381 | mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0); | 381 | mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0); |
382 | if ((rc = request_irq(MV64x60_IRQ_CPU_ERR + mv64360_irq_base, | 382 | if ((rc = request_irq(MV64x60_IRQ_CPU_ERR + mv64360_irq_base, |
383 | mv64360_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0))) | 383 | mv64360_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, 0))) |
384 | printk(KERN_WARNING "Can't register cpu error handler: %d", rc); | 384 | printk(KERN_WARNING "Can't register cpu error handler: %d", rc); |
385 | 385 | ||
386 | mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); | 386 | mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); |
@@ -389,14 +389,14 @@ mv64360_register_hdlrs(void) | |||
389 | /* Clear old errors and register internal SRAM error intr handler */ | 389 | /* Clear old errors and register internal SRAM error intr handler */ |
390 | mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0); | 390 | mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0); |
391 | if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR + mv64360_irq_base, | 391 | if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR + mv64360_irq_base, |
392 | mv64360_sram_error_int_handler,SA_INTERRUPT,SRAM_INTR_STR, 0))) | 392 | mv64360_sram_error_int_handler,IRQF_DISABLED,SRAM_INTR_STR, 0))) |
393 | printk(KERN_WARNING "Can't register SRAM error handler: %d",rc); | 393 | printk(KERN_WARNING "Can't register SRAM error handler: %d",rc); |
394 | 394 | ||
395 | /* Clear old errors and register PCI 0 error intr handler */ | 395 | /* Clear old errors and register PCI 0 error intr handler */ |
396 | mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0); | 396 | mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0); |
397 | if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base, | 397 | if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base, |
398 | mv64360_pci_error_int_handler, | 398 | mv64360_pci_error_int_handler, |
399 | SA_INTERRUPT, PCI0_INTR_STR, (void *)0))) | 399 | IRQF_DISABLED, PCI0_INTR_STR, (void *)0))) |
400 | printk(KERN_WARNING "Can't register pci 0 error handler: %d", | 400 | printk(KERN_WARNING "Can't register pci 0 error handler: %d", |
401 | rc); | 401 | rc); |
402 | 402 | ||
@@ -411,7 +411,7 @@ mv64360_register_hdlrs(void) | |||
411 | mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0); | 411 | mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0); |
412 | if ((rc = request_irq(MV64360_IRQ_PCI1 + mv64360_irq_base, | 412 | if ((rc = request_irq(MV64360_IRQ_PCI1 + mv64360_irq_base, |
413 | mv64360_pci_error_int_handler, | 413 | mv64360_pci_error_int_handler, |
414 | SA_INTERRUPT, PCI1_INTR_STR, (void *)1))) | 414 | IRQF_DISABLED, PCI1_INTR_STR, (void *)1))) |
415 | printk(KERN_WARNING "Can't register pci 1 error handler: %d", | 415 | printk(KERN_WARNING "Can't register pci 1 error handler: %d", |
416 | rc); | 416 | rc); |
417 | 417 | ||
diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c index 08973663fa24..aa0b95788705 100644 --- a/arch/ppc/syslib/open_pic.c +++ b/arch/ppc/syslib/open_pic.c | |||
@@ -575,18 +575,21 @@ void openpic_request_IPIs(void) | |||
575 | if (OpenPIC == NULL) | 575 | if (OpenPIC == NULL) |
576 | return; | 576 | return; |
577 | 577 | ||
578 | /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */ | 578 | /* |
579 | * IPIs are marked IRQF_DISABLED as they must run with irqs | ||
580 | * disabled | ||
581 | */ | ||
579 | request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset, | 582 | request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset, |
580 | openpic_ipi_action, SA_INTERRUPT, | 583 | openpic_ipi_action, IRQF_DISABLED, |
581 | "IPI0 (call function)", NULL); | 584 | "IPI0 (call function)", NULL); |
582 | request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1, | 585 | request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1, |
583 | openpic_ipi_action, SA_INTERRUPT, | 586 | openpic_ipi_action, IRQF_DISABLED, |
584 | "IPI1 (reschedule)", NULL); | 587 | "IPI1 (reschedule)", NULL); |
585 | request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2, | 588 | request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2, |
586 | openpic_ipi_action, SA_INTERRUPT, | 589 | openpic_ipi_action, IRQF_DISABLED, |
587 | "IPI2 (invalidate tlb)", NULL); | 590 | "IPI2 (invalidate tlb)", NULL); |
588 | request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3, | 591 | request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3, |
589 | openpic_ipi_action, SA_INTERRUPT, | 592 | openpic_ipi_action, IRQF_DISABLED, |
590 | "IPI3 (xmon break)", NULL); | 593 | "IPI3 (xmon break)", NULL); |
591 | 594 | ||
592 | for ( i = 0; i < OPENPIC_NUM_IPI ; i++ ) | 595 | for ( i = 0; i < OPENPIC_NUM_IPI ; i++ ) |
@@ -691,7 +694,7 @@ openpic_init_nmi_irq(u_int irq) | |||
691 | 694 | ||
692 | static struct irqaction openpic_cascade_irqaction = { | 695 | static struct irqaction openpic_cascade_irqaction = { |
693 | .handler = no_action, | 696 | .handler = no_action, |
694 | .flags = SA_INTERRUPT, | 697 | .flags = IRQF_DISABLED, |
695 | .mask = CPU_MASK_NONE, | 698 | .mask = CPU_MASK_NONE, |
696 | }; | 699 | }; |
697 | 700 | ||