Auto-update from upstream

8 files changed, 86 insertions, 79 deletions

diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile
index f3e9c534aa82..9533f8de238f 100644
--- a/arch/ppc/boot/simple/Makefile
+++ b/arch/ppc/boot/simple/Makefile
@@ -190,6 +190,8 @@ boot-$(CONFIG_REDWOOD_5)	+= embed_config.o
 boot-$(CONFIG_REDWOOD_6)        += embed_config.o
 boot-$(CONFIG_8xx)              += embed_config.o
 boot-$(CONFIG_8260)             += embed_config.o
+boot-$(CONFIG_EP405)            += embed_config.o
+boot-$(CONFIG_XILINX_ML300)     += embed_config.o
 boot-$(CONFIG_BSEIP)            += iic.o
 boot-$(CONFIG_MBX)              += iic.o pci.o qspan_pci.o
 boot-$(CONFIG_MV64X60)          += misc-mv64x60.o
diff --git a/arch/ppc/kernel/idle.c b/arch/ppc/kernel/idle.c
index 821a75e45602..1be3ca5bae40 100644
--- a/arch/ppc/kernel/idle.c
+++ b/arch/ppc/kernel/idle.c
@@ -37,7 +37,6 @@
 void default_idle(void)
 {
         void (*powersave)(void);
-        int cpu = smp_processor_id();
 
         powersave = ppc_md.power_save;
 
@@ -47,7 +46,8 @@ void default_idle(void)
 #ifdef CONFIG_SMP
                 else {
                         set_thread_flag(TIF_POLLING_NRFLAG);
-                        while (!need_resched() && !cpu_is_offline(cpu))
+                        while (!need_resched() &&
+                                        !cpu_is_offline(smp_processor_id()))
                                 barrier();
                         clear_thread_flag(TIF_POLLING_NRFLAG);
                 }
diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c
index 956f45e4ef97..d24c09ee7b18 100644
--- a/arch/ppc/platforms/4xx/ibm440gx.c
+++ b/arch/ppc/platforms/4xx/ibm440gx.c
@@ -58,7 +58,6 @@ static struct ocp_func_emac_data ibm440gx_emac2_def = {
         .wol_irq        = 65,           /* WOL interrupt number */
         .mdio_idx       = -1,           /* No shared MDIO */
         .tah_idx        = 0,            /* TAH device index */
-        .jumbo          = 1,            /* Jumbo frames supported */
 };
 
 static struct ocp_func_emac_data ibm440gx_emac3_def = {
@@ -72,7 +71,6 @@ static struct ocp_func_emac_data ibm440gx_emac3_def = {
         .wol_irq        = 67,           /* WOL interrupt number */
         .mdio_idx       = -1,           /* No shared MDIO */
         .tah_idx        = 1,            /* TAH device index */
-        .jumbo          = 1,            /* Jumbo frames supported */
 };
 OCP_SYSFS_EMAC_DATA()
 
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
index feb17e41ef69..71a0117d3597 100644
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ b/arch/ppc/platforms/4xx/ibm440sp.c
@@ -31,7 +31,6 @@ static struct ocp_func_emac_data ibm440sp_emac0_def = {
         .wol_irq        = 61,           /* WOL interrupt number */
         .mdio_idx       = -1,           /* No shared MDIO */
         .tah_idx        = -1,           /* No TAH */
-        .jumbo          = 1,            /* Jumbo frames supported */
 };
 OCP_SYSFS_EMAC_DATA()
 
diff --git a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
index d44cc991179f..7ed52dc340c9 100644
--- a/arch/ppc/platforms/lite5200.c
+++ b/arch/ppc/platforms/lite5200.c
@@ -196,8 +196,10 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
         mpc52xx_set_bat();
 
         /* No ISA bus by default */
+#ifdef CONFIG_PCI
         isa_io_base             = 0;
         isa_mem_base            = 0;
+#endif
 
         /* Powersave */
         /* This is provided as an example on how to do it. But you
diff --git a/arch/ppc/platforms/mpc5200.c b/arch/ppc/platforms/mpc5200.c
deleted file mode 100644
index a58db438c162..000000000000
--- a/arch/ppc/platforms/mpc5200.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * arch/ppc/platforms/mpc5200.c
- *
- * OCP Definitions for the boards based on MPC5200 processor. Contains
- * definitions for every common peripherals. (Mostly all but PSCs)
- * 
- * Maintainer : Sylvain Munaut <tnt@246tNt.com>
- *
- * Copyright 2004 Sylvain Munaut <tnt@246tNt.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <asm/ocp.h>
-#include <asm/mpc52xx.h>
-
-
-static struct ocp_fs_i2c_data mpc5200_i2c_def = {
-        .flags  = FS_I2C_CLOCK_5200,
-};
-
-
-/* Here is the core_ocp struct.
- * With all the devices common to all board. Even if port multiplexing is
- * not setup for them (if the user don't want them, just don't select the
- * config option). The potentially conflicting devices (like PSCs) goes in
- * board specific file.
- */
-struct ocp_def core_ocp[] = {
-        {
-                .vendor         = OCP_VENDOR_FREESCALE,
-                .function       = OCP_FUNC_IIC,
-                .index          = 0,
-                .paddr          = MPC52xx_I2C1,
-                .irq            = OCP_IRQ_NA,   /* MPC52xx_IRQ_I2C1 - Buggy */
-                .pm             = OCP_CPM_NA,
-                .additions      = &mpc5200_i2c_def,
-        },
-        {
-                .vendor         = OCP_VENDOR_FREESCALE,
-                .function       = OCP_FUNC_IIC,
-                .index          = 1,
-                .paddr          = MPC52xx_I2C2,
-                .irq            = OCP_IRQ_NA,   /* MPC52xx_IRQ_I2C2 - Buggy */
-                .pm             = OCP_CPM_NA,
-                .additions      = &mpc5200_i2c_def,
-        },
-        {       /* Terminating entry */
-                .vendor         = OCP_VENDOR_INVALID
-        }
-};
diff --git a/arch/ppc/syslib/mpc52xx_pci.c b/arch/ppc/syslib/mpc52xx_pci.c
index 4ac19080eb85..313c96ec7eb1 100644
--- a/arch/ppc/syslib/mpc52xx_pci.c
+++ b/arch/ppc/syslib/mpc52xx_pci.c
@@ -24,6 +24,12 @@
 #include <asm/machdep.h>
 
 
+/* This macro is defined to activate the workaround for the bug
+   435 of the MPC5200 (L25R). With it activated, we don't do any
+   32 bits configuration access during type-1 cycles */
+#define MPC5200_BUG_435_WORKAROUND
+
+
 static int
 mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                                 int offset, int len, u32 *val)
@@ -40,17 +46,39 @@ mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                 ((bus->number - hose->bus_offset) << 16) |
                 (devfn << 8) |
                 (offset & 0xfc));
+        mb();
+
+#ifdef MPC5200_BUG_435_WORKAROUND
+        if (bus->number != hose->bus_offset) {
+                switch (len) {
+                        case 1:
+                                value = in_8(((u8 __iomem *)hose->cfg_data) + (offset & 3));
+                                break;
+                        case 2:
+                                value = in_le16(((u16 __iomem *)hose->cfg_data) + ((offset>>1) & 1));
+                                break;
+
+                        default:
+                                value = in_le16((u16 __iomem *)hose->cfg_data) |
+                                        (in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16);
+                                break;
+                }
+        }
+        else
+#endif
+        {
+                value = in_le32(hose->cfg_data);
 
-        value = in_le32(hose->cfg_data);
-
-        if (len != 4) {
-                value >>= ((offset & 0x3) << 3);
-                value &= 0xffffffff >> (32 - (len << 3));
+                if (len != 4) {
+                        value >>= ((offset & 0x3) << 3);
+                        value &= 0xffffffff >> (32 - (len << 3));
+                }
         }
 
         *val = value;
 
         out_be32(hose->cfg_addr, 0);
+        mb();
 
         return PCIBIOS_SUCCESSFUL;
 }
@@ -71,21 +99,48 @@ mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
                 ((bus->number - hose->bus_offset) << 16) |
                 (devfn << 8) |
                 (offset & 0xfc));
+        mb();
+
+#ifdef MPC5200_BUG_435_WORKAROUND
+        if (bus->number != hose->bus_offset) {
+                switch (len) {
+                        case 1:
+                                out_8(((u8 __iomem *)hose->cfg_data) +
+                                        (offset & 3), val);
+                                break;
+                        case 2:
+                                out_le16(((u16 __iomem *)hose->cfg_data) +
+                                        ((offset>>1) & 1), val);
+                                break;
+
+                        default:
+                                out_le16((u16 __iomem *)hose->cfg_data,
+                                        (u16)val);
+                                out_le16(((u16 __iomem *)hose->cfg_data) + 1,
+                                        (u16)(val>>16));
+                                break;
+                }
+        }
+        else
+#endif
+        {
+                if (len != 4) {
+                        value = in_le32(hose->cfg_data);
 
-        if (len != 4) {
-                value = in_le32(hose->cfg_data);
+                        offset = (offset & 0x3) << 3;
+                        mask = (0xffffffff >> (32 - (len << 3)));
+                        mask <<= offset;
 
-                offset = (offset & 0x3) << 3;
-                mask = (0xffffffff >> (32 - (len << 3)));
-                mask <<= offset;
+                        value &= ~mask;
+                        val = value | ((val << offset) & mask);
+                }
 
-                value &= ~mask;
-                val = value | ((val << offset) & mask);
+                out_le32(hose->cfg_data, val);
         }
-
-        out_le32(hose->cfg_data, val);
+        mb();
 
         out_be32(hose->cfg_addr, 0);
+        mb();
 
         return PCIBIOS_SUCCESSFUL;
 }
@@ -99,9 +154,12 @@ static struct pci_ops mpc52xx_pci_ops = {
 static void __init
 mpc52xx_pci_setup(struct mpc52xx_pci __iomem *pci_regs)
 {
+        u32 tmp;
 
         /* Setup control regs */
-                /* Nothing to do afaik */
+        tmp = in_be32(&pci_regs->scr);
+        tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+        out_be32(&pci_regs->scr, tmp);
 
         /* Setup windows */
         out_be32(&pci_regs->iw0btar, MPC52xx_PCI_IWBTAR_TRANSLATION(
@@ -142,16 +200,15 @@ mpc52xx_pci_setup(struct mpc52xx_pci __iomem *pci_regs)
         /* Not necessary and can be a bad thing if for example the bootloader
            is displaying a splash screen or ... Just left here for
            documentation purpose if anyone need it */
-#if 0
-        u32 tmp;
         tmp = in_be32(&pci_regs->gscr);
+#if 0
         out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR);
         udelay(50);
-        out_be32(&pci_regs->gscr, tmp);
 #endif
+        out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR);
 }
 
-static void __init
+static void
 mpc52xx_pci_fixup_resources(struct pci_dev *dev)
 {
         int i;
diff --git a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c
index bb2374585a7b..a4a4b02227df 100644
--- a/arch/ppc/syslib/mpc52xx_setup.c
+++ b/arch/ppc/syslib/mpc52xx_setup.c
@@ -84,9 +84,11 @@ mpc52xx_set_bat(void)
 void __init
 mpc52xx_map_io(void)
 {
-        /* Here we only map the MBAR */
+        /* Here we map the MBAR and the whole upper zone. MBAR is only
+           64k but we can't map only 64k with BATs. Map the whole
+           0xf0000000 range is ok and helps eventual lpb devices placed there */
         io_block_mapping(
-                MPC52xx_MBAR_VIRT, MPC52xx_MBAR, MPC52xx_MBAR_SIZE, _PAGE_IO);
+                MPC52xx_MBAR_VIRT, MPC52xx_MBAR, 0x10000000, _PAGE_IO);
 }