aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ppc
diff options
context:
space:
mode:
authorPaul Mackerras <paulus@samba.org>2006-08-31 01:45:48 -0400
committerPaul Mackerras <paulus@samba.org>2006-08-31 01:45:48 -0400
commitaa43f77939c97bf9d3580c6a5e71a5a40290e451 (patch)
tree095c0b8b3da4b6554a3f8ef4b39240a5d9216d4d /arch/ppc
parent2818c5dec5e28d65d52afbb7695bbbafe6377ee5 (diff)
parent4c15343167b5febe7bb0ba96aad5bef42ae94d3b (diff)
Merge branch 'merge'
Diffstat (limited to 'arch/ppc')
-rw-r--r--arch/ppc/kernel/smp-tbsync.c7
-rw-r--r--arch/ppc/platforms/85xx/mpc8560_ads.c89
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_ads_common.h19
-rw-r--r--arch/ppc/platforms/mpc8272ads_setup.c154
-rw-r--r--arch/ppc/platforms/mpc866ads_setup.c192
-rw-r--r--arch/ppc/platforms/mpc885ads_setup.c175
-rw-r--r--arch/ppc/platforms/pq2ads_pd.h82
-rw-r--r--arch/ppc/syslib/Makefile2
-rw-r--r--arch/ppc/syslib/ipic.c646
-rw-r--r--arch/ppc/syslib/ipic.h47
-rw-r--r--arch/ppc/syslib/mpc85xx_devices.c89
-rw-r--r--arch/ppc/syslib/mpc8xx_devices.c8
-rw-r--r--arch/ppc/syslib/mpc8xx_sys.c6
-rw-r--r--arch/ppc/syslib/pq2_devices.c5
-rw-r--r--arch/ppc/syslib/pq2_sys.c3
15 files changed, 1158 insertions, 366 deletions
diff --git a/arch/ppc/kernel/smp-tbsync.c b/arch/ppc/kernel/smp-tbsync.c
index 1576758debaf..d0cf3f86931d 100644
--- a/arch/ppc/kernel/smp-tbsync.c
+++ b/arch/ppc/kernel/smp-tbsync.c
@@ -47,8 +47,9 @@ void __devinit
47smp_generic_take_timebase( void ) 47smp_generic_take_timebase( void )
48{ 48{
49 int cmd, tbl, tbu; 49 int cmd, tbl, tbu;
50 unsigned long flags;
50 51
51 local_irq_disable(); 52 local_irq_save(flags);
52 while( !running ) 53 while( !running )
53 ; 54 ;
54 rmb(); 55 rmb();
@@ -64,7 +65,7 @@ smp_generic_take_timebase( void )
64 tbu = tbsync->tbu; 65 tbu = tbsync->tbu;
65 tbsync->ack = 0; 66 tbsync->ack = 0;
66 if( cmd == kExit ) 67 if( cmd == kExit )
67 return; 68 break;
68 69
69 if( cmd == kSetAndTest ) { 70 if( cmd == kSetAndTest ) {
70 while( tbsync->handshake ) 71 while( tbsync->handshake )
@@ -77,7 +78,7 @@ smp_generic_take_timebase( void )
77 } 78 }
78 enter_contest( tbsync->mark, -1 ); 79 enter_contest( tbsync->mark, -1 );
79 } 80 }
80 local_irq_enable(); 81 local_irq_restore(flags);
81} 82}
82 83
83static int __devinit 84static int __devinit
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c
index d90cd24d018e..94badafe4ef1 100644
--- a/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -29,6 +29,7 @@
29#include <linux/initrd.h> 29#include <linux/initrd.h>
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/fsl_devices.h> 31#include <linux/fsl_devices.h>
32#include <linux/fs_enet_pd.h>
32 33
33#include <asm/system.h> 34#include <asm/system.h>
34#include <asm/pgtable.h> 35#include <asm/pgtable.h>
@@ -58,6 +59,71 @@
58 * Setup the architecture 59 * Setup the architecture
59 * 60 *
60 */ 61 */
62static void init_fcc_ioports(void)
63{
64 struct immap *immap;
65 struct io_port *io;
66 u32 tempval;
67
68 immap = cpm2_immr;
69
70 io = &immap->im_ioport;
71 /* FCC2/3 are on the ports B/C. */
72 tempval = in_be32(&io->iop_pdirb);
73 tempval &= ~PB2_DIRB0;
74 tempval |= PB2_DIRB1;
75 out_be32(&io->iop_pdirb, tempval);
76
77 tempval = in_be32(&io->iop_psorb);
78 tempval &= ~PB2_PSORB0;
79 tempval |= PB2_PSORB1;
80 out_be32(&io->iop_psorb, tempval);
81
82 tempval = in_be32(&io->iop_pparb);
83 tempval |= (PB2_DIRB0 | PB2_DIRB1);
84 out_be32(&io->iop_pparb, tempval);
85
86 tempval = in_be32(&io->iop_pdirb);
87 tempval &= ~PB3_DIRB0;
88 tempval |= PB3_DIRB1;
89 out_be32(&io->iop_pdirb, tempval);
90
91 tempval = in_be32(&io->iop_psorb);
92 tempval &= ~PB3_PSORB0;
93 tempval |= PB3_PSORB1;
94 out_be32(&io->iop_psorb, tempval);
95
96 tempval = in_be32(&io->iop_pparb);
97 tempval |= (PB3_DIRB0 | PB3_DIRB1);
98 out_be32(&io->iop_pparb, tempval);
99
100 tempval = in_be32(&io->iop_pdirc);
101 tempval |= PC3_DIRC1;
102 out_be32(&io->iop_pdirc, tempval);
103
104 tempval = in_be32(&io->iop_pparc);
105 tempval |= PC3_DIRC1;
106 out_be32(&io->iop_pparc, tempval);
107
108 /* Port C has clocks...... */
109 tempval = in_be32(&io->iop_psorc);
110 tempval &= ~(CLK_TRX);
111 out_be32(&io->iop_psorc, tempval);
112
113 tempval = in_be32(&io->iop_pdirc);
114 tempval &= ~(CLK_TRX);
115 out_be32(&io->iop_pdirc, tempval);
116 tempval = in_be32(&io->iop_pparc);
117 tempval |= (CLK_TRX);
118 out_be32(&io->iop_pparc, tempval);
119
120 /* Configure Serial Interface clock routing.
121 * First, clear all FCC bits to zero,
122 * then set the ones we want.
123 */
124 immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK);
125 immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE;
126}
61 127
62static void __init 128static void __init
63mpc8560ads_setup_arch(void) 129mpc8560ads_setup_arch(void)
@@ -66,6 +132,7 @@ mpc8560ads_setup_arch(void)
66 unsigned int freq; 132 unsigned int freq;
67 struct gianfar_platform_data *pdata; 133 struct gianfar_platform_data *pdata;
68 struct gianfar_mdio_data *mdata; 134 struct gianfar_mdio_data *mdata;
135 struct fs_platform_info *fpi;
69 136
70 cpm2_reset(); 137 cpm2_reset();
71 138
@@ -110,6 +177,28 @@ mpc8560ads_setup_arch(void)
110 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 177 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
111 } 178 }
112 179
180 init_fcc_ioports();
181 ppc_sys_device_remove(MPC85xx_CPM_FCC1);
182
183 fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2);
184 if (fpi) {
185 memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
186 fpi->bus_id = "0:02";
187 fpi->phy_addr = 2;
188 fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
189 fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1];
190 }
191
192 fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3);
193 if (fpi) {
194 memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
195 fpi->macaddr[5] += 1;
196 fpi->bus_id = "0:03";
197 fpi->phy_addr = 3;
198 fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
199 fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2];
200 }
201
113#ifdef CONFIG_BLK_DEV_INITRD 202#ifdef CONFIG_BLK_DEV_INITRD
114 if (initrd_start) 203 if (initrd_start)
115 ROOT_DEV = Root_RAM0; 204 ROOT_DEV = Root_RAM0;
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
index abf32281655d..c8c322fe3680 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
@@ -45,4 +45,23 @@ extern void mpc85xx_ads_map_io(void) __init;
45 45
46#define MPC85XX_PCI1_IO_SIZE 0x01000000 46#define MPC85XX_PCI1_IO_SIZE 0x01000000
47 47
48/* FCC1 Clock Source Configuration. These can be
49 * redefined in the board specific file.
50 * Can only choose from CLK9-12 */
51#define F1_RXCLK 12
52#define F1_TXCLK 11
53
54/* FCC2 Clock Source Configuration. These can be
55 * redefined in the board specific file.
56 * Can only choose from CLK13-16 */
57#define F2_RXCLK 13
58#define F2_TXCLK 14
59
60/* FCC3 Clock Source Configuration. These can be
61 * redefined in the board specific file.
62 * Can only choose from CLK13-16 */
63#define F3_RXCLK 15
64#define F3_TXCLK 16
65
66
48#endif /* __MACH_MPC85XX_ADS_H__ */ 67#endif /* __MACH_MPC85XX_ADS_H__ */
diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c
index abb7154de2c7..2a35fe2b9b96 100644
--- a/arch/ppc/platforms/mpc8272ads_setup.c
+++ b/arch/ppc/platforms/mpc8272ads_setup.c
@@ -56,64 +56,51 @@ static struct fs_uart_platform_info mpc8272_uart_pdata[] = {
56 }, 56 },
57}; 57};
58 58
59static struct fs_mii_bus_info mii_bus_info = { 59static struct fs_mii_bb_platform_info m82xx_mii_bb_pdata = {
60 .method = fsmii_bitbang, 60 .mdio_dat.bit = 18,
61 .id = 0, 61 .mdio_dir.bit = 18,
62 .i.bitbang = { 62 .mdc_dat.bit = 19,
63 .mdio_port = fsiop_portc, 63 .delay = 1,
64 .mdio_bit = 18,
65 .mdc_port = fsiop_portc,
66 .mdc_bit = 19,
67 .delay = 1,
68 },
69};
70
71static struct fs_platform_info mpc82xx_fcc1_pdata = {
72 .fs_no = fsid_fcc1,
73 .cp_page = CPM_CR_FCC1_PAGE,
74 .cp_block = CPM_CR_FCC1_SBLOCK,
75 .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
76 .clk_route = CMX1_CLK_ROUTE,
77 .clk_mask = CMX1_CLK_MASK,
78 .init_ioports = init_fcc1_ioports,
79
80 .phy_addr = 0,
81#ifdef PHY_INTERRUPT
82 .phy_irq = PHY_INTERRUPT,
83#else
84 .phy_irq = -1;
85#endif
86 .mem_offset = FCC1_MEM_OFFSET,
87 .bus_info = &mii_bus_info,
88 .rx_ring = 32,
89 .tx_ring = 32,
90 .rx_copybreak = 240,
91 .use_napi = 0,
92 .napi_weight = 17,
93}; 64};
94 65
95static struct fs_platform_info mpc82xx_fcc2_pdata = { 66static struct fs_platform_info mpc82xx_enet_pdata[] = {
96 .fs_no = fsid_fcc2, 67 [fsid_fcc1] = {
97 .cp_page = CPM_CR_FCC2_PAGE, 68 .fs_no = fsid_fcc1,
98 .cp_block = CPM_CR_FCC2_SBLOCK, 69 .cp_page = CPM_CR_FCC1_PAGE,
99 .clk_trx = (PC_F2RXCLK | PC_F2TXCLK), 70 .cp_block = CPM_CR_FCC1_SBLOCK,
100 .clk_route = CMX2_CLK_ROUTE, 71
101 .clk_mask = CMX2_CLK_MASK, 72 .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
102 .init_ioports = init_fcc2_ioports, 73 .clk_route = CMX1_CLK_ROUTE,
103 74 .clk_mask = CMX1_CLK_MASK,
104 .phy_addr = 3, 75 .init_ioports = init_fcc1_ioports,
105#ifdef PHY_INTERRUPT 76
106 .phy_irq = PHY_INTERRUPT, 77 .mem_offset = FCC1_MEM_OFFSET,
107#else 78
108 .phy_irq = -1; 79 .rx_ring = 32,
109#endif 80 .tx_ring = 32,
110 .mem_offset = FCC2_MEM_OFFSET, 81 .rx_copybreak = 240,
111 .bus_info = &mii_bus_info, 82 .use_napi = 0,
112 .rx_ring = 32, 83 .napi_weight = 17,
113 .tx_ring = 32, 84 .bus_id = "0:00",
114 .rx_copybreak = 240, 85 },
115 .use_napi = 0, 86 [fsid_fcc2] = {
116 .napi_weight = 17, 87 .fs_no = fsid_fcc2,
88 .cp_page = CPM_CR_FCC2_PAGE,
89 .cp_block = CPM_CR_FCC2_SBLOCK,
90 .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
91 .clk_route = CMX2_CLK_ROUTE,
92 .clk_mask = CMX2_CLK_MASK,
93 .init_ioports = init_fcc2_ioports,
94
95 .mem_offset = FCC2_MEM_OFFSET,
96
97 .rx_ring = 32,
98 .tx_ring = 32,
99 .rx_copybreak = 240,
100 .use_napi = 0,
101 .napi_weight = 17,
102 .bus_id = "0:03",
103 },
117}; 104};
118 105
119static void init_fcc1_ioports(void) 106static void init_fcc1_ioports(void)
@@ -209,20 +196,21 @@ static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev,
209 bd_t* bi = (void*)__res; 196 bd_t* bi = (void*)__res;
210 int fs_no = fsid_fcc1+pdev->id-1; 197 int fs_no = fsid_fcc1+pdev->id-1;
211 198
212 mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase; 199 if(fs_no > ARRAY_SIZE(mpc82xx_enet_pdata)) {
213 mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c; 200 return;
214
215 switch(fs_no) {
216 case fsid_fcc1:
217 memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6);
218 pdev->dev.platform_data = &mpc82xx_fcc1_pdata;
219 break;
220 case fsid_fcc2:
221 memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6);
222 mpc82xx_fcc2_pdata.macaddr[5] ^= 1;
223 pdev->dev.platform_data = &mpc82xx_fcc2_pdata;
224 break;
225 } 201 }
202
203 mpc82xx_enet_pdata[fs_no].dpram_offset=
204 (u32)cpm2_immr->im_dprambase;
205 mpc82xx_enet_pdata[fs_no].fcc_regs_c =
206 (u32)cpm2_immr->im_fcc_c;
207 memcpy(&mpc82xx_enet_pdata[fs_no].macaddr,bi->bi_enetaddr,6);
208
209 /* prevent dup mac */
210 if(fs_no == fsid_fcc2)
211 mpc82xx_enet_pdata[fs_no].macaddr[5] ^= 1;
212
213 pdev->dev.platform_data = &mpc82xx_enet_pdata[fs_no];
226} 214}
227 215
228static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev, 216static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev,
@@ -274,6 +262,29 @@ static void init_scc4_uart_ioports(void)
274 iounmap(immap); 262 iounmap(immap);
275} 263}
276 264
265static void __init mpc8272ads_fixup_mdio_pdata(struct platform_device *pdev,
266 int idx)
267{
268 m82xx_mii_bb_pdata.irq[0] = PHY_INTERRUPT;
269 m82xx_mii_bb_pdata.irq[1] = -1;
270 m82xx_mii_bb_pdata.irq[2] = -1;
271 m82xx_mii_bb_pdata.irq[3] = PHY_INTERRUPT;
272 m82xx_mii_bb_pdata.irq[31] = -1;
273
274
275 m82xx_mii_bb_pdata.mdio_dat.offset =
276 (u32)&cpm2_immr->im_ioport.iop_pdatc;
277
278 m82xx_mii_bb_pdata.mdio_dir.offset =
279 (u32)&cpm2_immr->im_ioport.iop_pdirc;
280
281 m82xx_mii_bb_pdata.mdc_dat.offset =
282 (u32)&cpm2_immr->im_ioport.iop_pdatc;
283
284
285 pdev->dev.platform_data = &m82xx_mii_bb_pdata;
286}
287
277static int mpc8272ads_platform_notify(struct device *dev) 288static int mpc8272ads_platform_notify(struct device *dev)
278{ 289{
279 static const struct platform_notify_dev_map dev_map[] = { 290 static const struct platform_notify_dev_map dev_map[] = {
@@ -286,6 +297,10 @@ static int mpc8272ads_platform_notify(struct device *dev)
286 .rtn = mpc8272ads_fixup_uart_pdata, 297 .rtn = mpc8272ads_fixup_uart_pdata,
287 }, 298 },
288 { 299 {
300 .bus_id = "fsl-bb-mdio",
301 .rtn = mpc8272ads_fixup_mdio_pdata,
302 },
303 {
289 .bus_id = NULL 304 .bus_id = NULL
290 } 305 }
291 }; 306 };
@@ -319,6 +334,7 @@ int __init mpc8272ads_init(void)
319 ppc_sys_device_enable(MPC82xx_CPM_SCC4); 334 ppc_sys_device_enable(MPC82xx_CPM_SCC4);
320#endif 335#endif
321 336
337 ppc_sys_device_enable(MPC82xx_MDIO_BB);
322 338
323 return 0; 339 return 0;
324} 340}
diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c
index f19b6167c770..e12cece4c9fd 100644
--- a/arch/ppc/platforms/mpc866ads_setup.c
+++ b/arch/ppc/platforms/mpc866ads_setup.c
@@ -1,10 +1,10 @@
1/*arch/ppc/platforms/mpc885ads-setup.c 1/*arch/ppc/platforms/mpc866ads-setup.c
2 * 2 *
3 * Platform setup for the Freescale mpc885ads board 3 * Platform setup for the Freescale mpc866ads board
4 * 4 *
5 * Vitaly Bordug <vbordug@ru.mvista.com> 5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 * 6 *
7 * Copyright 2005 MontaVista Software Inc. 7 * Copyright 2005-2006 MontaVista Software Inc.
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public License 9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any 10 * version 2. This program is licensed "as is" without any warranty of any
@@ -42,49 +42,36 @@ static void setup_scc1_ioports(void);
42static void setup_smc1_ioports(void); 42static void setup_smc1_ioports(void);
43static void setup_smc2_ioports(void); 43static void setup_smc2_ioports(void);
44 44
45static struct fs_mii_bus_info fec_mii_bus_info = { 45static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
46 .method = fsmii_fec,
47 .id = 0,
48};
49
50static struct fs_mii_bus_info scc_mii_bus_info = {
51 .method = fsmii_fixed,
52 .id = 0,
53 .i.fixed.speed = 10,
54 .i.fixed.duplex = 0,
55};
56 46
57static struct fs_platform_info mpc8xx_fec_pdata[] = { 47static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
58 {
59 .rx_ring = 128,
60 .tx_ring = 16,
61 .rx_copybreak = 240,
62 48
63 .use_napi = 1, 49static struct fs_platform_info mpc8xx_enet_pdata[] = {
64 .napi_weight = 17, 50 [fsid_fec1] = {
51 .rx_ring = 128,
52 .tx_ring = 16,
53 .rx_copybreak = 240,
65 54
66 .phy_addr = 15, 55 .use_napi = 1,
67 .phy_irq = -1, 56 .napi_weight = 17,
68 57
69 .use_rmii = 0, 58 .init_ioports = setup_fec1_ioports,
70 59
71 .bus_info = &fec_mii_bus_info, 60 .bus_id = "0:0f",
72 } 61 .has_phy = 1,
73}; 62 },
63 [fsid_scc1] = {
64 .rx_ring = 64,
65 .tx_ring = 8,
66 .rx_copybreak = 240,
67 .use_napi = 1,
68 .napi_weight = 17,
74 69
75static struct fs_platform_info mpc8xx_scc_pdata = {
76 .rx_ring = 64,
77 .tx_ring = 8,
78 .rx_copybreak = 240,
79 70
80 .use_napi = 1, 71 .init_ioports = setup_scc1_ioports,
81 .napi_weight = 17,
82
83 .phy_addr = -1,
84 .phy_irq = -1,
85
86 .bus_info = &scc_mii_bus_info,
87 72
73 .bus_id = "fixed@100:1",
74 },
88}; 75};
89 76
90static struct fs_uart_platform_info mpc866_uart_pdata[] = { 77static struct fs_uart_platform_info mpc866_uart_pdata[] = {
@@ -207,63 +194,6 @@ static void setup_scc1_ioports(void)
207 194
208} 195}
209 196
210static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
211{
212 struct fs_platform_info *fpi = pdev->dev.platform_data;
213
214 volatile cpm8xx_t *cp;
215 bd_t *bd = (bd_t *) __res;
216 char *e;
217 int i;
218
219 /* Get pointer to Communication Processor */
220 cp = cpmp;
221 switch (fs_no) {
222 case fsid_fec1:
223 fpi = &mpc8xx_fec_pdata[0];
224 fpi->init_ioports = &setup_fec1_ioports;
225
226 break;
227 case fsid_scc1:
228 fpi = &mpc8xx_scc_pdata;
229 fpi->init_ioports = &setup_scc1_ioports;
230
231 break;
232 default:
233 printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
234 return;
235 }
236
237 pdev->dev.platform_data = fpi;
238 fpi->fs_no = fs_no;
239
240 e = (unsigned char *)&bd->bi_enetaddr;
241 for (i = 0; i < 6; i++)
242 fpi->macaddr[i] = *e++;
243
244 fpi->macaddr[5 - pdev->id]++;
245
246}
247
248static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
249 int idx)
250{
251 /* This is for FEC devices only */
252 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
253 return;
254 mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
255}
256
257static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
258 int idx)
259{
260 /* This is for SCC devices only */
261 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
262 return;
263
264 mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
265}
266
267static void setup_smc1_ioports(void) 197static void setup_smc1_ioports(void)
268{ 198{
269 immap_t *immap = (immap_t *) IMAP_ADDR; 199 immap_t *immap = (immap_t *) IMAP_ADDR;
@@ -315,6 +245,56 @@ static void setup_smc2_ioports(void)
315 245
316} 246}
317 247
248static int ma_count = 0;
249
250static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
251{
252 struct fs_platform_info *fpi;
253
254 volatile cpm8xx_t *cp;
255 bd_t *bd = (bd_t *) __res;
256 char *e;
257 int i;
258
259 /* Get pointer to Communication Processor */
260 cp = cpmp;
261
262 if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) {
263 printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
264 return;
265 }
266
267
268 fpi = &mpc8xx_enet_pdata[fs_no];
269 fpi->fs_no = fs_no;
270 pdev->dev.platform_data = fpi;
271
272 e = (unsigned char *)&bd->bi_enetaddr;
273 for (i = 0; i < 6; i++)
274 fpi->macaddr[i] = *e++;
275
276 fpi->macaddr[5] += ma_count++;
277}
278
279static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
280 int idx)
281{
282 /* This is for FEC devices only */
283 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
284 return;
285 mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
286}
287
288static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
289 int idx)
290{
291 /* This is for SCC devices only */
292 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
293 return;
294
295 mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
296}
297
318static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev, 298static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev,
319 int idx) 299 int idx)
320{ 300{
@@ -359,6 +339,9 @@ static int mpc866ads_platform_notify(struct device *dev)
359 339
360int __init mpc866ads_init(void) 340int __init mpc866ads_init(void)
361{ 341{
342 bd_t *bd = (bd_t *) __res;
343 struct fs_mii_fec_platform_info* fmpi;
344
362 printk(KERN_NOTICE "mpc866ads: Init\n"); 345 printk(KERN_NOTICE "mpc866ads: Init\n");
363 346
364 platform_notify = mpc866ads_platform_notify; 347 platform_notify = mpc866ads_platform_notify;
@@ -366,11 +349,20 @@ int __init mpc866ads_init(void)
366 ppc_sys_device_initfunc(); 349 ppc_sys_device_initfunc();
367 ppc_sys_device_disable_all(); 350 ppc_sys_device_disable_all();
368 351
369#ifdef MPC8xx_SECOND_ETH_SCC1 352#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC1
370 ppc_sys_device_enable(MPC8xx_CPM_SCC1); 353 ppc_sys_device_enable(MPC8xx_CPM_SCC1);
371#endif 354#endif
372 ppc_sys_device_enable(MPC8xx_CPM_FEC1); 355 ppc_sys_device_enable(MPC8xx_CPM_FEC1);
373 356
357 ppc_sys_device_enable(MPC8xx_MDIO_FEC);
358
359 fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
360 &mpc8xx_mdio_fec_pdata;
361
362 fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
363 /* No PHY interrupt line here */
364 fmpi->irq[0xf] = -1;
365
374/* Since either of the uarts could be used as console, they need to ready */ 366/* Since either of the uarts could be used as console, they need to ready */
375#ifdef CONFIG_SERIAL_CPM_SMC1 367#ifdef CONFIG_SERIAL_CPM_SMC1
376 ppc_sys_device_enable(MPC8xx_CPM_SMC1); 368 ppc_sys_device_enable(MPC8xx_CPM_SMC1);
@@ -381,6 +373,14 @@ int __init mpc866ads_init(void)
381 ppc_sys_device_enable(MPC8xx_CPM_SMC2); 373 ppc_sys_device_enable(MPC8xx_CPM_SMC2);
382 ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART); 374 ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
383#endif 375#endif
376 ppc_sys_device_enable(MPC8xx_MDIO_FEC);
377
378 fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
379 &mpc8xx_mdio_fec_pdata;
380
381 fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
382 /* No PHY interrupt line here */
383 fmpi->irq[0xf] = -1;
384 384
385 return 0; 385 return 0;
386} 386}
diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c
index c1fc4a16fea9..5dfa4e6c2af0 100644
--- a/arch/ppc/platforms/mpc885ads_setup.c
+++ b/arch/ppc/platforms/mpc885ads_setup.c
@@ -38,7 +38,10 @@ extern unsigned char __res[];
38static void setup_smc1_ioports(void); 38static void setup_smc1_ioports(void);
39static void setup_smc2_ioports(void); 39static void setup_smc2_ioports(void);
40 40
41static void __init mpc885ads_scc_phy_init(char); 41static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
42static void setup_fec1_ioports(void);
43static void setup_fec2_ioports(void);
44static void setup_scc3_ioports(void);
42 45
43static struct fs_uart_platform_info mpc885_uart_pdata[] = { 46static struct fs_uart_platform_info mpc885_uart_pdata[] = {
44 [fsid_smc1_uart] = { 47 [fsid_smc1_uart] = {
@@ -61,23 +64,8 @@ static struct fs_uart_platform_info mpc885_uart_pdata[] = {
61 }, 64 },
62}; 65};
63 66
64static struct fs_mii_bus_info fec_mii_bus_info = { 67static struct fs_platform_info mpc8xx_enet_pdata[] = {
65 .method = fsmii_fec, 68 [fsid_fec1] = {
66 .id = 0,
67};
68
69static struct fs_mii_bus_info scc_mii_bus_info = {
70#ifdef CONFIG_SCC_ENET_8xx_FIXED
71 .method = fsmii_fixed,
72#else
73 .method = fsmii_fec,
74#endif
75
76 .id = 0,
77};
78
79static struct fs_platform_info mpc8xx_fec_pdata[] = {
80 {
81 .rx_ring = 128, 69 .rx_ring = 128,
82 .tx_ring = 16, 70 .tx_ring = 16,
83 .rx_copybreak = 240, 71 .rx_copybreak = 240,
@@ -85,11 +73,12 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = {
85 .use_napi = 1, 73 .use_napi = 1,
86 .napi_weight = 17, 74 .napi_weight = 17,
87 75
88 .phy_addr = 0, 76 .init_ioports = setup_fec1_ioports,
89 .phy_irq = SIU_IRQ7,
90 77
91 .bus_info = &fec_mii_bus_info, 78 .bus_id = "0:00",
92 }, { 79 .has_phy = 1,
80 },
81 [fsid_fec2] = {
93 .rx_ring = 128, 82 .rx_ring = 128,
94 .tx_ring = 16, 83 .tx_ring = 16,
95 .rx_copybreak = 240, 84 .rx_copybreak = 240,
@@ -97,35 +86,32 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = {
97 .use_napi = 1, 86 .use_napi = 1,
98 .napi_weight = 17, 87 .napi_weight = 17,
99 88
100 .phy_addr = 1, 89 .init_ioports = setup_fec2_ioports,
101 .phy_irq = SIU_IRQ7,
102
103 .bus_info = &fec_mii_bus_info,
104 }
105};
106 90
107static struct fs_platform_info mpc8xx_scc_pdata = { 91 .bus_id = "0:01",
108 .rx_ring = 64, 92 .has_phy = 1,
109 .tx_ring = 8, 93 },
110 .rx_copybreak = 240, 94 [fsid_scc3] = {
95 .rx_ring = 64,
96 .tx_ring = 8,
97 .rx_copybreak = 240,
111 98
112 .use_napi = 1, 99 .use_napi = 1,
113 .napi_weight = 17, 100 .napi_weight = 17,
114 101
115 .phy_addr = 2, 102 .init_ioports = setup_scc3_ioports,
116#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED 103#ifdef CONFIG_FIXED_MII_10_FDX
117 .phy_irq = -1, 104 .bus_id = "fixed@100:1",
118#else 105#else
119 .phy_irq = SIU_IRQ7, 106 .bus_id = "0:02",
120#endif 107 #endif
121 108 },
122 .bus_info = &scc_mii_bus_info,
123}; 109};
124 110
125void __init board_init(void) 111void __init board_init(void)
126{ 112{
127 volatile cpm8xx_t *cp = cpmp; 113 cpm8xx_t *cp = cpmp;
128 unsigned int *bcsr_io; 114 unsigned int *bcsr_io;
129 115
130#ifdef CONFIG_FS_ENET 116#ifdef CONFIG_FS_ENET
131 immap_t *immap = (immap_t *) IMAP_ADDR; 117 immap_t *immap = (immap_t *) IMAP_ADDR;
@@ -164,6 +150,14 @@ void __init board_init(void)
164 /* use MDC for MII (common) */ 150 /* use MDC for MII (common) */
165 setbits16(&immap->im_ioport.iop_pdpar, 0x0080); 151 setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
166 clrbits16(&immap->im_ioport.iop_pddir, 0x0080); 152 clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
153 bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
154 clrbits32(bcsr_io,BCSR5_MII1_EN);
155 clrbits32(bcsr_io,BCSR5_MII1_RST);
156#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
157 clrbits32(bcsr_io,BCSR5_MII2_EN);
158 clrbits32(bcsr_io,BCSR5_MII2_RST);
159#endif
160 iounmap(bcsr_io);
167#endif 161#endif
168} 162}
169 163
@@ -194,8 +188,8 @@ static void setup_fec2_ioports(void)
194 /* configure FEC2 pins */ 188 /* configure FEC2 pins */
195 setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc); 189 setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
196 setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc); 190 setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
197 setbits32(&immap->im_cpm.cp_peso, 0x00037800);
198 clrbits32(&immap->im_cpm.cp_peso, 0x000087fc); 191 clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
192 setbits32(&immap->im_cpm.cp_peso, 0x00037800);
199 clrbits32(&immap->im_cpm.cp_cptr, 0x00000080); 193 clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
200} 194}
201 195
@@ -213,6 +207,8 @@ static void setup_scc3_ioports(void)
213 207
214 /* Enable the PHY. 208 /* Enable the PHY.
215 */ 209 */
210 clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
211 udelay(1000);
216 setbits32(bcsr_io+4, BCSR4_ETH10_RST); 212 setbits32(bcsr_io+4, BCSR4_ETH10_RST);
217 /* Configure port A pins for Txd and Rxd. 213 /* Configure port A pins for Txd and Rxd.
218 */ 214 */
@@ -254,37 +250,38 @@ static void setup_scc3_ioports(void)
254 clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA); 250 clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
255 setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA); 251 setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
256 252
257 setbits32(bcsr_io+1, BCSR1_ETHEN); 253 setbits32(bcsr_io+4, BCSR1_ETHEN);
258 iounmap(bcsr_io); 254 iounmap(bcsr_io);
259} 255}
260 256
257static int mac_count = 0;
258
261static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) 259static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
262{ 260{
263 struct fs_platform_info *fpi = pdev->dev.platform_data; 261 struct fs_platform_info *fpi;
264
265 volatile cpm8xx_t *cp;
266 bd_t *bd = (bd_t *) __res; 262 bd_t *bd = (bd_t *) __res;
267 char *e; 263 char *e;
268 int i; 264 int i;
269 265
270 /* Get pointer to Communication Processor */ 266 if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) {
271 cp = cpmp; 267 printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
268 return;
269 }
270
271 fpi = &mpc8xx_enet_pdata[fs_no];
272
272 switch (fs_no) { 273 switch (fs_no) {
273 case fsid_fec1: 274 case fsid_fec1:
274 fpi = &mpc8xx_fec_pdata[0];
275 fpi->init_ioports = &setup_fec1_ioports; 275 fpi->init_ioports = &setup_fec1_ioports;
276 break; 276 break;
277 case fsid_fec2: 277 case fsid_fec2:
278 fpi = &mpc8xx_fec_pdata[1];
279 fpi->init_ioports = &setup_fec2_ioports; 278 fpi->init_ioports = &setup_fec2_ioports;
280 break; 279 break;
281 case fsid_scc3: 280 case fsid_scc3:
282 fpi = &mpc8xx_scc_pdata;
283 fpi->init_ioports = &setup_scc3_ioports; 281 fpi->init_ioports = &setup_scc3_ioports;
284 mpc885ads_scc_phy_init(fpi->phy_addr);
285 break; 282 break;
286 default: 283 default:
287 printk(KERN_WARNING"Device %s is not supported!\n", pdev->name); 284 printk(KERN_WARNING "Device %s is not supported!\n", pdev->name);
288 return; 285 return;
289 } 286 }
290 287
@@ -295,7 +292,7 @@ static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
295 for (i = 0; i < 6; i++) 292 for (i = 0; i < 6; i++)
296 fpi->macaddr[i] = *e++; 293 fpi->macaddr[i] = *e++;
297 294
298 fpi->macaddr[5 - pdev->id]++; 295 fpi->macaddr[5] += mac_count++;
299 296
300} 297}
301 298
@@ -318,58 +315,6 @@ static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev,
318 mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); 315 mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
319} 316}
320 317
321/* SCC ethernet controller does not have MII management channel. FEC1 MII
322 * channel is used to communicate with the 10Mbit PHY.
323 */
324
325#define MII_ECNTRL_PINMUX 0x4
326#define FEC_ECNTRL_PINMUX 0x00000004
327#define FEC_RCNTRL_MII_MODE 0x00000004
328
329/* Make MII read/write commands.
330 */
331#define mk_mii_write(REG, VAL, PHY_ADDR) (0x50020000 | (((REG) & 0x1f) << 18) | \
332 ((VAL) & 0xffff) | ((PHY_ADDR) << 23))
333
334static void mpc885ads_scc_phy_init(char phy_addr)
335{
336 volatile immap_t *immap;
337 volatile fec_t *fecp;
338 bd_t *bd;
339
340 bd = (bd_t *) __res;
341 immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */
342 fecp = &(immap->im_cpm.cp_fec);
343
344 /* Enable MII pins of the FEC1
345 */
346 setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
347 clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
348 /* Set MII speed to 2.5 MHz
349 */
350 out_be32(&fecp->fec_mii_speed,
351 ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1);
352
353 /* Enable FEC pin MUX
354 */
355 setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
356 setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
357
358 out_be32(&fecp->fec_mii_data,
359 mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr));
360 udelay(100);
361 out_be32(&fecp->fec_mii_data,
362 mk_mii_write(MII_ADVERTISE,
363 ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr));
364 udelay(100);
365
366 /* Disable FEC MII settings
367 */
368 clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
369 clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
370 out_be32(&fecp->fec_mii_speed, 0);
371}
372
373static void setup_smc1_ioports(void) 318static void setup_smc1_ioports(void)
374{ 319{
375 immap_t *immap = (immap_t *) IMAP_ADDR; 320 immap_t *immap = (immap_t *) IMAP_ADDR;
@@ -462,6 +407,9 @@ static int mpc885ads_platform_notify(struct device *dev)
462 407
463int __init mpc885ads_init(void) 408int __init mpc885ads_init(void)
464{ 409{
410 struct fs_mii_fec_platform_info* fmpi;
411 bd_t *bd = (bd_t *) __res;
412
465 printk(KERN_NOTICE "mpc885ads: Init\n"); 413 printk(KERN_NOTICE "mpc885ads: Init\n");
466 414
467 platform_notify = mpc885ads_platform_notify; 415 platform_notify = mpc885ads_platform_notify;
@@ -471,8 +419,17 @@ int __init mpc885ads_init(void)
471 419
472 ppc_sys_device_enable(MPC8xx_CPM_FEC1); 420 ppc_sys_device_enable(MPC8xx_CPM_FEC1);
473 421
422 ppc_sys_device_enable(MPC8xx_MDIO_FEC);
423 fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
424 &mpc8xx_mdio_fec_pdata;
425
426 fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
427
428 /* No PHY interrupt line here */
429 fmpi->irq[0xf] = SIU_IRQ7;
430
474#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 431#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
475 ppc_sys_device_enable(MPC8xx_CPM_SCC1); 432 ppc_sys_device_enable(MPC8xx_CPM_SCC3);
476 433
477#endif 434#endif
478#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 435#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
diff --git a/arch/ppc/platforms/pq2ads_pd.h b/arch/ppc/platforms/pq2ads_pd.h
index 8f14a43eafec..672483df8079 100644
--- a/arch/ppc/platforms/pq2ads_pd.h
+++ b/arch/ppc/platforms/pq2ads_pd.h
@@ -29,86 +29,4 @@
29#define F3_RXCLK 13 29#define F3_RXCLK 13
30#define F3_TXCLK 14 30#define F3_TXCLK 14
31 31
32/* Automatically generates register configurations */
33#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
34
35#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
36#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
37#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
38#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
39#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
40#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
41
42#define PC_F1RXCLK PC_CLK(F1_RXCLK)
43#define PC_F1TXCLK PC_CLK(F1_TXCLK)
44#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
45#define CMX1_CLK_MASK ((uint)0xff000000)
46
47#define PC_F2RXCLK PC_CLK(F2_RXCLK)
48#define PC_F2TXCLK PC_CLK(F2_TXCLK)
49#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
50#define CMX2_CLK_MASK ((uint)0x00ff0000)
51
52#define PC_F3RXCLK PC_CLK(F3_RXCLK)
53#define PC_F3TXCLK PC_CLK(F3_TXCLK)
54#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
55#define CMX3_CLK_MASK ((uint)0x0000ff00)
56
57/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
58 * but there is little variation among the choices.
59 */
60#define PA1_COL 0x00000001U
61#define PA1_CRS 0x00000002U
62#define PA1_TXER 0x00000004U
63#define PA1_TXEN 0x00000008U
64#define PA1_RXDV 0x00000010U
65#define PA1_RXER 0x00000020U
66#define PA1_TXDAT 0x00003c00U
67#define PA1_RXDAT 0x0003c000U
68#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
69#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
70 PA1_RXDV | PA1_RXER)
71#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
72#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
73
74
75/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
76 * but there is little variation among the choices.
77 */
78#define PB2_TXER 0x00000001U
79#define PB2_RXDV 0x00000002U
80#define PB2_TXEN 0x00000004U
81#define PB2_RXER 0x00000008U
82#define PB2_COL 0x00000010U
83#define PB2_CRS 0x00000020U
84#define PB2_TXDAT 0x000003c0U
85#define PB2_RXDAT 0x00003c00U
86#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
87 PB2_RXER | PB2_RXDV | PB2_TXER)
88#define PB2_PSORB1 (PB2_TXEN)
89#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
90#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
91
92
93/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
94 * but there is little variation among the choices.
95 */
96#define PB3_RXDV 0x00004000U
97#define PB3_RXER 0x00008000U
98#define PB3_TXER 0x00010000U
99#define PB3_TXEN 0x00020000U
100#define PB3_COL 0x00040000U
101#define PB3_CRS 0x00080000U
102#define PB3_TXDAT 0x0f000000U
103#define PB3_RXDAT 0x00f00000U
104#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
105 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
106#define PB3_PSORB1 0
107#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
108#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
109
110#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
111#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
112#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
113
114#endif 32#endif
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 2497bbc07e76..dca23f2ef851 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -93,7 +93,7 @@ obj-$(CONFIG_PCI) += pci_auto.o
93endif 93endif
94obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o 94obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o
95obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \ 95obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \
96 mpc83xx_sys.o mpc83xx_devices.o 96 mpc83xx_sys.o mpc83xx_devices.o ipic.o
97ifeq ($(CONFIG_83xx),y) 97ifeq ($(CONFIG_83xx),y)
98obj-$(CONFIG_PCI) += pci_auto.o 98obj-$(CONFIG_PCI) += pci_auto.o
99endif 99endif
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c
new file mode 100644
index 000000000000..46801f5ec03f
--- /dev/null
+++ b/arch/ppc/syslib/ipic.c
@@ -0,0 +1,646 @@
1/*
2 * include/asm-ppc/ipic.c
3 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
21#include <linux/sysdev.h>
22#include <asm/irq.h>
23#include <asm/io.h>
24#include <asm/ipic.h>
25#include <asm/mpc83xx.h>
26
27#include "ipic.h"
28
29static struct ipic p_ipic;
30static struct ipic * primary_ipic;
31
32static struct ipic_info ipic_info[] = {
33 [9] = {
34 .pend = IPIC_SIPNR_H,
35 .mask = IPIC_SIMSR_H,
36 .prio = IPIC_SIPRR_D,
37 .force = IPIC_SIFCR_H,
38 .bit = 24,
39 .prio_mask = 0,
40 },
41 [10] = {
42 .pend = IPIC_SIPNR_H,
43 .mask = IPIC_SIMSR_H,
44 .prio = IPIC_SIPRR_D,
45 .force = IPIC_SIFCR_H,
46 .bit = 25,
47 .prio_mask = 1,
48 },
49 [11] = {
50 .pend = IPIC_SIPNR_H,
51 .mask = IPIC_SIMSR_H,
52 .prio = IPIC_SIPRR_D,
53 .force = IPIC_SIFCR_H,
54 .bit = 26,
55 .prio_mask = 2,
56 },
57 [14] = {
58 .pend = IPIC_SIPNR_H,
59 .mask = IPIC_SIMSR_H,
60 .prio = IPIC_SIPRR_D,
61 .force = IPIC_SIFCR_H,
62 .bit = 29,
63 .prio_mask = 5,
64 },
65 [15] = {
66 .pend = IPIC_SIPNR_H,
67 .mask = IPIC_SIMSR_H,
68 .prio = IPIC_SIPRR_D,
69 .force = IPIC_SIFCR_H,
70 .bit = 30,
71 .prio_mask = 6,
72 },
73 [16] = {
74 .pend = IPIC_SIPNR_H,
75 .mask = IPIC_SIMSR_H,
76 .prio = IPIC_SIPRR_D,
77 .force = IPIC_SIFCR_H,
78 .bit = 31,
79 .prio_mask = 7,
80 },
81 [17] = {
82 .pend = IPIC_SEPNR,
83 .mask = IPIC_SEMSR,
84 .prio = IPIC_SMPRR_A,
85 .force = IPIC_SEFCR,
86 .bit = 1,
87 .prio_mask = 5,
88 },
89 [18] = {
90 .pend = IPIC_SEPNR,
91 .mask = IPIC_SEMSR,
92 .prio = IPIC_SMPRR_A,
93 .force = IPIC_SEFCR,
94 .bit = 2,
95 .prio_mask = 6,
96 },
97 [19] = {
98 .pend = IPIC_SEPNR,
99 .mask = IPIC_SEMSR,
100 .prio = IPIC_SMPRR_A,
101 .force = IPIC_SEFCR,
102 .bit = 3,
103 .prio_mask = 7,
104 },
105 [20] = {
106 .pend = IPIC_SEPNR,
107 .mask = IPIC_SEMSR,
108 .prio = IPIC_SMPRR_B,
109 .force = IPIC_SEFCR,
110 .bit = 4,
111 .prio_mask = 4,
112 },
113 [21] = {
114 .pend = IPIC_SEPNR,
115 .mask = IPIC_SEMSR,
116 .prio = IPIC_SMPRR_B,
117 .force = IPIC_SEFCR,
118 .bit = 5,
119 .prio_mask = 5,
120 },
121 [22] = {
122 .pend = IPIC_SEPNR,
123 .mask = IPIC_SEMSR,
124 .prio = IPIC_SMPRR_B,
125 .force = IPIC_SEFCR,
126 .bit = 6,
127 .prio_mask = 6,
128 },
129 [23] = {
130 .pend = IPIC_SEPNR,
131 .mask = IPIC_SEMSR,
132 .prio = IPIC_SMPRR_B,
133 .force = IPIC_SEFCR,
134 .bit = 7,
135 .prio_mask = 7,
136 },
137 [32] = {
138 .pend = IPIC_SIPNR_H,
139 .mask = IPIC_SIMSR_H,
140 .prio = IPIC_SIPRR_A,
141 .force = IPIC_SIFCR_H,
142 .bit = 0,
143 .prio_mask = 0,
144 },
145 [33] = {
146 .pend = IPIC_SIPNR_H,
147 .mask = IPIC_SIMSR_H,
148 .prio = IPIC_SIPRR_A,
149 .force = IPIC_SIFCR_H,
150 .bit = 1,
151 .prio_mask = 1,
152 },
153 [34] = {
154 .pend = IPIC_SIPNR_H,
155 .mask = IPIC_SIMSR_H,
156 .prio = IPIC_SIPRR_A,
157 .force = IPIC_SIFCR_H,
158 .bit = 2,
159 .prio_mask = 2,
160 },
161 [35] = {
162 .pend = IPIC_SIPNR_H,
163 .mask = IPIC_SIMSR_H,
164 .prio = IPIC_SIPRR_A,
165 .force = IPIC_SIFCR_H,
166 .bit = 3,
167 .prio_mask = 3,
168 },
169 [36] = {
170 .pend = IPIC_SIPNR_H,
171 .mask = IPIC_SIMSR_H,
172 .prio = IPIC_SIPRR_A,
173 .force = IPIC_SIFCR_H,
174 .bit = 4,
175 .prio_mask = 4,
176 },
177 [37] = {
178 .pend = IPIC_SIPNR_H,
179 .mask = IPIC_SIMSR_H,
180 .prio = IPIC_SIPRR_A,
181 .force = IPIC_SIFCR_H,
182 .bit = 5,
183 .prio_mask = 5,
184 },
185 [38] = {
186 .pend = IPIC_SIPNR_H,
187 .mask = IPIC_SIMSR_H,
188 .prio = IPIC_SIPRR_A,
189 .force = IPIC_SIFCR_H,
190 .bit = 6,
191 .prio_mask = 6,
192 },
193 [39] = {
194 .pend = IPIC_SIPNR_H,
195 .mask = IPIC_SIMSR_H,
196 .prio = IPIC_SIPRR_A,
197 .force = IPIC_SIFCR_H,
198 .bit = 7,
199 .prio_mask = 7,
200 },
201 [48] = {
202 .pend = IPIC_SEPNR,
203 .mask = IPIC_SEMSR,
204 .prio = IPIC_SMPRR_A,
205 .force = IPIC_SEFCR,
206 .bit = 0,
207 .prio_mask = 4,
208 },
209 [64] = {
210 .pend = IPIC_SIPNR_H,
211 .mask = IPIC_SIMSR_L,
212 .prio = IPIC_SMPRR_A,
213 .force = IPIC_SIFCR_L,
214 .bit = 0,
215 .prio_mask = 0,
216 },
217 [65] = {
218 .pend = IPIC_SIPNR_H,
219 .mask = IPIC_SIMSR_L,
220 .prio = IPIC_SMPRR_A,
221 .force = IPIC_SIFCR_L,
222 .bit = 1,
223 .prio_mask = 1,
224 },
225 [66] = {
226 .pend = IPIC_SIPNR_H,
227 .mask = IPIC_SIMSR_L,
228 .prio = IPIC_SMPRR_A,
229 .force = IPIC_SIFCR_L,
230 .bit = 2,
231 .prio_mask = 2,
232 },
233 [67] = {
234 .pend = IPIC_SIPNR_H,
235 .mask = IPIC_SIMSR_L,
236 .prio = IPIC_SMPRR_A,
237 .force = IPIC_SIFCR_L,
238 .bit = 3,
239 .prio_mask = 3,
240 },
241 [68] = {
242 .pend = IPIC_SIPNR_H,
243 .mask = IPIC_SIMSR_L,
244 .prio = IPIC_SMPRR_B,
245 .force = IPIC_SIFCR_L,
246 .bit = 4,
247 .prio_mask = 0,
248 },
249 [69] = {
250 .pend = IPIC_SIPNR_H,
251 .mask = IPIC_SIMSR_L,
252 .prio = IPIC_SMPRR_B,
253 .force = IPIC_SIFCR_L,
254 .bit = 5,
255 .prio_mask = 1,
256 },
257 [70] = {
258 .pend = IPIC_SIPNR_H,
259 .mask = IPIC_SIMSR_L,
260 .prio = IPIC_SMPRR_B,
261 .force = IPIC_SIFCR_L,
262 .bit = 6,
263 .prio_mask = 2,
264 },
265 [71] = {
266 .pend = IPIC_SIPNR_H,
267 .mask = IPIC_SIMSR_L,
268 .prio = IPIC_SMPRR_B,
269 .force = IPIC_SIFCR_L,
270 .bit = 7,
271 .prio_mask = 3,
272 },
273 [72] = {
274 .pend = IPIC_SIPNR_H,
275 .mask = IPIC_SIMSR_L,
276 .prio = 0,
277 .force = IPIC_SIFCR_L,
278 .bit = 8,
279 },
280 [73] = {
281 .pend = IPIC_SIPNR_H,
282 .mask = IPIC_SIMSR_L,
283 .prio = 0,
284 .force = IPIC_SIFCR_L,
285 .bit = 9,
286 },
287 [74] = {
288 .pend = IPIC_SIPNR_H,
289 .mask = IPIC_SIMSR_L,
290 .prio = 0,
291 .force = IPIC_SIFCR_L,
292 .bit = 10,
293 },
294 [75] = {
295 .pend = IPIC_SIPNR_H,
296 .mask = IPIC_SIMSR_L,
297 .prio = 0,
298 .force = IPIC_SIFCR_L,
299 .bit = 11,
300 },
301 [76] = {
302 .pend = IPIC_SIPNR_H,
303 .mask = IPIC_SIMSR_L,
304 .prio = 0,
305 .force = IPIC_SIFCR_L,
306 .bit = 12,
307 },
308 [77] = {
309 .pend = IPIC_SIPNR_H,
310 .mask = IPIC_SIMSR_L,
311 .prio = 0,
312 .force = IPIC_SIFCR_L,
313 .bit = 13,
314 },
315 [78] = {
316 .pend = IPIC_SIPNR_H,
317 .mask = IPIC_SIMSR_L,
318 .prio = 0,
319 .force = IPIC_SIFCR_L,
320 .bit = 14,
321 },
322 [79] = {
323 .pend = IPIC_SIPNR_H,
324 .mask = IPIC_SIMSR_L,
325 .prio = 0,
326 .force = IPIC_SIFCR_L,
327 .bit = 15,
328 },
329 [80] = {
330 .pend = IPIC_SIPNR_H,
331 .mask = IPIC_SIMSR_L,
332 .prio = 0,
333 .force = IPIC_SIFCR_L,
334 .bit = 16,
335 },
336 [84] = {
337 .pend = IPIC_SIPNR_H,
338 .mask = IPIC_SIMSR_L,
339 .prio = 0,
340 .force = IPIC_SIFCR_L,
341 .bit = 20,
342 },
343 [85] = {
344 .pend = IPIC_SIPNR_H,
345 .mask = IPIC_SIMSR_L,
346 .prio = 0,
347 .force = IPIC_SIFCR_L,
348 .bit = 21,
349 },
350 [90] = {
351 .pend = IPIC_SIPNR_H,
352 .mask = IPIC_SIMSR_L,
353 .prio = 0,
354 .force = IPIC_SIFCR_L,
355 .bit = 26,
356 },
357 [91] = {
358 .pend = IPIC_SIPNR_H,
359 .mask = IPIC_SIMSR_L,
360 .prio = 0,
361 .force = IPIC_SIFCR_L,
362 .bit = 27,
363 },
364};
365
366static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
367{
368 return in_be32(base + (reg >> 2));
369}
370
371static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
372{
373 out_be32(base + (reg >> 2), value);
374}
375
376static inline struct ipic * ipic_from_irq(unsigned int irq)
377{
378 return primary_ipic;
379}
380
381static void ipic_enable_irq(unsigned int irq)
382{
383 struct ipic *ipic = ipic_from_irq(irq);
384 unsigned int src = irq - ipic->irq_offset;
385 u32 temp;
386
387 temp = ipic_read(ipic->regs, ipic_info[src].mask);
388 temp |= (1 << (31 - ipic_info[src].bit));
389 ipic_write(ipic->regs, ipic_info[src].mask, temp);
390}
391
392static void ipic_disable_irq(unsigned int irq)
393{
394 struct ipic *ipic = ipic_from_irq(irq);
395 unsigned int src = irq - ipic->irq_offset;
396 u32 temp;
397
398 temp = ipic_read(ipic->regs, ipic_info[src].mask);
399 temp &= ~(1 << (31 - ipic_info[src].bit));
400 ipic_write(ipic->regs, ipic_info[src].mask, temp);
401}
402
403static void ipic_disable_irq_and_ack(unsigned int irq)
404{
405 struct ipic *ipic = ipic_from_irq(irq);
406 unsigned int src = irq - ipic->irq_offset;
407 u32 temp;
408
409 ipic_disable_irq(irq);
410
411 temp = ipic_read(ipic->regs, ipic_info[src].pend);
412 temp |= (1 << (31 - ipic_info[src].bit));
413 ipic_write(ipic->regs, ipic_info[src].pend, temp);
414}
415
416static void ipic_end_irq(unsigned int irq)
417{
418 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
419 ipic_enable_irq(irq);
420}
421
422struct hw_interrupt_type ipic = {
423 .typename = " IPIC ",
424 .enable = ipic_enable_irq,
425 .disable = ipic_disable_irq,
426 .ack = ipic_disable_irq_and_ack,
427 .end = ipic_end_irq,
428};
429
430void __init ipic_init(phys_addr_t phys_addr,
431 unsigned int flags,
432 unsigned int irq_offset,
433 unsigned char *senses,
434 unsigned int senses_count)
435{
436 u32 i, temp = 0;
437
438 primary_ipic = &p_ipic;
439 primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
440
441 primary_ipic->irq_offset = irq_offset;
442
443 ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0);
444
445 /* default priority scheme is grouped. If spread mode is required
446 * configure SICFR accordingly */
447 if (flags & IPIC_SPREADMODE_GRP_A)
448 temp |= SICFR_IPSA;
449 if (flags & IPIC_SPREADMODE_GRP_D)
450 temp |= SICFR_IPSD;
451 if (flags & IPIC_SPREADMODE_MIX_A)
452 temp |= SICFR_MPSA;
453 if (flags & IPIC_SPREADMODE_MIX_B)
454 temp |= SICFR_MPSB;
455
456 ipic_write(primary_ipic->regs, IPIC_SICNR, temp);
457
458 /* handle MCP route */
459 temp = 0;
460 if (flags & IPIC_DISABLE_MCP_OUT)
461 temp = SERCR_MCPR;
462 ipic_write(primary_ipic->regs, IPIC_SERCR, temp);
463
464 /* handle routing of IRQ0 to MCP */
465 temp = ipic_read(primary_ipic->regs, IPIC_SEMSR);
466
467 if (flags & IPIC_IRQ0_MCP)
468 temp |= SEMSR_SIRQ0;
469 else
470 temp &= ~SEMSR_SIRQ0;
471
472 ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
473
474 for (i = 0 ; i < NR_IPIC_INTS ; i++) {
475 irq_desc[i+irq_offset].chip = &ipic;
476 irq_desc[i+irq_offset].status = IRQ_LEVEL;
477 }
478
479 temp = 0;
480 for (i = 0 ; i < senses_count ; i++) {
481 if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
482 temp |= 1 << (15 - i);
483 if (i != 0)
484 irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
485 else
486 irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
487 }
488 }
489 ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
490
491 printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
492 senses_count, primary_ipic->regs);
493}
494
495int ipic_set_priority(unsigned int irq, unsigned int priority)
496{
497 struct ipic *ipic = ipic_from_irq(irq);
498 unsigned int src = irq - ipic->irq_offset;
499 u32 temp;
500
501 if (priority > 7)
502 return -EINVAL;
503 if (src > 127)
504 return -EINVAL;
505 if (ipic_info[src].prio == 0)
506 return -EINVAL;
507
508 temp = ipic_read(ipic->regs, ipic_info[src].prio);
509
510 if (priority < 4) {
511 temp &= ~(0x7 << (20 + (3 - priority) * 3));
512 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
513 } else {
514 temp &= ~(0x7 << (4 + (7 - priority) * 3));
515 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
516 }
517
518 ipic_write(ipic->regs, ipic_info[src].prio, temp);
519
520 return 0;
521}
522
523void ipic_set_highest_priority(unsigned int irq)
524{
525 struct ipic *ipic = ipic_from_irq(irq);
526 unsigned int src = irq - ipic->irq_offset;
527 u32 temp;
528
529 temp = ipic_read(ipic->regs, IPIC_SICFR);
530
531 /* clear and set HPI */
532 temp &= 0x7f000000;
533 temp |= (src & 0x7f) << 24;
534
535 ipic_write(ipic->regs, IPIC_SICFR, temp);
536}
537
538void ipic_set_default_priority(void)
539{
540 ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
541 ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
542 ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
543 ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
544 ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
545 ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
546 ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
547 ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
548
549 ipic_set_priority(MPC83xx_IRQ_UART1, 0);
550 ipic_set_priority(MPC83xx_IRQ_UART2, 1);
551 ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
552 ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
553 ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
554 ipic_set_priority(MPC83xx_IRQ_SPI, 7);
555 ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
556 ipic_set_priority(MPC83xx_IRQ_PIT, 1);
557 ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
558 ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
559 ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
560 ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
561 ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
562 ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
563 ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
564 ipic_set_priority(MPC83xx_IRQ_MU, 1);
565 ipic_set_priority(MPC83xx_IRQ_SBA, 2);
566 ipic_set_priority(MPC83xx_IRQ_DMA, 3);
567 ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
568 ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
569 ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
570 ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
571}
572
573void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
574{
575 struct ipic *ipic = primary_ipic;
576 u32 temp;
577
578 temp = ipic_read(ipic->regs, IPIC_SERMR);
579 temp |= (1 << (31 - mcp_irq));
580 ipic_write(ipic->regs, IPIC_SERMR, temp);
581}
582
583void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
584{
585 struct ipic *ipic = primary_ipic;
586 u32 temp;
587
588 temp = ipic_read(ipic->regs, IPIC_SERMR);
589 temp &= (1 << (31 - mcp_irq));
590 ipic_write(ipic->regs, IPIC_SERMR, temp);
591}
592
593u32 ipic_get_mcp_status(void)
594{
595 return ipic_read(primary_ipic->regs, IPIC_SERMR);
596}
597
598void ipic_clear_mcp_status(u32 mask)
599{
600 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
601}
602
603/* Return an interrupt vector or -1 if no interrupt is pending. */
604int ipic_get_irq(struct pt_regs *regs)
605{
606 int irq;
607
608 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f;
609
610 if (irq == 0) /* 0 --> no irq is pending */
611 irq = -1;
612
613 return irq;
614}
615
616static struct sysdev_class ipic_sysclass = {
617 set_kset_name("ipic"),
618};
619
620static struct sys_device device_ipic = {
621 .id = 0,
622 .cls = &ipic_sysclass,
623};
624
625static int __init init_ipic_sysfs(void)
626{
627 int rc;
628
629 if (!primary_ipic->regs)
630 return -ENODEV;
631 printk(KERN_DEBUG "Registering ipic with sysfs...\n");
632
633 rc = sysdev_class_register(&ipic_sysclass);
634 if (rc) {
635 printk(KERN_ERR "Failed registering ipic sys class\n");
636 return -ENODEV;
637 }
638 rc = sysdev_register(&device_ipic);
639 if (rc) {
640 printk(KERN_ERR "Failed registering ipic sys device\n");
641 return -ENODEV;
642 }
643 return 0;
644}
645
646subsys_initcall(init_ipic_sysfs);
diff --git a/arch/ppc/syslib/ipic.h b/arch/ppc/syslib/ipic.h
new file mode 100644
index 000000000000..a60c9d18bb7f
--- /dev/null
+++ b/arch/ppc/syslib/ipic.h
@@ -0,0 +1,47 @@
1/*
2 * IPIC private definitions and structure.
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#ifndef __IPIC_H__
14#define __IPIC_H__
15
16#include <asm/ipic.h>
17
18#define MPC83xx_IPIC_SIZE (0x00100)
19
20/* System Global Interrupt Configuration Register */
21#define SICFR_IPSA 0x00010000
22#define SICFR_IPSD 0x00080000
23#define SICFR_MPSA 0x00200000
24#define SICFR_MPSB 0x00400000
25
26/* System External Interrupt Mask Register */
27#define SEMSR_SIRQ0 0x00008000
28
29/* System Error Control Register */
30#define SERCR_MCPR 0x00000001
31
32struct ipic {
33 volatile u32 __iomem *regs;
34 unsigned int irq_offset;
35};
36
37struct ipic_info {
38 u8 pend; /* pending register offset from base */
39 u8 mask; /* mask register offset from base */
40 u8 prio; /* priority register offset from base */
41 u8 force; /* force register offset from base */
42 u8 bit; /* register bit position (as per doc)
43 bit mask = 1 << (31 - bit) */
44 u8 prio_mask; /* priority mask value */
45};
46
47#endif /* __IPIC_H__ */
diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c
index 7735336f5b8f..325136e5aee0 100644
--- a/arch/ppc/syslib/mpc85xx_devices.c
+++ b/arch/ppc/syslib/mpc85xx_devices.c
@@ -16,9 +16,11 @@
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
18#include <linux/fsl_devices.h> 18#include <linux/fsl_devices.h>
19#include <linux/fs_enet_pd.h>
19#include <asm/mpc85xx.h> 20#include <asm/mpc85xx.h>
20#include <asm/irq.h> 21#include <asm/irq.h>
21#include <asm/ppc_sys.h> 22#include <asm/ppc_sys.h>
23#include <asm/cpm2.h>
22 24
23/* We use offsets for IORESOURCE_MEM since we do not know at compile time 25/* We use offsets for IORESOURCE_MEM since we do not know at compile time
24 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup 26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
@@ -82,6 +84,60 @@ static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
82 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, 84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
83}; 85};
84 86
87static struct fs_platform_info mpc85xx_fcc1_pdata = {
88 .fs_no = fsid_fcc1,
89 .cp_page = CPM_CR_FCC1_PAGE,
90 .cp_block = CPM_CR_FCC1_SBLOCK,
91
92 .rx_ring = 32,
93 .tx_ring = 32,
94 .rx_copybreak = 240,
95 .use_napi = 0,
96 .napi_weight = 17,
97
98 .clk_mask = CMX1_CLK_MASK,
99 .clk_route = CMX1_CLK_ROUTE,
100 .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
101
102 .mem_offset = FCC1_MEM_OFFSET,
103};
104
105static struct fs_platform_info mpc85xx_fcc2_pdata = {
106 .fs_no = fsid_fcc2,
107 .cp_page = CPM_CR_FCC2_PAGE,
108 .cp_block = CPM_CR_FCC2_SBLOCK,
109
110 .rx_ring = 32,
111 .tx_ring = 32,
112 .rx_copybreak = 240,
113 .use_napi = 0,
114 .napi_weight = 17,
115
116 .clk_mask = CMX2_CLK_MASK,
117 .clk_route = CMX2_CLK_ROUTE,
118 .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
119
120 .mem_offset = FCC2_MEM_OFFSET,
121};
122
123static struct fs_platform_info mpc85xx_fcc3_pdata = {
124 .fs_no = fsid_fcc3,
125 .cp_page = CPM_CR_FCC3_PAGE,
126 .cp_block = CPM_CR_FCC3_SBLOCK,
127
128 .rx_ring = 32,
129 .tx_ring = 32,
130 .rx_copybreak = 240,
131 .use_napi = 0,
132 .napi_weight = 17,
133
134 .clk_mask = CMX3_CLK_MASK,
135 .clk_route = CMX3_CLK_ROUTE,
136 .clk_trx = (PC_F3RXCLK | PC_F3TXCLK),
137
138 .mem_offset = FCC3_MEM_OFFSET,
139};
140
85static struct plat_serial8250_port serial_platform_data[] = { 141static struct plat_serial8250_port serial_platform_data[] = {
86 [0] = { 142 [0] = {
87 .mapbase = 0x4500, 143 .mapbase = 0x4500,
@@ -318,19 +374,28 @@ struct platform_device ppc_sys_platform_devices[] = {
318 [MPC85xx_CPM_FCC1] = { 374 [MPC85xx_CPM_FCC1] = {
319 .name = "fsl-cpm-fcc", 375 .name = "fsl-cpm-fcc",
320 .id = 1, 376 .id = 1,
321 .num_resources = 3, 377 .num_resources = 4,
378 .dev.platform_data = &mpc85xx_fcc1_pdata,
322 .resource = (struct resource[]) { 379 .resource = (struct resource[]) {
323 { 380 {
381 .name = "fcc_regs",
324 .start = 0x91300, 382 .start = 0x91300,
325 .end = 0x9131F, 383 .end = 0x9131F,
326 .flags = IORESOURCE_MEM, 384 .flags = IORESOURCE_MEM,
327 }, 385 },
328 { 386 {
387 .name = "fcc_regs_c",
329 .start = 0x91380, 388 .start = 0x91380,
330 .end = 0x9139F, 389 .end = 0x9139F,
331 .flags = IORESOURCE_MEM, 390 .flags = IORESOURCE_MEM,
332 }, 391 },
333 { 392 {
393 .name = "fcc_pram",
394 .start = 0x88400,
395 .end = 0x884ff,
396 .flags = IORESOURCE_MEM,
397 },
398 {
334 .start = SIU_INT_FCC1, 399 .start = SIU_INT_FCC1,
335 .end = SIU_INT_FCC1, 400 .end = SIU_INT_FCC1,
336 .flags = IORESOURCE_IRQ, 401 .flags = IORESOURCE_IRQ,
@@ -340,19 +405,28 @@ struct platform_device ppc_sys_platform_devices[] = {
340 [MPC85xx_CPM_FCC2] = { 405 [MPC85xx_CPM_FCC2] = {
341 .name = "fsl-cpm-fcc", 406 .name = "fsl-cpm-fcc",
342 .id = 2, 407 .id = 2,
343 .num_resources = 3, 408 .num_resources = 4,
409 .dev.platform_data = &mpc85xx_fcc2_pdata,
344 .resource = (struct resource[]) { 410 .resource = (struct resource[]) {
345 { 411 {
412 .name = "fcc_regs",
346 .start = 0x91320, 413 .start = 0x91320,
347 .end = 0x9133F, 414 .end = 0x9133F,
348 .flags = IORESOURCE_MEM, 415 .flags = IORESOURCE_MEM,
349 }, 416 },
350 { 417 {
418 .name = "fcc_regs_c",
351 .start = 0x913A0, 419 .start = 0x913A0,
352 .end = 0x913CF, 420 .end = 0x913CF,
353 .flags = IORESOURCE_MEM, 421 .flags = IORESOURCE_MEM,
354 }, 422 },
355 { 423 {
424 .name = "fcc_pram",
425 .start = 0x88500,
426 .end = 0x885ff,
427 .flags = IORESOURCE_MEM,
428 },
429 {
356 .start = SIU_INT_FCC2, 430 .start = SIU_INT_FCC2,
357 .end = SIU_INT_FCC2, 431 .end = SIU_INT_FCC2,
358 .flags = IORESOURCE_IRQ, 432 .flags = IORESOURCE_IRQ,
@@ -362,19 +436,28 @@ struct platform_device ppc_sys_platform_devices[] = {
362 [MPC85xx_CPM_FCC3] = { 436 [MPC85xx_CPM_FCC3] = {
363 .name = "fsl-cpm-fcc", 437 .name = "fsl-cpm-fcc",
364 .id = 3, 438 .id = 3,
365 .num_resources = 3, 439 .num_resources = 4,
440 .dev.platform_data = &mpc85xx_fcc3_pdata,
366 .resource = (struct resource[]) { 441 .resource = (struct resource[]) {
367 { 442 {
443 .name = "fcc_regs",
368 .start = 0x91340, 444 .start = 0x91340,
369 .end = 0x9135F, 445 .end = 0x9135F,
370 .flags = IORESOURCE_MEM, 446 .flags = IORESOURCE_MEM,
371 }, 447 },
372 { 448 {
449 .name = "fcc_regs_c",
373 .start = 0x913D0, 450 .start = 0x913D0,
374 .end = 0x913FF, 451 .end = 0x913FF,
375 .flags = IORESOURCE_MEM, 452 .flags = IORESOURCE_MEM,
376 }, 453 },
377 { 454 {
455 .name = "fcc_pram",
456 .start = 0x88600,
457 .end = 0x886ff,
458 .flags = IORESOURCE_MEM,
459 },
460 {
378 .start = SIU_INT_FCC3, 461 .start = SIU_INT_FCC3,
379 .end = SIU_INT_FCC3, 462 .end = SIU_INT_FCC3,
380 .flags = IORESOURCE_IRQ, 463 .flags = IORESOURCE_IRQ,
diff --git a/arch/ppc/syslib/mpc8xx_devices.c b/arch/ppc/syslib/mpc8xx_devices.c
index 6f536383866e..cf5ab47487a7 100644
--- a/arch/ppc/syslib/mpc8xx_devices.c
+++ b/arch/ppc/syslib/mpc8xx_devices.c
@@ -218,6 +218,14 @@ struct platform_device ppc_sys_platform_devices[] = {
218 }, 218 },
219 }, 219 },
220 }, 220 },
221
222 [MPC8xx_MDIO_FEC] = {
223 .name = "fsl-cpm-fec-mdio",
224 .id = 0,
225 .num_resources = 0,
226
227 },
228
221}; 229};
222 230
223static int __init mach_mpc8xx_fixup(struct platform_device *pdev) 231static int __init mach_mpc8xx_fixup(struct platform_device *pdev)
diff --git a/arch/ppc/syslib/mpc8xx_sys.c b/arch/ppc/syslib/mpc8xx_sys.c
index eee213284855..18ba1d7ff9f1 100644
--- a/arch/ppc/syslib/mpc8xx_sys.c
+++ b/arch/ppc/syslib/mpc8xx_sys.c
@@ -22,7 +22,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
22 .ppc_sys_name = "MPC86X", 22 .ppc_sys_name = "MPC86X",
23 .mask = 0xFFFFFFFF, 23 .mask = 0xFFFFFFFF,
24 .value = 0x00000000, 24 .value = 0x00000000,
25 .num_devices = 7, 25 .num_devices = 8,
26 .device_list = (enum ppc_sys_devices[]) 26 .device_list = (enum ppc_sys_devices[])
27 { 27 {
28 MPC8xx_CPM_FEC1, 28 MPC8xx_CPM_FEC1,
@@ -32,13 +32,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
32 MPC8xx_CPM_SCC4, 32 MPC8xx_CPM_SCC4,
33 MPC8xx_CPM_SMC1, 33 MPC8xx_CPM_SMC1,
34 MPC8xx_CPM_SMC2, 34 MPC8xx_CPM_SMC2,
35 MPC8xx_MDIO_FEC,
35 }, 36 },
36 }, 37 },
37 { 38 {
38 .ppc_sys_name = "MPC885", 39 .ppc_sys_name = "MPC885",
39 .mask = 0xFFFFFFFF, 40 .mask = 0xFFFFFFFF,
40 .value = 0x00000000, 41 .value = 0x00000000,
41 .num_devices = 8, 42 .num_devices = 9,
42 .device_list = (enum ppc_sys_devices[]) 43 .device_list = (enum ppc_sys_devices[])
43 { 44 {
44 MPC8xx_CPM_FEC1, 45 MPC8xx_CPM_FEC1,
@@ -49,6 +50,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
49 MPC8xx_CPM_SCC4, 50 MPC8xx_CPM_SCC4,
50 MPC8xx_CPM_SMC1, 51 MPC8xx_CPM_SMC1,
51 MPC8xx_CPM_SMC2, 52 MPC8xx_CPM_SMC2,
53 MPC8xx_MDIO_FEC,
52 }, 54 },
53 }, 55 },
54 { /* default match */ 56 { /* default match */
diff --git a/arch/ppc/syslib/pq2_devices.c b/arch/ppc/syslib/pq2_devices.c
index 8692d00c08c4..fefbc217a56d 100644
--- a/arch/ppc/syslib/pq2_devices.c
+++ b/arch/ppc/syslib/pq2_devices.c
@@ -369,6 +369,11 @@ struct platform_device ppc_sys_platform_devices[] = {
369 }, 369 },
370 }, 370 },
371 }, 371 },
372 [MPC82xx_MDIO_BB] = {
373 .name = "fsl-bb-mdio",
374 .id = 0,
375 .num_resources = 0,
376 },
372}; 377};
373 378
374static int __init mach_mpc82xx_fixup(struct platform_device *pdev) 379static int __init mach_mpc82xx_fixup(struct platform_device *pdev)
diff --git a/arch/ppc/syslib/pq2_sys.c b/arch/ppc/syslib/pq2_sys.c
index fee8948162b9..f52600c0db20 100644
--- a/arch/ppc/syslib/pq2_sys.c
+++ b/arch/ppc/syslib/pq2_sys.c
@@ -139,13 +139,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
139 .ppc_sys_name = "8272", 139 .ppc_sys_name = "8272",
140 .mask = 0x0000ff00, 140 .mask = 0x0000ff00,
141 .value = 0x00000c00, 141 .value = 0x00000c00,
142 .num_devices = 12, 142 .num_devices = 13,
143 .device_list = (enum ppc_sys_devices[]) 143 .device_list = (enum ppc_sys_devices[])
144 { 144 {
145 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, 145 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1,
146 MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4, 146 MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4,
147 MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, 147 MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI,
148 MPC82xx_CPM_I2C, MPC82xx_CPM_USB, MPC82xx_SEC1, 148 MPC82xx_CPM_I2C, MPC82xx_CPM_USB, MPC82xx_SEC1,
149 MPC82xx_MDIO_BB,
149 }, 150 },
150 }, 151 },
151 /* below is a list of the 8280 family of processors */ 152 /* below is a list of the 8280 family of processors */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 16:15:13 -0500