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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2005-05-01 21:22:34 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-05-01 21:22:34 -0400
commit15fd56867b6b94dc829d880bc078428eb41859c8 (patch)
tree2cadd2a246de12dade57a75cc57c296070d58712 /arch/ppc
parent7da21a02b3587157bd43910ea6d4c76661228ebb (diff)
[PATCH] ppc32: Workaround a cache flush issue on sleep
We are experiencing a problem when flushing the CPU caches before sleep on some laptop models using the 750FX CPU rev 1.X. While I haven't been able to figure out a proper explanation for what's going on, I do have a workaround that seem to work reliably and allows those machine to sleep and wakeup properly again. I'll re-update that code if/when I ever find exactly what is happening with those CPU revisions. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc')
-rw-r--r--arch/ppc/platforms/pmac_cache.S54
1 files changed, 42 insertions, 12 deletions
diff --git a/arch/ppc/platforms/pmac_cache.S b/arch/ppc/platforms/pmac_cache.S
index da34a9bc9299..fb977de6b704 100644
--- a/arch/ppc/platforms/pmac_cache.S
+++ b/arch/ppc/platforms/pmac_cache.S
@@ -64,27 +64,39 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
64 mtspr SPRN_HID0,r4 /* Disable DPM */ 64 mtspr SPRN_HID0,r4 /* Disable DPM */
65 sync 65 sync
66 66
67 /* disp-flush L1 */ 67 /* Disp-flush L1. We have a weird problem here that I never
68 li r4,0x4000 68 * totally figured out. On 750FX, using the ROM for the flush
69 mtctr r4 69 * results in a non-working flush. We use that workaround for
70 * now until I finally understand what's going on. --BenH
71 */
72
73 /* ROM base by default */
70 lis r4,0xfff0 74 lis r4,0xfff0
711: lwzx r0,r0,r4 75 mfpvr r3
76 srwi r3,r3,16
77 cmplwi cr0,r3,0x7000
78 bne+ 1f
79 /* RAM base on 750FX */
80 li r4,0
811: li r4,0x4000
82 mtctr r4
831: lwz r0,0(r4)
72 addi r4,r4,32 84 addi r4,r4,32
73 bdnz 1b 85 bdnz 1b
74 sync 86 sync
75 isync 87 isync
76 88
77 /* disable / invalidate / enable L1 data */ 89 /* Disable / invalidate / enable L1 data */
78 mfspr r3,SPRN_HID0 90 mfspr r3,SPRN_HID0
79 rlwinm r0,r0,0,~HID0_DCE 91 rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
80 mtspr SPRN_HID0,r3 92 mtspr SPRN_HID0,r3
81 sync 93 sync
82 isync 94 isync
83 ori r3,r3,HID0_DCE|HID0_DCI 95 ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
84 sync 96 sync
85 isync 97 isync
86 mtspr SPRN_HID0,r3 98 mtspr SPRN_HID0,r3
87 xori r3,r3,HID0_DCI 99 xori r3,r3,(HID0_DCI|HID0_ICFI)
88 mtspr SPRN_HID0,r3 100 mtspr SPRN_HID0,r3
89 sync 101 sync
90 102
@@ -110,11 +122,20 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
110 lis r4,2 122 lis r4,2
111 mtctr r4 123 mtctr r4
112 lis r4,0xfff0 124 lis r4,0xfff0
1131: lwzx r0,r0,r4 1251: lwz r0,0(r4)
126 addi r4,r4,32
127 bdnz 1b
128 sync
129 isync
130 lis r4,2
131 mtctr r4
132 lis r4,0xfff0
1331: dcbf 0,r4
114 addi r4,r4,32 134 addi r4,r4,32
115 bdnz 1b 135 bdnz 1b
116 sync 136 sync
117 isync 137 isync
138
118 /* now disable L2 */ 139 /* now disable L2 */
119 rlwinm r5,r5,0,~L2CR_L2E 140 rlwinm r5,r5,0,~L2CR_L2E
120 b 2f 141 b 2f
@@ -135,6 +156,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
135 mtspr SPRN_L2CR,r4 156 mtspr SPRN_L2CR,r4
136 sync 157 sync
137 isync 158 isync
159
160 /* Wait for the invalidation to complete */
1611: mfspr r3,SPRN_L2CR
162 rlwinm. r0,r3,0,31,31
163 bne 1b
164
165 /* Clear L2I */
138 xoris r4,r4,L2CR_L2I@h 166 xoris r4,r4,L2CR_L2I@h
139 sync 167 sync
140 mtspr SPRN_L2CR,r4 168 mtspr SPRN_L2CR,r4
@@ -142,14 +170,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
142 170
143 /* now disable the L1 data cache */ 171 /* now disable the L1 data cache */
144 mfspr r0,SPRN_HID0 172 mfspr r0,SPRN_HID0
145 rlwinm r0,r0,0,~HID0_DCE 173 rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
146 mtspr SPRN_HID0,r0 174 mtspr SPRN_HID0,r0
147 sync 175 sync
148 isync 176 isync
149 177
150 /* Restore HID0[DPM] to whatever it was before */ 178 /* Restore HID0[DPM] to whatever it was before */
151 sync 179 sync
152 mtspr SPRN_HID0,r8 180 mfspr r0,SPRN_HID0
181 rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
182 mtspr SPRN_HID0,r0
153 sync 183 sync
154 184
155 /* restore DR and EE */ 185 /* restore DR and EE */
@@ -201,7 +231,7 @@ flush_disable_745x:
201 mtctr r4 231 mtctr r4
202 li r4,0 232 li r4,0
2031: 2331:
204 lwzx r0,r0,r4 234 lwz r0,0(r4)
205 addi r4,r4,32 /* Go to start of next cache line */ 235 addi r4,r4,32 /* Go to start of next cache line */
206 bdnz 1b 236 bdnz 1b
207 isync 237 isync