[PATCH] ppc32: Added support for all MPC8548 internal interrupts

The MPC8548 has 48 internal interrupts and 12 external interrupts. The previous generation PowerQUICC III devices only had 32 internal and 12 external interrupts on the primary interrupt controller. Expanded the number of internal interrupts to 48 for all PowerQUICC III processors and moved the interrupt numbers for the external after the 48 internal interrupt lines, rather than putting the 12 new internal interrupts at the end and ifdef'ng the whole mess. As parted of this created a macro which represents the internal interrupt senses since they are the same on all PQ3 processors. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
author: Kumar Gala <galak@freescale.com> 2005-06-21 20:15:25 -0400
committer: Linus Torvalds <torvalds@ppc970.osdl.org> 2005-06-21 21:46:24 -0400
commit: 65145e060b1c933ebc4215c3b493f586e08a1d5c (patch)
tree: 7468cf3075cbd10863886ac1bd3d0f08b25fec2d /arch/ppc
parent: eee4146ab908188e556641f1cd7a10e894d10edb (diff)
4 files changed, 12 insertions, 137 deletions
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
index ba9f9f562c45..30397623fa6f 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
@@ -59,40 +59,8 @@ extern unsigned long total_memory;	/* in mm/init */
 unsigned char __res[sizeof (bd_t)];
 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
 static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: L2 Cache */
+        MPC85XX_INTERNAL_IRQ_SENSES,
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: ECM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCI/PCI-X */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: RIO Inbound Port Write Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: RIO Doorbell Inbound */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: RIO Outbound Message */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: RIO Inbound Message */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 0 Transmit */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 0 Receive */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 0 Receive/Transmit Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 1 Transmit */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 1 Receive */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 1 Receive/Transmit Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Fast Ethernet */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: CPM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
        0x0,                                            /* External  0: */
 #if defined(CONFIG_PCI)
        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI slot 0 */
@@ -159,7 +127,7 @@ mpc85xx_ads_init_IRQ(void)
        /* Skip reserved space and internal sources */
        openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
        /* Map PIC IRQs 0-11 */
-        openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
+        openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
        /* we let openpic interrupts starting from an offset, to
         * leave space for cascading interrupts underneath.
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
index 2d04bf599d2f..bee6633f4601 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -73,40 +73,8 @@ static int cds_pci_slot = 2;
 static volatile u8 * cadmus;
 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
 static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: L2 Cache */
+        MPC85XX_INTERNAL_IRQ_SENSES,
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: ECM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCI/PCI-X */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: RIO Inbound Port Write Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: RIO Doorbell Inbound */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: RIO Outbound Message */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: RIO Inbound Message */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 0 Transmit */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 0 Receive */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 0 Receive/Transmit Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 1 Transmit */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 1 Receive */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 1 Receive/Transmit Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Fast Ethernet */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: CPM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
 #if defined(CONFIG_PCI)
        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 0: PCI1 slot */
        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI1 slot */
@@ -182,7 +150,6 @@ void __init
 mpc85xx_cds_init_IRQ(void)
 {
        bd_t *binfo = (bd_t *) __res;
-        int i;
        /* Determine the Physical Address of the OpenPIC regs */
        phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
@@ -191,9 +158,13 @@ mpc85xx_cds_init_IRQ(void)
        OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
        /* Skip reserved space and internal sources */
+#ifdef CONFIG_MPC8548
+        openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200);
+#else
        openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
+#endif
        /* Map PIC IRQs 0-11 */
-        openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
+        openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
        /* we let openpic interrupts starting from an offset, to
         * leave space for cascading interrupts underneath.
diff --git a/arch/ppc/platforms/85xx/sbc85xx.c b/arch/ppc/platforms/85xx/sbc85xx.c
index 2d638c1c1bd6..a7cb625b2d0c 100644
--- a/arch/ppc/platforms/85xx/sbc85xx.c
+++ b/arch/ppc/platforms/85xx/sbc85xx.c
@@ -59,40 +59,8 @@ unsigned long pci_dram_offset = 0;
 extern unsigned long total_memory;      /* in mm/init */
 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
 static u_char sbc8560_openpic_initsenses[] __initdata = {
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: L2 Cache */
+        MPC85XX_INTERNAL_IRQ_SENSES,
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: ECM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCI/PCI-X */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: RIO Inbound Port Write Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: RIO Doorbell Inbound */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: RIO Outbound Message */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: RIO Inbound Message */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 0 Transmit */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 0 Receive */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 0 Receive/Transmit Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 1 Transmit */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 1 Receive */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 1 Receive/Transmit Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Fast Ethernet */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: CPM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
        0x0,                            /* External  0: */
        0x0,                            /* External  1: */
 #if defined(CONFIG_PCI)
@@ -159,7 +127,7 @@ sbc8560_init_IRQ(void)
        /* Skip reserved space and internal sources */
        openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
        /* Map PIC IRQs 0-11 */
-        openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
+        openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
        /* we let openpic interrupts starting from an offset, to 
         * leave space for cascading interrupts underneath.
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
index bc95836e417c..bc0a99638ff6 100644
--- a/arch/ppc/platforms/85xx/stx_gp3.c
+++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -72,38 +72,7 @@ unsigned long pci_dram_offset = 0;
 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
 static u8 gp3_openpic_initsenses[] __initdata = {
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: L2 Cache */
+        MPC85XX_INTERNAL_IRQ_SENSES,
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: ECM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCI/PCI-X */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: RIO Inbound Port Write Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: RIO Doorbell Inbound */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: RIO Outbound Message */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: RIO Inbound Message */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 0 Transmit */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 0 Receive */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 0 Receive/Transmit Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 1 Transmit */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 1 Receive */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 1 Receive/Transmit Error */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Fast Ethernet */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: CPM */
-        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
        0x0,                                            /* External  0: */
 #if defined(CONFIG_PCI)
        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI slot 0 */
@@ -200,7 +169,6 @@ static struct irqaction cpm2_irqaction = {
 static void __init
 gp3_init_IRQ(void)
 {
-        int i;
        bd_t *binfo = (bd_t *) __res;
        /*
@@ -218,7 +186,7 @@ gp3_init_IRQ(void)
        openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
        /* Map PIC IRQs 0-11 */
-        openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
+        openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
        /*
         * Let openpic interrupts starting from an offset, to
author	Kumar Gala <galak@freescale.com>	2005-06-21 20:15:25 -0400
committer	Linus Torvalds <torvalds@ppc970.osdl.org>	2005-06-21 21:46:24 -0400
commit	65145e060b1c933ebc4215c3b493f586e08a1d5c (patch)
tree	7468cf3075cbd10863886ac1bd3d0f08b25fec2d /arch/ppc
parent	eee4146ab908188e556641f1cd7a10e894d10edb (diff)

diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c index ba9f9f562c45..30397623fa6f 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c +++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
@@ -59,40 +59,8 @@ extern unsigned long total_memory; /* in mm/init */
59	unsigned char __res[sizeof (bd_t)];	59	unsigned char __res[sizeof (bd_t)];
60		60
61	/* Internal interrupts are all Level Sensitive, and Positive Polarity */	61	/* Internal interrupts are all Level Sensitive, and Positive Polarity */
62
63	static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {	62	static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
64	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */	63	MPC85XX_INTERNAL_IRQ_SENSES,
65	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
66	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
67	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
68	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
69	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
70	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
71	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
72	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
73	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
74	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
75	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
76	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
77	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
78	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
79	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
80	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
81	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
82	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
83	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
84	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
85	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
86	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
87	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
88	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
89	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
90	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
91	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
92	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
93	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
94	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
95	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
96	0x0, /* External 0: */	64	0x0, /* External 0: */
97	#if defined(CONFIG_PCI)	65	#if defined(CONFIG_PCI)
98	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */	66	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
@@ -159,7 +127,7 @@ mpc85xx_ads_init_IRQ(void)
159	/* Skip reserved space and internal sources */	127	/* Skip reserved space and internal sources */
160	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);	128	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
161	/* Map PIC IRQs 0-11 */	129	/* Map PIC IRQs 0-11 */
162	openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);	130	openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
163		131
164	/* we let openpic interrupts starting from an offset, to	132	/* we let openpic interrupts starting from an offset, to
165	* leave space for cascading interrupts underneath.	133	* leave space for cascading interrupts underneath.


diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c index 2d04bf599d2f..bee6633f4601 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c +++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -73,40 +73,8 @@ static int cds_pci_slot = 2;
73	static volatile u8 * cadmus;	73	static volatile u8 * cadmus;
74		74
75	/* Internal interrupts are all Level Sensitive, and Positive Polarity */	75	/* Internal interrupts are all Level Sensitive, and Positive Polarity */
76
77	static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {	76	static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
78	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */	77	MPC85XX_INTERNAL_IRQ_SENSES,
79	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
80	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
81	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
82	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
83	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
84	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
85	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
86	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
87	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
88	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
89	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
90	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
91	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
92	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
93	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
94	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
95	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
96	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
97	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
98	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
99	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
100	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
101	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
102	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
103	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
104	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
105	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
106	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
107	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
108	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
109	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
110	#if defined(CONFIG_PCI)	78	#if defined(CONFIG_PCI)
111	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */	79	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
112	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */	80	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
@@ -182,7 +150,6 @@ void __init
182	mpc85xx_cds_init_IRQ(void)	150	mpc85xx_cds_init_IRQ(void)
183	{	151	{
184	bd_t binfo = (bd_t ) __res;	152	bd_t binfo = (bd_t ) __res;
185	int i;
186		153
187	/* Determine the Physical Address of the OpenPIC regs */	154	/* Determine the Physical Address of the OpenPIC regs */
188	phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;	155	phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
@@ -191,9 +158,13 @@ mpc85xx_cds_init_IRQ(void)
191	OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);	158	OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
192		159
193	/* Skip reserved space and internal sources */	160	/* Skip reserved space and internal sources */
		161	#ifdef CONFIG_MPC8548
		162	openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200);
		163	#else
194	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);	164	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
		165	#endif
195	/* Map PIC IRQs 0-11 */	166	/* Map PIC IRQs 0-11 */
196	openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);	167	openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
197		168
198	/* we let openpic interrupts starting from an offset, to	169	/* we let openpic interrupts starting from an offset, to
199	* leave space for cascading interrupts underneath.	170	* leave space for cascading interrupts underneath.


diff --git a/arch/ppc/platforms/85xx/sbc85xx.c b/arch/ppc/platforms/85xx/sbc85xx.c index 2d638c1c1bd6..a7cb625b2d0c 100644 --- a/arch/ppc/platforms/85xx/sbc85xx.c +++ b/arch/ppc/platforms/85xx/sbc85xx.c
@@ -59,40 +59,8 @@ unsigned long pci_dram_offset = 0;
59	extern unsigned long total_memory; /* in mm/init */	59	extern unsigned long total_memory; /* in mm/init */
60		60
61	/* Internal interrupts are all Level Sensitive, and Positive Polarity */	61	/* Internal interrupts are all Level Sensitive, and Positive Polarity */
62
63	static u_char sbc8560_openpic_initsenses[] __initdata = {	62	static u_char sbc8560_openpic_initsenses[] __initdata = {
64	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */	63	MPC85XX_INTERNAL_IRQ_SENSES,
65	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
66	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
67	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
68	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
69	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
70	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
71	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
72	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
73	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
74	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
75	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
76	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
77	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
78	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
79	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
80	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
81	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
82	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
83	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
84	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
85	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
86	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
87	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
88	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
89	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
90	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
91	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
92	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
93	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
94	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
95	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
96	0x0, /* External 0: */	64	0x0, /* External 0: */
97	0x0, /* External 1: */	65	0x0, /* External 1: */
98	#if defined(CONFIG_PCI)	66	#if defined(CONFIG_PCI)
@@ -159,7 +127,7 @@ sbc8560_init_IRQ(void)
159	/* Skip reserved space and internal sources */	127	/* Skip reserved space and internal sources */
160	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);	128	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
161	/* Map PIC IRQs 0-11 */	129	/* Map PIC IRQs 0-11 */
162	openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);	130	openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
163		131
164	/* we let openpic interrupts starting from an offset, to	132	/* we let openpic interrupts starting from an offset, to
165	* leave space for cascading interrupts underneath.	133	* leave space for cascading interrupts underneath.


diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c index bc95836e417c..bc0a99638ff6 100644 --- a/arch/ppc/platforms/85xx/stx_gp3.c +++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -72,38 +72,7 @@ unsigned long pci_dram_offset = 0;
72		72
73	/* Internal interrupts are all Level Sensitive, and Positive Polarity */	73	/* Internal interrupts are all Level Sensitive, and Positive Polarity */
74	static u8 gp3_openpic_initsenses[] __initdata = {	74	static u8 gp3_openpic_initsenses[] __initdata = {
75	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */	75	MPC85XX_INTERNAL_IRQ_SENSES,
76	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
77	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
78	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
79	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
80	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
81	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
82	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
83	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
84	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
85	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
86	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
87	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
88	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
89	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
90	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
91	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
92	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
93	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
94	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
95	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
96	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
97	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
98	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
99	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
100	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
101	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
102	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
103	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
104	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
105	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
106	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
107	0x0, /* External 0: */	76	0x0, /* External 0: */
108	#if defined(CONFIG_PCI)	77	#if defined(CONFIG_PCI)
109	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */	78	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
@@ -200,7 +169,6 @@ static struct irqaction cpm2_irqaction = {
200	static void __init	169	static void __init
201	gp3_init_IRQ(void)	170	gp3_init_IRQ(void)
202	{	171	{
203	int i;
204	bd_t binfo = (bd_t ) __res;	172	bd_t binfo = (bd_t ) __res;
205		173
206	/*	174	/*
@@ -218,7 +186,7 @@ gp3_init_IRQ(void)
218	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);	186	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
219		187
220	/* Map PIC IRQs 0-11 */	188	/* Map PIC IRQs 0-11 */
221	openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);	189	openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
222		190
223	/*	191	/*
224	* Let openpic interrupts starting from an offset, to	192	* Let openpic interrupts starting from an offset, to