diff options
author | David Gibson <david@gibson.dropbear.id.au> | 2005-11-01 01:28:10 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2005-11-01 05:49:02 -0500 |
commit | a0e60b2033b30a6bb8479629001cf98e58e4079a (patch) | |
tree | 6386eeca340a25c4ae1876f2f9663f94628c8cc3 /arch/ppc | |
parent | 031ef0a72aa8f7ee63ae9f307c1bcff92b3ccc2c (diff) |
[PATCH] powerpc: Merge bitops.h
Here's a revised version. This re-introduces the set_bits() function
from ppc64, which I removed because I thought it was unused (it exists
on no other arch). In fact it is used in the powermac interrupt code
(but not on pSeries).
- We use LARXL/STCXL macros to generate the right (32 or 64 bit)
instructions, similar to LDL/STL from ppc_asm.h, used in fpu.S
- ppc32 previously used a full "sync" barrier at the end of
test_and_*_bit(), whereas ppc64 used an "isync". The merged version
uses "isync", since I believe that's sufficient.
- The ppc64 versions of then minix_*() bitmap functions have changed
semantics. Previously on ppc64, these functions were big-endian
(that is bit 0 was the LSB in the first 64-bit, big-endian word).
On ppc32 (and x86, for that matter, they were little-endian. As far
as I can tell, the big-endian usage was simply wrong - I guess
no-one ever tried to use minixfs on ppc64.
- On ppc32 find_next_bit() and find_next_zero_bit() are no longer
inline (they were already out-of-line on ppc64).
- For ppc64, sched_find_first_bit() has moved from mmu_context.h to
the merged bitops. What it was doing in mmu_context.h in the first
place, I have no idea.
- The fls() function is now implemented using the cntlzw instruction
on ppc64, instead of generic_fls(), as it already was on ppc32.
- For ARCH=ppc, this patch requires adding arch/powerpc/lib to the
arch/ppc/Makefile. This in turn requires some changes to
arch/powerpc/lib/Makefile which didn't correctly handle ARCH=ppc.
Built and running on G5.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc')
-rw-r--r-- | arch/ppc/Makefile | 3 | ||||
-rw-r--r-- | arch/ppc/kernel/bitops.c | 126 |
2 files changed, 2 insertions, 127 deletions
diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile index 94d5716fa7c3..e719a4933af1 100644 --- a/arch/ppc/Makefile +++ b/arch/ppc/Makefile | |||
@@ -66,7 +66,8 @@ head-$(CONFIG_PPC_FPU) += arch/powerpc/kernel/fpu.o | |||
66 | core-y += arch/ppc/kernel/ arch/powerpc/kernel/ \ | 66 | core-y += arch/ppc/kernel/ arch/powerpc/kernel/ \ |
67 | arch/ppc/platforms/ \ | 67 | arch/ppc/platforms/ \ |
68 | arch/ppc/mm/ arch/ppc/lib/ \ | 68 | arch/ppc/mm/ arch/ppc/lib/ \ |
69 | arch/ppc/syslib/ arch/powerpc/sysdev/ | 69 | arch/ppc/syslib/ arch/powerpc/sysdev/ \ |
70 | arch/powerpc/lib/ | ||
70 | core-$(CONFIG_4xx) += arch/ppc/platforms/4xx/ | 71 | core-$(CONFIG_4xx) += arch/ppc/platforms/4xx/ |
71 | core-$(CONFIG_83xx) += arch/ppc/platforms/83xx/ | 72 | core-$(CONFIG_83xx) += arch/ppc/platforms/83xx/ |
72 | core-$(CONFIG_85xx) += arch/ppc/platforms/85xx/ | 73 | core-$(CONFIG_85xx) += arch/ppc/platforms/85xx/ |
diff --git a/arch/ppc/kernel/bitops.c b/arch/ppc/kernel/bitops.c deleted file mode 100644 index 7f53d193968b..000000000000 --- a/arch/ppc/kernel/bitops.c +++ /dev/null | |||
@@ -1,126 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1996 Paul Mackerras. | ||
3 | */ | ||
4 | |||
5 | #include <linux/kernel.h> | ||
6 | #include <linux/bitops.h> | ||
7 | |||
8 | /* | ||
9 | * If the bitops are not inlined in bitops.h, they are defined here. | ||
10 | * -- paulus | ||
11 | */ | ||
12 | #if !__INLINE_BITOPS | ||
13 | void set_bit(int nr, volatile void * addr) | ||
14 | { | ||
15 | unsigned long old; | ||
16 | unsigned long mask = 1 << (nr & 0x1f); | ||
17 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
18 | |||
19 | __asm__ __volatile__(SMP_WMB "\n\ | ||
20 | 1: lwarx %0,0,%3 \n\ | ||
21 | or %0,%0,%2 \n" | ||
22 | PPC405_ERR77(0,%3) | ||
23 | " stwcx. %0,0,%3 \n\ | ||
24 | bne 1b" | ||
25 | SMP_MB | ||
26 | : "=&r" (old), "=m" (*p) | ||
27 | : "r" (mask), "r" (p), "m" (*p) | ||
28 | : "cc" ); | ||
29 | } | ||
30 | |||
31 | void clear_bit(int nr, volatile void *addr) | ||
32 | { | ||
33 | unsigned long old; | ||
34 | unsigned long mask = 1 << (nr & 0x1f); | ||
35 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
36 | |||
37 | __asm__ __volatile__(SMP_WMB "\n\ | ||
38 | 1: lwarx %0,0,%3 \n\ | ||
39 | andc %0,%0,%2 \n" | ||
40 | PPC405_ERR77(0,%3) | ||
41 | " stwcx. %0,0,%3 \n\ | ||
42 | bne 1b" | ||
43 | SMP_MB | ||
44 | : "=&r" (old), "=m" (*p) | ||
45 | : "r" (mask), "r" (p), "m" (*p) | ||
46 | : "cc"); | ||
47 | } | ||
48 | |||
49 | void change_bit(int nr, volatile void *addr) | ||
50 | { | ||
51 | unsigned long old; | ||
52 | unsigned long mask = 1 << (nr & 0x1f); | ||
53 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
54 | |||
55 | __asm__ __volatile__(SMP_WMB "\n\ | ||
56 | 1: lwarx %0,0,%3 \n\ | ||
57 | xor %0,%0,%2 \n" | ||
58 | PPC405_ERR77(0,%3) | ||
59 | " stwcx. %0,0,%3 \n\ | ||
60 | bne 1b" | ||
61 | SMP_MB | ||
62 | : "=&r" (old), "=m" (*p) | ||
63 | : "r" (mask), "r" (p), "m" (*p) | ||
64 | : "cc"); | ||
65 | } | ||
66 | |||
67 | int test_and_set_bit(int nr, volatile void *addr) | ||
68 | { | ||
69 | unsigned int old, t; | ||
70 | unsigned int mask = 1 << (nr & 0x1f); | ||
71 | volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); | ||
72 | |||
73 | __asm__ __volatile__(SMP_WMB "\n\ | ||
74 | 1: lwarx %0,0,%4 \n\ | ||
75 | or %1,%0,%3 \n" | ||
76 | PPC405_ERR77(0,%4) | ||
77 | " stwcx. %1,0,%4 \n\ | ||
78 | bne 1b" | ||
79 | SMP_MB | ||
80 | : "=&r" (old), "=&r" (t), "=m" (*p) | ||
81 | : "r" (mask), "r" (p), "m" (*p) | ||
82 | : "cc"); | ||
83 | |||
84 | return (old & mask) != 0; | ||
85 | } | ||
86 | |||
87 | int test_and_clear_bit(int nr, volatile void *addr) | ||
88 | { | ||
89 | unsigned int old, t; | ||
90 | unsigned int mask = 1 << (nr & 0x1f); | ||
91 | volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); | ||
92 | |||
93 | __asm__ __volatile__(SMP_WMB "\n\ | ||
94 | 1: lwarx %0,0,%4 \n\ | ||
95 | andc %1,%0,%3 \n" | ||
96 | PPC405_ERR77(0,%4) | ||
97 | " stwcx. %1,0,%4 \n\ | ||
98 | bne 1b" | ||
99 | SMP_MB | ||
100 | : "=&r" (old), "=&r" (t), "=m" (*p) | ||
101 | : "r" (mask), "r" (p), "m" (*p) | ||
102 | : "cc"); | ||
103 | |||
104 | return (old & mask) != 0; | ||
105 | } | ||
106 | |||
107 | int test_and_change_bit(int nr, volatile void *addr) | ||
108 | { | ||
109 | unsigned int old, t; | ||
110 | unsigned int mask = 1 << (nr & 0x1f); | ||
111 | volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); | ||
112 | |||
113 | __asm__ __volatile__(SMP_WMB "\n\ | ||
114 | 1: lwarx %0,0,%4 \n\ | ||
115 | xor %1,%0,%3 \n" | ||
116 | PPC405_ERR77(0,%4) | ||
117 | " stwcx. %1,0,%4 \n\ | ||
118 | bne 1b" | ||
119 | SMP_MB | ||
120 | : "=&r" (old), "=&r" (t), "=m" (*p) | ||
121 | : "r" (mask), "r" (p), "m" (*p) | ||
122 | : "cc"); | ||
123 | |||
124 | return (old & mask) != 0; | ||
125 | } | ||
126 | #endif /* !__INLINE_BITOPS */ | ||