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authorStephen Rothwell <sfr@canb.auug.org.au>2005-09-26 23:51:59 -0400
committerStephen Rothwell <sfr@canb.auug.org.au>2005-09-26 23:51:59 -0400
commitbbeb3f4c55f666df7bcd2655b303dfb8c4d1a119 (patch)
tree30180a33fb5bb9a5c633e93d533b7f4ffc800e2e /arch/ppc64
parent51a0885ed7f883758462926b35fbd6f09f9c717c (diff)
powerpc: clean up after powermac build merge
Complete moving arch/ppc64/kernel/mpic.h, include/asm-ppc/reg.h, include/asm-ppc64/kdebug.h and include/asm-ppc64/kprobes.h Add arch/powerpc/platforms/Makefile and use it from arch/powerpc/Makefile Introduce OLDARCH temporarily so we can point back to the originating architecture Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Diffstat (limited to 'arch/ppc64')
-rw-r--r--arch/ppc64/kernel/kprobes.c1
-rw-r--r--arch/ppc64/kernel/maple_setup.c3
-rw-r--r--arch/ppc64/kernel/mpic.c3
-rw-r--r--arch/ppc64/kernel/mpic.h273
-rw-r--r--arch/ppc64/kernel/pSeries_setup.c2
-rw-r--r--arch/ppc64/kernel/pSeries_smp.c2
-rw-r--r--arch/ppc64/kernel/pmac_setup.c2
-rw-r--r--arch/ppc64/kernel/pmac_smp.c3
-rw-r--r--arch/ppc64/kernel/rtas_pci.c2
-rw-r--r--arch/ppc64/kernel/smp.c3
-rw-r--r--arch/ppc64/kernel/traps.c4
11 files changed, 10 insertions, 288 deletions
diff --git a/arch/ppc64/kernel/kprobes.c b/arch/ppc64/kernel/kprobes.c
index 7e80d49c589a..abb90e67534a 100644
--- a/arch/ppc64/kernel/kprobes.c
+++ b/arch/ppc64/kernel/kprobes.c
@@ -395,7 +395,6 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
395 if (post_kprobe_handler(args->regs)) 395 if (post_kprobe_handler(args->regs))
396 ret = NOTIFY_STOP; 396 ret = NOTIFY_STOP;
397 break; 397 break;
398 case DIE_GPF:
399 case DIE_PAGE_FAULT: 398 case DIE_PAGE_FAULT:
400 if (kprobe_running() && 399 if (kprobe_running() &&
401 kprobe_fault_handler(args->regs, args->trapnr)) 400 kprobe_fault_handler(args->regs, args->trapnr))
diff --git a/arch/ppc64/kernel/maple_setup.c b/arch/ppc64/kernel/maple_setup.c
index fc0567498a3a..2a7fae01eee1 100644
--- a/arch/ppc64/kernel/maple_setup.c
+++ b/arch/ppc64/kernel/maple_setup.c
@@ -59,8 +59,7 @@
59#include <asm/time.h> 59#include <asm/time.h>
60#include <asm/of_device.h> 60#include <asm/of_device.h>
61#include <asm/lmb.h> 61#include <asm/lmb.h>
62 62#include <asm/mpic.h>
63#include "mpic.h"
64 63
65#ifdef DEBUG 64#ifdef DEBUG
66#define DBG(fmt...) udbg_printf(fmt) 65#define DBG(fmt...) udbg_printf(fmt)
diff --git a/arch/ppc64/kernel/mpic.c b/arch/ppc64/kernel/mpic.c
index cc262a05ddb4..ec22321342ad 100644
--- a/arch/ppc64/kernel/mpic.c
+++ b/arch/ppc64/kernel/mpic.c
@@ -31,8 +31,7 @@
31#include <asm/pgtable.h> 31#include <asm/pgtable.h>
32#include <asm/irq.h> 32#include <asm/irq.h>
33#include <asm/machdep.h> 33#include <asm/machdep.h>
34 34#include <asm/mpic.h>
35#include "mpic.h"
36 35
37#ifdef DEBUG 36#ifdef DEBUG
38#define DBG(fmt...) printk(fmt) 37#define DBG(fmt...) printk(fmt)
diff --git a/arch/ppc64/kernel/mpic.h b/arch/ppc64/kernel/mpic.h
deleted file mode 100644
index ca78a7f10528..000000000000
--- a/arch/ppc64/kernel/mpic.h
+++ /dev/null
@@ -1,273 +0,0 @@
1#include <linux/irq.h>
2
3/*
4 * Global registers
5 */
6
7#define MPIC_GREG_BASE 0x01000
8
9#define MPIC_GREG_FEATURE_0 0x00000
10#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
11#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
12#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
13#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
14#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
15#define MPIC_GREG_FEATURE_1 0x00010
16#define MPIC_GREG_GLOBAL_CONF_0 0x00020
17#define MPIC_GREG_GCONF_RESET 0x80000000
18#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
19#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
20#define MPIC_GREG_GLOBAL_CONF_1 0x00030
21#define MPIC_GREG_VENDOR_0 0x00040
22#define MPIC_GREG_VENDOR_1 0x00050
23#define MPIC_GREG_VENDOR_2 0x00060
24#define MPIC_GREG_VENDOR_3 0x00070
25#define MPIC_GREG_VENDOR_ID 0x00080
26#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
27#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
28#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
29#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
30#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
31#define MPIC_GREG_PROCESSOR_INIT 0x00090
32#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
33#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
34#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
35#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
36#define MPIC_GREG_SPURIOUS 0x000e0
37#define MPIC_GREG_TIMER_FREQ 0x000f0
38
39/*
40 *
41 * Timer registers
42 */
43#define MPIC_TIMER_BASE 0x01100
44#define MPIC_TIMER_STRIDE 0x40
45
46#define MPIC_TIMER_CURRENT_CNT 0x00000
47#define MPIC_TIMER_BASE_CNT 0x00010
48#define MPIC_TIMER_VECTOR_PRI 0x00020
49#define MPIC_TIMER_DESTINATION 0x00030
50
51/*
52 * Per-Processor registers
53 */
54
55#define MPIC_CPU_THISBASE 0x00000
56#define MPIC_CPU_BASE 0x20000
57#define MPIC_CPU_STRIDE 0x01000
58
59#define MPIC_CPU_IPI_DISPATCH_0 0x00040
60#define MPIC_CPU_IPI_DISPATCH_1 0x00050
61#define MPIC_CPU_IPI_DISPATCH_2 0x00060
62#define MPIC_CPU_IPI_DISPATCH_3 0x00070
63#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
64#define MPIC_CPU_TASKPRI_MASK 0x0000000f
65#define MPIC_CPU_WHOAMI 0x00090
66#define MPIC_CPU_WHOAMI_MASK 0x0000001f
67#define MPIC_CPU_INTACK 0x000a0
68#define MPIC_CPU_EOI 0x000b0
69
70/*
71 * Per-source registers
72 */
73
74#define MPIC_IRQ_BASE 0x10000
75#define MPIC_IRQ_STRIDE 0x00020
76#define MPIC_IRQ_VECTOR_PRI 0x00000
77#define MPIC_VECPRI_MASK 0x80000000
78#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
79#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
80#define MPIC_VECPRI_PRIORITY_SHIFT 16
81#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
82#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
83#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
84#define MPIC_VECPRI_POLARITY_MASK 0x00800000
85#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
86#define MPIC_VECPRI_SENSE_EDGE 0x00000000
87#define MPIC_VECPRI_SENSE_MASK 0x00400000
88#define MPIC_IRQ_DESTINATION 0x00010
89
90#define MPIC_MAX_IRQ_SOURCES 2048
91#define MPIC_MAX_CPUS 32
92#define MPIC_MAX_ISU 32
93
94/*
95 * Special vector numbers (internal use only)
96 */
97#define MPIC_VEC_SPURRIOUS 255
98#define MPIC_VEC_IPI_3 254
99#define MPIC_VEC_IPI_2 253
100#define MPIC_VEC_IPI_1 252
101#define MPIC_VEC_IPI_0 251
102
103/* unused */
104#define MPIC_VEC_TIMER_3 250
105#define MPIC_VEC_TIMER_2 249
106#define MPIC_VEC_TIMER_1 248
107#define MPIC_VEC_TIMER_0 247
108
109/* Type definition of the cascade handler */
110typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
111
112#ifdef CONFIG_MPIC_BROKEN_U3
113/* Fixup table entry */
114struct mpic_irq_fixup
115{
116 u8 __iomem *base;
117 unsigned int irq;
118};
119#endif /* CONFIG_MPIC_BROKEN_U3 */
120
121
122/* The instance data of a given MPIC */
123struct mpic
124{
125 /* The "linux" controller struct */
126 hw_irq_controller hc_irq;
127#ifdef CONFIG_SMP
128 hw_irq_controller hc_ipi;
129#endif
130 const char *name;
131 /* Flags */
132 unsigned int flags;
133 /* How many irq sources in a given ISU */
134 unsigned int isu_size;
135 unsigned int isu_shift;
136 unsigned int isu_mask;
137 /* Offset of irq vector numbers */
138 unsigned int irq_offset;
139 unsigned int irq_count;
140 /* Offset of ipi vector numbers */
141 unsigned int ipi_offset;
142 /* Number of sources */
143 unsigned int num_sources;
144 /* Number of CPUs */
145 unsigned int num_cpus;
146 /* cascade handler */
147 mpic_cascade_t cascade;
148 void *cascade_data;
149 unsigned int cascade_vec;
150 /* senses array */
151 unsigned char *senses;
152 unsigned int senses_count;
153
154#ifdef CONFIG_MPIC_BROKEN_U3
155 /* The fixup table */
156 struct mpic_irq_fixup *fixups;
157 spinlock_t fixup_lock;
158#endif
159
160 /* The various ioremap'ed bases */
161 volatile u32 __iomem *gregs;
162 volatile u32 __iomem *tmregs;
163 volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
164 volatile u32 __iomem *isus[MPIC_MAX_ISU];
165
166 /* link */
167 struct mpic *next;
168};
169
170/* This is the primary controller, only that one has IPIs and
171 * has afinity control. A non-primary MPIC always uses CPU0
172 * registers only
173 */
174#define MPIC_PRIMARY 0x00000001
175/* Set this for a big-endian MPIC */
176#define MPIC_BIG_ENDIAN 0x00000002
177/* Broken U3 MPIC */
178#define MPIC_BROKEN_U3 0x00000004
179/* Broken IPI registers (autodetected) */
180#define MPIC_BROKEN_IPI 0x00000008
181/* MPIC wants a reset */
182#define MPIC_WANTS_RESET 0x00000010
183
184/* Allocate the controller structure and setup the linux irq descs
185 * for the range if interrupts passed in. No HW initialization is
186 * actually performed.
187 *
188 * @phys_addr: physial base address of the MPIC
189 * @flags: flags, see constants above
190 * @isu_size: number of interrupts in an ISU. Use 0 to use a
191 * standard ISU-less setup (aka powermac)
192 * @irq_offset: first irq number to assign to this mpic
193 * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
194 * to match the number of sources
195 * @ipi_offset: first irq number to assign to this mpic IPI sources,
196 * used only on primary mpic
197 * @senses: array of sense values
198 * @senses_num: number of entries in the array
199 *
200 * Note about the sense array. If none is passed, all interrupts are
201 * setup to be level negative unless MPIC_BROKEN_U3 is set in which
202 * case they are edge positive (and the array is ignored anyway).
203 * The values in the array start at the first source of the MPIC,
204 * that is senses[0] correspond to linux irq "irq_offset".
205 */
206extern struct mpic *mpic_alloc(unsigned long phys_addr,
207 unsigned int flags,
208 unsigned int isu_size,
209 unsigned int irq_offset,
210 unsigned int irq_count,
211 unsigned int ipi_offset,
212 unsigned char *senses,
213 unsigned int senses_num,
214 const char *name);
215
216/* Assign ISUs, to call before mpic_init()
217 *
218 * @mpic: controller structure as returned by mpic_alloc()
219 * @isu_num: ISU number
220 * @phys_addr: physical address of the ISU
221 */
222extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
223 unsigned long phys_addr);
224
225/* Initialize the controller. After this has been called, none of the above
226 * should be called again for this mpic
227 */
228extern void mpic_init(struct mpic *mpic);
229
230/* Setup a cascade. Currently, only one cascade is supported this
231 * way, though you can always do a normal request_irq() and add
232 * other cascades this way. You should call this _after_ having
233 * added all the ISUs
234 *
235 * @irq_no: "linux" irq number of the cascade (that is offset'ed vector)
236 * @handler: cascade handler function
237 */
238extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
239 void *data);
240
241/*
242 * All of the following functions must only be used after the
243 * ISUs have been assigned and the controller fully initialized
244 * with mpic_init()
245 */
246
247
248/* Change/Read the priority of an interrupt. Default is 8 for irqs and
249 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
250 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
251 */
252extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
253extern unsigned int mpic_irq_get_priority(unsigned int irq);
254
255/* Setup a non-boot CPU */
256extern void mpic_setup_this_cpu(void);
257
258/* Clean up for kexec (or cpu offline or ...) */
259extern void mpic_teardown_this_cpu(int secondary);
260
261/* Request IPIs on primary mpic */
262extern void mpic_request_ipis(void);
263
264/* Send an IPI (non offseted number 0..3) */
265extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
266
267/* Fetch interrupt from a given mpic */
268extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
269/* This one gets to the primary mpic */
270extern int mpic_get_irq(struct pt_regs *regs);
271
272/* global mpic for pSeries */
273extern struct mpic *pSeries_mpic;
diff --git a/arch/ppc64/kernel/pSeries_setup.c b/arch/ppc64/kernel/pSeries_setup.c
index 3009701eb90d..b9bcff21b463 100644
--- a/arch/ppc64/kernel/pSeries_setup.c
+++ b/arch/ppc64/kernel/pSeries_setup.c
@@ -62,9 +62,9 @@
62#include <asm/xics.h> 62#include <asm/xics.h>
63#include <asm/firmware.h> 63#include <asm/firmware.h>
64#include <asm/pmc.h> 64#include <asm/pmc.h>
65#include <asm/mpic.h>
65 66
66#include "i8259.h" 67#include "i8259.h"
67#include "mpic.h"
68#include "pci.h" 68#include "pci.h"
69 69
70#ifdef DEBUG 70#ifdef DEBUG
diff --git a/arch/ppc64/kernel/pSeries_smp.c b/arch/ppc64/kernel/pSeries_smp.c
index d2c7e2c4733b..5d1ed850f47b 100644
--- a/arch/ppc64/kernel/pSeries_smp.c
+++ b/arch/ppc64/kernel/pSeries_smp.c
@@ -46,8 +46,8 @@
46#include <asm/rtas.h> 46#include <asm/rtas.h>
47#include <asm/plpar_wrappers.h> 47#include <asm/plpar_wrappers.h>
48#include <asm/pSeries_reconfig.h> 48#include <asm/pSeries_reconfig.h>
49#include <asm/mpic.h>
49 50
50#include "mpic.h"
51#include "bpa_iic.h" 51#include "bpa_iic.h"
52 52
53#ifdef DEBUG 53#ifdef DEBUG
diff --git a/arch/ppc64/kernel/pmac_setup.c b/arch/ppc64/kernel/pmac_setup.c
index bb0c3bfbb7e2..497c3cd95bc3 100644
--- a/arch/ppc64/kernel/pmac_setup.c
+++ b/arch/ppc64/kernel/pmac_setup.c
@@ -72,9 +72,9 @@
72#include <asm/lmb.h> 72#include <asm/lmb.h>
73#include <asm/smu.h> 73#include <asm/smu.h>
74#include <asm/pmc.h> 74#include <asm/pmc.h>
75#include <asm/mpic.h>
75 76
76#include "pmac.h" 77#include "pmac.h"
77#include "mpic.h"
78 78
79#ifdef DEBUG 79#ifdef DEBUG
80#define DBG(fmt...) udbg_printf(fmt) 80#define DBG(fmt...) udbg_printf(fmt)
diff --git a/arch/ppc64/kernel/pmac_smp.c b/arch/ppc64/kernel/pmac_smp.c
index 9fd23ea55bc9..3a1683f5b07f 100644
--- a/arch/ppc64/kernel/pmac_smp.c
+++ b/arch/ppc64/kernel/pmac_smp.c
@@ -51,8 +51,7 @@
51#include <asm/cacheflush.h> 51#include <asm/cacheflush.h>
52#include <asm/keylargo.h> 52#include <asm/keylargo.h>
53#include <asm/pmac_low_i2c.h> 53#include <asm/pmac_low_i2c.h>
54 54#include <asm/mpic.h>
55#include "mpic.h"
56 55
57#ifdef DEBUG 56#ifdef DEBUG
58#define DBG(fmt...) udbg_printf(fmt) 57#define DBG(fmt...) udbg_printf(fmt)
diff --git a/arch/ppc64/kernel/rtas_pci.c b/arch/ppc64/kernel/rtas_pci.c
index 4a9719b48abe..4d920dd41dc6 100644
--- a/arch/ppc64/kernel/rtas_pci.c
+++ b/arch/ppc64/kernel/rtas_pci.c
@@ -38,8 +38,8 @@
38#include <asm/pci-bridge.h> 38#include <asm/pci-bridge.h>
39#include <asm/iommu.h> 39#include <asm/iommu.h>
40#include <asm/rtas.h> 40#include <asm/rtas.h>
41#include <asm/mpic.h>
41 42
42#include "mpic.h"
43#include "pci.h" 43#include "pci.h"
44 44
45/* RTAS tokens */ 45/* RTAS tokens */
diff --git a/arch/ppc64/kernel/smp.c b/arch/ppc64/kernel/smp.c
index 793b562da653..6f4f3da12a63 100644
--- a/arch/ppc64/kernel/smp.c
+++ b/arch/ppc64/kernel/smp.c
@@ -45,8 +45,7 @@
45#include <asm/cputable.h> 45#include <asm/cputable.h>
46#include <asm/system.h> 46#include <asm/system.h>
47#include <asm/abs_addr.h> 47#include <asm/abs_addr.h>
48 48#include <asm/mpic.h>
49#include "mpic.h"
50 49
51#ifdef DEBUG 50#ifdef DEBUG
52#define DBG(fmt...) udbg_printf(fmt) 51#define DBG(fmt...) udbg_printf(fmt)
diff --git a/arch/ppc64/kernel/traps.c b/arch/ppc64/kernel/traps.c
index 5c4647b2c5f3..a728c9f0b53f 100644
--- a/arch/ppc64/kernel/traps.c
+++ b/arch/ppc64/kernel/traps.c
@@ -62,7 +62,7 @@ EXPORT_SYMBOL(__debugger_dabr_match);
62EXPORT_SYMBOL(__debugger_fault_handler); 62EXPORT_SYMBOL(__debugger_fault_handler);
63#endif 63#endif
64 64
65struct notifier_block *ppc64_die_chain; 65struct notifier_block *powerpc_die_chain;
66static DEFINE_SPINLOCK(die_notifier_lock); 66static DEFINE_SPINLOCK(die_notifier_lock);
67 67
68int register_die_notifier(struct notifier_block *nb) 68int register_die_notifier(struct notifier_block *nb)
@@ -71,7 +71,7 @@ int register_die_notifier(struct notifier_block *nb)
71 unsigned long flags; 71 unsigned long flags;
72 72
73 spin_lock_irqsave(&die_notifier_lock, flags); 73 spin_lock_irqsave(&die_notifier_lock, flags);
74 err = notifier_chain_register(&ppc64_die_chain, nb); 74 err = notifier_chain_register(&powerpc_die_chain, nb);
75 spin_unlock_irqrestore(&die_notifier_lock, flags); 75 spin_unlock_irqrestore(&die_notifier_lock, flags);
76 return err; 76 return err;
77} 77}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-27 00:25:57 -0400