[PATCH] ppc64: add 970MP PVR

Add PVR value and tests for 970MP.  Also switch to a simpler (but slightly
longer) check at init time for simplicity.

Signed-off-by: Olof Johansson <olof@austin.ibm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

2 files changed, 37 insertions, 16 deletions

diff --git a/arch/ppc64/kernel/cpu_setup_power4.S b/arch/ppc64/kernel/cpu_setup_power4.S
index 42fc08cf87a0..0482c063c26e 100644
--- a/arch/ppc64/kernel/cpu_setup_power4.S
+++ b/arch/ppc64/kernel/cpu_setup_power4.S
@@ -31,10 +31,13 @@ _GLOBAL(__970_cpu_preinit)
          */
         mfspr   r0,SPRN_PVR
         srwi    r0,r0,16
-        cmpwi   cr0,r0,0x39
-        cmpwi   cr1,r0,0x3c
-        cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
+        cmpwi   r0,0x39
+        beq     1f
+        cmpwi   r0,0x3c
+        beq     1f
+        cmpwi   r0,0x44
         bnelr
+1:
 
         /* Make sure HID4:rm_ci is off before MMU is turned off, that large
          * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
@@ -133,12 +136,14 @@ _GLOBAL(__save_cpu_setup)
         /* We only deal with 970 for now */
         mfspr   r0,SPRN_PVR
         srwi    r0,r0,16
-        cmpwi   cr0,r0,0x39
-        cmpwi   cr1,r0,0x3c
-        cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
-        bne     1f
-
-        /* Save HID0,1,4 and 5 */
+        cmpwi   r0,0x39
+        beq     1f
+        cmpwi   r0,0x3c
+        beq     1f
+        cmpwi   r0,0x44
+        bne     2f
+
+1:      /* Save HID0,1,4 and 5 */
         mfspr   r3,SPRN_HID0
         std     r3,CS_HID0(r5)
         mfspr   r3,SPRN_HID1
@@ -148,7 +153,7 @@ _GLOBAL(__save_cpu_setup)
         mfspr   r3,SPRN_HID5
         std     r3,CS_HID5(r5)
         
-1:
+2:
         mtcr    r7
         blr
 
@@ -165,12 +170,14 @@ _GLOBAL(__restore_cpu_setup)
         /* We only deal with 970 for now */
         mfspr   r0,SPRN_PVR
         srwi    r0,r0,16
-        cmpwi   cr0,r0,0x39
-        cmpwi   cr1,r0,0x3c
-        cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
-        bne     1f
+        cmpwi   r0,0x39
+        beq     1f
+        cmpwi   r0,0x3c
+        beq     1f
+        cmpwi   r0,0x44
+        bnelr
 
-        /* Before accessing memory, we make sure rm_ci is clear */
+1:      /* Before accessing memory, we make sure rm_ci is clear */
         li      r0,0
         mfspr   r3,SPRN_HID4
         rldimi  r3,r0,40,23     /* clear bit 23 (rm_ci) */
@@ -223,6 +230,5 @@ _GLOBAL(__restore_cpu_setup)
         mtspr   SPRN_HID5,r3
         sync
         isync
-1:
         blr
 
diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c
index 8d4c46f6f0b6..77cec42f9525 100644
--- a/arch/ppc64/kernel/cputable.c
+++ b/arch/ppc64/kernel/cputable.c
@@ -183,6 +183,21 @@ struct cpu_spec	cpu_specs[] = {
                 .cpu_setup              = __setup_cpu_ppc970,
                 .firmware_features      = COMMON_PPC64_FW,
         },
+        {       /* PPC970MP */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x00440000,
+                .cpu_name               = "PPC970MP",
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                        CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
+                        CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                .cpu_user_features      = COMMON_USER_PPC64 |
+                        PPC_FEATURE_HAS_ALTIVEC_COMP,
+                .icache_bsize           = 128,
+                .dcache_bsize           = 128,
+                .cpu_setup              = __setup_cpu_ppc970,
+                .firmware_features      = COMMON_PPC64_FW,
+        },
         {       /* Power5 */
                 .pvr_mask               = 0xffff0000,
                 .pvr_value              = 0x003a0000,