aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ppc64/xmon
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/ppc64/xmon
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/ppc64/xmon')
-rw-r--r--arch/ppc64/xmon/Makefile5
-rw-r--r--arch/ppc64/xmon/ansidecl.h141
-rw-r--r--arch/ppc64/xmon/nonstdio.h22
-rw-r--r--arch/ppc64/xmon/ppc-dis.c184
-rw-r--r--arch/ppc64/xmon/ppc-opc.c4620
-rw-r--r--arch/ppc64/xmon/ppc.h307
-rw-r--r--arch/ppc64/xmon/privinst.h65
-rw-r--r--arch/ppc64/xmon/setjmp.S73
-rw-r--r--arch/ppc64/xmon/start.c185
-rw-r--r--arch/ppc64/xmon/subr_prf.c55
-rw-r--r--arch/ppc64/xmon/xmon.c2506
11 files changed, 8163 insertions, 0 deletions
diff --git a/arch/ppc64/xmon/Makefile b/arch/ppc64/xmon/Makefile
new file mode 100644
index 000000000000..fb21a7088d3e
--- /dev/null
+++ b/arch/ppc64/xmon/Makefile
@@ -0,0 +1,5 @@
1# Makefile for xmon
2
3EXTRA_CFLAGS += -mno-minimal-toc
4
5obj-y := start.o xmon.o ppc-dis.o ppc-opc.o subr_prf.o setjmp.o
diff --git a/arch/ppc64/xmon/ansidecl.h b/arch/ppc64/xmon/ansidecl.h
new file mode 100644
index 000000000000..c9b9f0929e9e
--- /dev/null
+++ b/arch/ppc64/xmon/ansidecl.h
@@ -0,0 +1,141 @@
1/* ANSI and traditional C compatibility macros
2 Copyright 1991, 1992 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4
5This program is free software; you can redistribute it and/or modify
6it under the terms of the GNU General Public License as published by
7the Free Software Foundation; either version 2 of the License, or
8(at your option) any later version.
9
10This program is distributed in the hope that it will be useful,
11but WITHOUT ANY WARRANTY; without even the implied warranty of
12MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13GNU General Public License for more details.
14
15You should have received a copy of the GNU General Public License
16along with this program; if not, write to the Free Software
17Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
18
19/* ANSI and traditional C compatibility macros
20
21 ANSI C is assumed if __STDC__ is #defined.
22
23 Macro ANSI C definition Traditional C definition
24 ----- ---- - ---------- ----------- - ----------
25 PTR `void *' `char *'
26 LONG_DOUBLE `long double' `double'
27 VOLATILE `volatile' `'
28 SIGNED `signed' `'
29 PTRCONST `void *const' `char *'
30 ANSI_PROTOTYPES 1 not defined
31
32 CONST is also defined, but is obsolete. Just use const.
33
34 DEFUN (name, arglist, args)
35
36 Defines function NAME.
37
38 ARGLIST lists the arguments, separated by commas and enclosed in
39 parentheses. ARGLIST becomes the argument list in traditional C.
40
41 ARGS list the arguments with their types. It becomes a prototype in
42 ANSI C, and the type declarations in traditional C. Arguments should
43 be separated with `AND'. For functions with a variable number of
44 arguments, the last thing listed should be `DOTS'.
45
46 DEFUN_VOID (name)
47
48 Defines a function NAME, which takes no arguments.
49
50 obsolete -- EXFUN (name, (prototype)) -- obsolete.
51
52 Replaced by PARAMS. Do not use; will disappear someday soon.
53 Was used in external function declarations.
54 In ANSI C it is `NAME PROTOTYPE' (so PROTOTYPE should be enclosed in
55 parentheses). In traditional C it is `NAME()'.
56 For a function that takes no arguments, PROTOTYPE should be `(void)'.
57
58 PARAMS ((args))
59
60 We could use the EXFUN macro to handle prototype declarations, but
61 the name is misleading and the result is ugly. So we just define a
62 simple macro to handle the parameter lists, as in:
63
64 static int foo PARAMS ((int, char));
65
66 This produces: `static int foo();' or `static int foo (int, char);'
67
68 EXFUN would have done it like this:
69
70 static int EXFUN (foo, (int, char));
71
72 but the function is not external...and it's hard to visually parse
73 the function name out of the mess. EXFUN should be considered
74 obsolete; new code should be written to use PARAMS.
75
76 For example:
77 extern int printf PARAMS ((CONST char *format DOTS));
78 int DEFUN(fprintf, (stream, format),
79 FILE *stream AND CONST char *format DOTS) { ... }
80 void DEFUN_VOID(abort) { ... }
81*/
82
83#ifndef _ANSIDECL_H
84
85#define _ANSIDECL_H 1
86
87
88/* Every source file includes this file,
89 so they will all get the switch for lint. */
90/* LINTLIBRARY */
91
92
93#if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(WIN32)
94/* All known AIX compilers implement these things (but don't always
95 define __STDC__). The RISC/OS MIPS compiler defines these things
96 in SVR4 mode, but does not define __STDC__. */
97
98#define PTR void *
99#define PTRCONST void *CONST
100#define LONG_DOUBLE long double
101
102#define AND ,
103#define NOARGS void
104#define CONST const
105#define VOLATILE volatile
106#define SIGNED signed
107#define DOTS , ...
108
109#define EXFUN(name, proto) name proto
110#define DEFUN(name, arglist, args) name(args)
111#define DEFUN_VOID(name) name(void)
112
113#define PROTO(type, name, arglist) type name arglist
114#define PARAMS(paramlist) paramlist
115#define ANSI_PROTOTYPES 1
116
117#else /* Not ANSI C. */
118
119#define PTR char *
120#define PTRCONST PTR
121#define LONG_DOUBLE double
122
123#define AND ;
124#define NOARGS
125#define CONST
126#ifndef const /* some systems define it in header files for non-ansi mode */
127#define const
128#endif
129#define VOLATILE
130#define SIGNED
131#define DOTS
132
133#define EXFUN(name, proto) name()
134#define DEFUN(name, arglist, args) name arglist args;
135#define DEFUN_VOID(name) name()
136#define PROTO(type, name, arglist) type name ()
137#define PARAMS(paramlist) ()
138
139#endif /* ANSI C. */
140
141#endif /* ansidecl.h */
diff --git a/arch/ppc64/xmon/nonstdio.h b/arch/ppc64/xmon/nonstdio.h
new file mode 100644
index 000000000000..84211a21c6f4
--- /dev/null
+++ b/arch/ppc64/xmon/nonstdio.h
@@ -0,0 +1,22 @@
1typedef int FILE;
2extern FILE *xmon_stdin, *xmon_stdout;
3#define EOF (-1)
4#define stdin xmon_stdin
5#define stdout xmon_stdout
6#define printf xmon_printf
7#define fprintf xmon_fprintf
8#define fputs xmon_fputs
9#define fgets xmon_fgets
10#define putchar xmon_putchar
11#define getchar xmon_getchar
12#define putc xmon_putc
13#define getc xmon_getc
14#define fopen(n, m) NULL
15#define fflush(f) do {} while (0)
16#define fclose(f) do {} while (0)
17extern char *fgets(char *, int, void *);
18extern void xmon_printf(const char *, ...);
19extern void xmon_fprintf(void *, const char *, ...);
20extern void xmon_sprintf(char *, const char *, ...);
21
22#define perror(s) printf("%s: no files!\n", (s))
diff --git a/arch/ppc64/xmon/ppc-dis.c b/arch/ppc64/xmon/ppc-dis.c
new file mode 100644
index 000000000000..ac0a9d2427e0
--- /dev/null
+++ b/arch/ppc64/xmon/ppc-dis.c
@@ -0,0 +1,184 @@
1/* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
102, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#include "nonstdio.h"
22#include "ansidecl.h"
23#include "ppc.h"
24
25extern void print_address (unsigned long memaddr);
26
27/* Print a PowerPC or POWER instruction. */
28
29int
30print_insn_powerpc (unsigned long insn, unsigned long memaddr, int dialect)
31{
32 const struct powerpc_opcode *opcode;
33 const struct powerpc_opcode *opcode_end;
34 unsigned long op;
35
36 if (dialect == 0)
37 dialect = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON
38 | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_ALTIVEC;
39
40 /* Get the major opcode of the instruction. */
41 op = PPC_OP (insn);
42
43 /* Find the first match in the opcode table. We could speed this up
44 a bit by doing a binary search on the major opcode. */
45 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
46 again:
47 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
48 {
49 unsigned long table_op;
50 const unsigned char *opindex;
51 const struct powerpc_operand *operand;
52 int invalid;
53 int need_comma;
54 int need_paren;
55
56 table_op = PPC_OP (opcode->opcode);
57 if (op < table_op)
58 break;
59 if (op > table_op)
60 continue;
61
62 if ((insn & opcode->mask) != opcode->opcode
63 || (opcode->flags & dialect) == 0)
64 continue;
65
66 /* Make two passes over the operands. First see if any of them
67 have extraction functions, and, if they do, make sure the
68 instruction is valid. */
69 invalid = 0;
70 for (opindex = opcode->operands; *opindex != 0; opindex++)
71 {
72 operand = powerpc_operands + *opindex;
73 if (operand->extract)
74 (*operand->extract) (insn, dialect, &invalid);
75 }
76 if (invalid)
77 continue;
78
79 /* The instruction is valid. */
80 printf("%s", opcode->name);
81 if (opcode->operands[0] != 0)
82 printf("\t");
83
84 /* Now extract and print the operands. */
85 need_comma = 0;
86 need_paren = 0;
87 for (opindex = opcode->operands; *opindex != 0; opindex++)
88 {
89 long value;
90
91 operand = powerpc_operands + *opindex;
92
93 /* Operands that are marked FAKE are simply ignored. We
94 already made sure that the extract function considered
95 the instruction to be valid. */
96 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
97 continue;
98
99 /* Extract the value from the instruction. */
100 if (operand->extract)
101 value = (*operand->extract) (insn, dialect, &invalid);
102 else
103 {
104 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
105 if ((operand->flags & PPC_OPERAND_SIGNED) != 0
106 && (value & (1 << (operand->bits - 1))) != 0)
107 value -= 1 << operand->bits;
108 }
109
110 /* If the operand is optional, and the value is zero, don't
111 print anything. */
112 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
113 && (operand->flags & PPC_OPERAND_NEXT) == 0
114 && value == 0)
115 continue;
116
117 if (need_comma)
118 {
119 printf(",");
120 need_comma = 0;
121 }
122
123 /* Print the operand as directed by the flags. */
124 if ((operand->flags & PPC_OPERAND_GPR) != 0)
125 printf("r%ld", value);
126 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
127 printf("f%ld", value);
128 else if ((operand->flags & PPC_OPERAND_VR) != 0)
129 printf("v%ld", value);
130 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
131 print_address (memaddr + value);
132 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
133 print_address (value & 0xffffffff);
134 else if ((operand->flags & PPC_OPERAND_CR) == 0
135 || (dialect & PPC_OPCODE_PPC) == 0)
136 printf("%ld", value);
137 else
138 {
139 if (operand->bits == 3)
140 printf("cr%d", value);
141 else
142 {
143 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
144 int cr;
145 int cc;
146
147 cr = value >> 2;
148 if (cr != 0)
149 printf("4*cr%d+", cr);
150 cc = value & 3;
151 printf("%s", cbnames[cc]);
152 }
153 }
154
155 if (need_paren)
156 {
157 printf(")");
158 need_paren = 0;
159 }
160
161 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
162 need_comma = 1;
163 else
164 {
165 printf("(");
166 need_paren = 1;
167 }
168 }
169
170 /* We have found and printed an instruction; return. */
171 return 4;
172 }
173
174 if ((dialect & PPC_OPCODE_ANY) != 0)
175 {
176 dialect = ~PPC_OPCODE_ANY;
177 goto again;
178 }
179
180 /* We could not find a match. */
181 printf(".long 0x%lx", insn);
182
183 return 4;
184}
diff --git a/arch/ppc64/xmon/ppc-opc.c b/arch/ppc64/xmon/ppc-opc.c
new file mode 100644
index 000000000000..1e4e7e319970
--- /dev/null
+++ b/arch/ppc64/xmon/ppc-opc.c
@@ -0,0 +1,4620 @@
1/* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23#include "nonstdio.h"
24#include "ppc.h"
25
26#define ATTRIBUTE_UNUSED
27#define _(x) x
28
29/* This file holds the PowerPC opcode table. The opcode table
30 includes almost all of the extended instruction mnemonics. This
31 permits the disassembler to use them, and simplifies the assembler
32 logic, at the cost of increasing the table size. The table is
33 strictly constant data, so the compiler should be able to put it in
34 the .text section.
35
36 This file also holds the operand table. All knowledge about
37 inserting operands into instructions and vice-versa is kept in this
38 file. */
39
40/* Local insertion and extraction functions. */
41
42static unsigned long insert_bat (unsigned long, long, int, const char **);
43static long extract_bat (unsigned long, int, int *);
44static unsigned long insert_bba (unsigned long, long, int, const char **);
45static long extract_bba (unsigned long, int, int *);
46static unsigned long insert_bd (unsigned long, long, int, const char **);
47static long extract_bd (unsigned long, int, int *);
48static unsigned long insert_bdm (unsigned long, long, int, const char **);
49static long extract_bdm (unsigned long, int, int *);
50static unsigned long insert_bdp (unsigned long, long, int, const char **);
51static long extract_bdp (unsigned long, int, int *);
52static unsigned long insert_bo (unsigned long, long, int, const char **);
53static long extract_bo (unsigned long, int, int *);
54static unsigned long insert_boe (unsigned long, long, int, const char **);
55static long extract_boe (unsigned long, int, int *);
56static unsigned long insert_dq (unsigned long, long, int, const char **);
57static long extract_dq (unsigned long, int, int *);
58static unsigned long insert_ds (unsigned long, long, int, const char **);
59static long extract_ds (unsigned long, int, int *);
60static unsigned long insert_de (unsigned long, long, int, const char **);
61static long extract_de (unsigned long, int, int *);
62static unsigned long insert_des (unsigned long, long, int, const char **);
63static long extract_des (unsigned long, int, int *);
64static unsigned long insert_fxm (unsigned long, long, int, const char **);
65static long extract_fxm (unsigned long, int, int *);
66static unsigned long insert_li (unsigned long, long, int, const char **);
67static long extract_li (unsigned long, int, int *);
68static unsigned long insert_mbe (unsigned long, long, int, const char **);
69static long extract_mbe (unsigned long, int, int *);
70static unsigned long insert_mb6 (unsigned long, long, int, const char **);
71static long extract_mb6 (unsigned long, int, int *);
72static unsigned long insert_nb (unsigned long, long, int, const char **);
73static long extract_nb (unsigned long, int, int *);
74static unsigned long insert_nsi (unsigned long, long, int, const char **);
75static long extract_nsi (unsigned long, int, int *);
76static unsigned long insert_ral (unsigned long, long, int, const char **);
77static unsigned long insert_ram (unsigned long, long, int, const char **);
78static unsigned long insert_raq (unsigned long, long, int, const char **);
79static unsigned long insert_ras (unsigned long, long, int, const char **);
80static unsigned long insert_rbs (unsigned long, long, int, const char **);
81static long extract_rbs (unsigned long, int, int *);
82static unsigned long insert_rsq (unsigned long, long, int, const char **);
83static unsigned long insert_rtq (unsigned long, long, int, const char **);
84static unsigned long insert_sh6 (unsigned long, long, int, const char **);
85static long extract_sh6 (unsigned long, int, int *);
86static unsigned long insert_spr (unsigned long, long, int, const char **);
87static long extract_spr (unsigned long, int, int *);
88static unsigned long insert_tbr (unsigned long, long, int, const char **);
89static long extract_tbr (unsigned long, int, int *);
90static unsigned long insert_ev2 (unsigned long, long, int, const char **);
91static long extract_ev2 (unsigned long, int, int *);
92static unsigned long insert_ev4 (unsigned long, long, int, const char **);
93static long extract_ev4 (unsigned long, int, int *);
94static unsigned long insert_ev8 (unsigned long, long, int, const char **);
95static long extract_ev8 (unsigned long, int, int *);
96
97/* The operands table.
98
99 The fields are bits, shift, insert, extract, flags.
100
101 We used to put parens around the various additions, like the one
102 for BA just below. However, that caused trouble with feeble
103 compilers with a limit on depth of a parenthesized expression, like
104 (reportedly) the compiler in Microsoft Developer Studio 5. So we
105 omit the parens, since the macros are never used in a context where
106 the addition will be ambiguous. */
107
108const struct powerpc_operand powerpc_operands[] =
109{
110 /* The zero index is used to indicate the end of the list of
111 operands. */
112#define UNUSED 0
113 { 0, 0, 0, 0, 0 },
114
115 /* The BA field in an XL form instruction. */
116#define BA UNUSED + 1
117#define BA_MASK (0x1f << 16)
118 { 5, 16, 0, 0, PPC_OPERAND_CR },
119
120 /* The BA field in an XL form instruction when it must be the same
121 as the BT field in the same instruction. */
122#define BAT BA + 1
123 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
124
125 /* The BB field in an XL form instruction. */
126#define BB BAT + 1
127#define BB_MASK (0x1f << 11)
128 { 5, 11, 0, 0, PPC_OPERAND_CR },
129
130 /* The BB field in an XL form instruction when it must be the same
131 as the BA field in the same instruction. */
132#define BBA BB + 1
133 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
134
135 /* The BD field in a B form instruction. The lower two bits are
136 forced to zero. */
137#define BD BBA + 1
138 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
139
140 /* The BD field in a B form instruction when absolute addressing is
141 used. */
142#define BDA BD + 1
143 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
144
145 /* The BD field in a B form instruction when the - modifier is used.
146 This sets the y bit of the BO field appropriately. */
147#define BDM BDA + 1
148 { 16, 0, insert_bdm, extract_bdm,
149 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
150
151 /* The BD field in a B form instruction when the - modifier is used
152 and absolute address is used. */
153#define BDMA BDM + 1
154 { 16, 0, insert_bdm, extract_bdm,
155 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
156
157 /* The BD field in a B form instruction when the + modifier is used.
158 This sets the y bit of the BO field appropriately. */
159#define BDP BDMA + 1
160 { 16, 0, insert_bdp, extract_bdp,
161 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
162
163 /* The BD field in a B form instruction when the + modifier is used
164 and absolute addressing is used. */
165#define BDPA BDP + 1
166 { 16, 0, insert_bdp, extract_bdp,
167 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
168
169 /* The BF field in an X or XL form instruction. */
170#define BF BDPA + 1
171 { 3, 23, 0, 0, PPC_OPERAND_CR },
172
173 /* An optional BF field. This is used for comparison instructions,
174 in which an omitted BF field is taken as zero. */
175#define OBF BF + 1
176 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
177
178 /* The BFA field in an X or XL form instruction. */
179#define BFA OBF + 1
180 { 3, 18, 0, 0, PPC_OPERAND_CR },
181
182 /* The BI field in a B form or XL form instruction. */
183#define BI BFA + 1
184#define BI_MASK (0x1f << 16)
185 { 5, 16, 0, 0, PPC_OPERAND_CR },
186
187 /* The BO field in a B form instruction. Certain values are
188 illegal. */
189#define BO BI + 1
190#define BO_MASK (0x1f << 21)
191 { 5, 21, insert_bo, extract_bo, 0 },
192
193 /* The BO field in a B form instruction when the + or - modifier is
194 used. This is like the BO field, but it must be even. */
195#define BOE BO + 1
196 { 5, 21, insert_boe, extract_boe, 0 },
197
198 /* The BT field in an X or XL form instruction. */
199#define BT BOE + 1
200 { 5, 21, 0, 0, PPC_OPERAND_CR },
201
202 /* The condition register number portion of the BI field in a B form
203 or XL form instruction. This is used for the extended
204 conditional branch mnemonics, which set the lower two bits of the
205 BI field. This field is optional. */
206#define CR BT + 1
207 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
208
209 /* The CRB field in an X form instruction. */
210#define CRB CR + 1
211 { 5, 6, 0, 0, 0 },
212
213 /* The CRFD field in an X form instruction. */
214#define CRFD CRB + 1
215 { 3, 23, 0, 0, PPC_OPERAND_CR },
216
217 /* The CRFS field in an X form instruction. */
218#define CRFS CRFD + 1
219 { 3, 0, 0, 0, PPC_OPERAND_CR },
220
221 /* The CT field in an X form instruction. */
222#define CT CRFS + 1
223 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
224
225 /* The D field in a D form instruction. This is a displacement off
226 a register, and implies that the next operand is a register in
227 parentheses. */
228#define D CT + 1
229 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
230
231 /* The DE field in a DE form instruction. This is like D, but is 12
232 bits only. */
233#define DE D + 1
234 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
235
236 /* The DES field in a DES form instruction. This is like DS, but is 14
237 bits only (12 stored.) */
238#define DES DE + 1
239 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
240
241 /* The DQ field in a DQ form instruction. This is like D, but the
242 lower four bits are forced to zero. */
243#define DQ DES + 1
244 { 16, 0, insert_dq, extract_dq,
245 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
246
247 /* The DS field in a DS form instruction. This is like D, but the
248 lower two bits are forced to zero. */
249#define DS DQ + 1
250 { 16, 0, insert_ds, extract_ds,
251 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252
253 /* The E field in a wrteei instruction. */
254#define E DS + 1
255 { 1, 15, 0, 0, 0 },
256
257 /* The FL1 field in a POWER SC form instruction. */
258#define FL1 E + 1
259 { 4, 12, 0, 0, 0 },
260
261 /* The FL2 field in a POWER SC form instruction. */
262#define FL2 FL1 + 1
263 { 3, 2, 0, 0, 0 },
264
265 /* The FLM field in an XFL form instruction. */
266#define FLM FL2 + 1
267 { 8, 17, 0, 0, 0 },
268
269 /* The FRA field in an X or A form instruction. */
270#define FRA FLM + 1
271#define FRA_MASK (0x1f << 16)
272 { 5, 16, 0, 0, PPC_OPERAND_FPR },
273
274 /* The FRB field in an X or A form instruction. */
275#define FRB FRA + 1
276#define FRB_MASK (0x1f << 11)
277 { 5, 11, 0, 0, PPC_OPERAND_FPR },
278
279 /* The FRC field in an A form instruction. */
280#define FRC FRB + 1
281#define FRC_MASK (0x1f << 6)
282 { 5, 6, 0, 0, PPC_OPERAND_FPR },
283
284 /* The FRS field in an X form instruction or the FRT field in a D, X
285 or A form instruction. */
286#define FRS FRC + 1
287#define FRT FRS
288 { 5, 21, 0, 0, PPC_OPERAND_FPR },
289
290 /* The FXM field in an XFX instruction. */
291#define FXM FRS + 1
292#define FXM_MASK (0xff << 12)
293 { 8, 12, insert_fxm, extract_fxm, 0 },
294
295 /* Power4 version for mfcr. */
296#define FXM4 FXM + 1
297 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
298
299 /* The L field in a D or X form instruction. */
300#define L FXM4 + 1
301 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
302
303 /* The LEV field in a POWER SC form instruction. */
304#define LEV L + 1
305 { 7, 5, 0, 0, 0 },
306
307 /* The LI field in an I form instruction. The lower two bits are
308 forced to zero. */
309#define LI LEV + 1
310 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
311
312 /* The LI field in an I form instruction when used as an absolute
313 address. */
314#define LIA LI + 1
315 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
316
317 /* The LS field in an X (sync) form instruction. */
318#define LS LIA + 1
319 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
320
321 /* The MB field in an M form instruction. */
322#define MB LS + 1
323#define MB_MASK (0x1f << 6)
324 { 5, 6, 0, 0, 0 },
325
326 /* The ME field in an M form instruction. */
327#define ME MB + 1
328#define ME_MASK (0x1f << 1)
329 { 5, 1, 0, 0, 0 },
330
331 /* The MB and ME fields in an M form instruction expressed a single
332 operand which is a bitmask indicating which bits to select. This
333 is a two operand form using PPC_OPERAND_NEXT. See the
334 description in opcode/ppc.h for what this means. */
335#define MBE ME + 1
336 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
337 { 32, 0, insert_mbe, extract_mbe, 0 },
338
339 /* The MB or ME field in an MD or MDS form instruction. The high
340 bit is wrapped to the low end. */
341#define MB6 MBE + 2
342#define ME6 MB6
343#define MB6_MASK (0x3f << 5)
344 { 6, 5, insert_mb6, extract_mb6, 0 },
345
346 /* The MO field in an mbar instruction. */
347#define MO MB6 + 1
348 { 5, 21, 0, 0, 0 },
349
350 /* The NB field in an X form instruction. The value 32 is stored as
351 0. */
352#define NB MO + 1
353 { 6, 11, insert_nb, extract_nb, 0 },
354
355 /* The NSI field in a D form instruction. This is the same as the
356 SI field, only negated. */
357#define NSI NB + 1
358 { 16, 0, insert_nsi, extract_nsi,
359 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
360
361 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
362#define RA NSI + 1
363#define RA_MASK (0x1f << 16)
364 { 5, 16, 0, 0, PPC_OPERAND_GPR },
365
366 /* The RA field in the DQ form lq instruction, which has special
367 value restrictions. */
368#define RAQ RA + 1
369 { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
370
371 /* The RA field in a D or X form instruction which is an updating
372 load, which means that the RA field may not be zero and may not
373 equal the RT field. */
374#define RAL RAQ + 1
375 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
376
377 /* The RA field in an lmw instruction, which has special value
378 restrictions. */
379#define RAM RAL + 1
380 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
381
382 /* The RA field in a D or X form instruction which is an updating
383 store or an updating floating point load, which means that the RA
384 field may not be zero. */
385#define RAS RAM + 1
386 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
387
388 /* The RB field in an X, XO, M, or MDS form instruction. */
389#define RB RAS + 1
390#define RB_MASK (0x1f << 11)
391 { 5, 11, 0, 0, PPC_OPERAND_GPR },
392
393 /* The RB field in an X form instruction when it must be the same as
394 the RS field in the instruction. This is used for extended
395 mnemonics like mr. */
396#define RBS RB + 1
397 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
398
399 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
400 instruction or the RT field in a D, DS, X, XFX or XO form
401 instruction. */
402#define RS RBS + 1
403#define RT RS
404#define RT_MASK (0x1f << 21)
405 { 5, 21, 0, 0, PPC_OPERAND_GPR },
406
407 /* The RS field of the DS form stq instruction, which has special
408 value restrictions. */
409#define RSQ RS + 1
410 { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
411
412 /* The RT field of the DQ form lq instruction, which has special
413 value restrictions. */
414#define RTQ RSQ + 1
415 { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
416
417 /* The SH field in an X or M form instruction. */
418#define SH RTQ + 1
419#define SH_MASK (0x1f << 11)
420 { 5, 11, 0, 0, 0 },
421
422 /* The SH field in an MD form instruction. This is split. */
423#define SH6 SH + 1
424#define SH6_MASK ((0x1f << 11) | (1 << 1))
425 { 6, 1, insert_sh6, extract_sh6, 0 },
426
427 /* The SI field in a D form instruction. */
428#define SI SH6 + 1
429 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
430
431 /* The SI field in a D form instruction when we accept a wide range
432 of positive values. */
433#define SISIGNOPT SI + 1
434 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
435
436 /* The SPR field in an XFX form instruction. This is flipped--the
437 lower 5 bits are stored in the upper 5 and vice- versa. */
438#define SPR SISIGNOPT + 1
439#define PMR SPR
440#define SPR_MASK (0x3ff << 11)
441 { 10, 11, insert_spr, extract_spr, 0 },
442
443 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
444#define SPRBAT SPR + 1
445#define SPRBAT_MASK (0x3 << 17)
446 { 2, 17, 0, 0, 0 },
447
448 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
449#define SPRG SPRBAT + 1
450#define SPRG_MASK (0x3 << 16)
451 { 2, 16, 0, 0, 0 },
452
453 /* The SR field in an X form instruction. */
454#define SR SPRG + 1
455 { 4, 16, 0, 0, 0 },
456
457 /* The STRM field in an X AltiVec form instruction. */
458#define STRM SR + 1
459#define STRM_MASK (0x3 << 21)
460 { 2, 21, 0, 0, 0 },
461
462 /* The SV field in a POWER SC form instruction. */
463#define SV STRM + 1
464 { 14, 2, 0, 0, 0 },
465
466 /* The TBR field in an XFX form instruction. This is like the SPR
467 field, but it is optional. */
468#define TBR SV + 1
469 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
470
471 /* The TO field in a D or X form instruction. */
472#define TO TBR + 1
473#define TO_MASK (0x1f << 21)
474 { 5, 21, 0, 0, 0 },
475
476 /* The U field in an X form instruction. */
477#define U TO + 1
478 { 4, 12, 0, 0, 0 },
479
480 /* The UI field in a D form instruction. */
481#define UI U + 1
482 { 16, 0, 0, 0, 0 },
483
484 /* The VA field in a VA, VX or VXR form instruction. */
485#define VA UI + 1
486#define VA_MASK (0x1f << 16)
487 { 5, 16, 0, 0, PPC_OPERAND_VR },
488
489 /* The VB field in a VA, VX or VXR form instruction. */
490#define VB VA + 1
491#define VB_MASK (0x1f << 11)
492 { 5, 11, 0, 0, PPC_OPERAND_VR },
493
494 /* The VC field in a VA form instruction. */
495#define VC VB + 1
496#define VC_MASK (0x1f << 6)
497 { 5, 6, 0, 0, PPC_OPERAND_VR },
498
499 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
500#define VD VC + 1
501#define VS VD
502#define VD_MASK (0x1f << 21)
503 { 5, 21, 0, 0, PPC_OPERAND_VR },
504
505 /* The SIMM field in a VX form instruction. */
506#define SIMM VD + 1
507 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
508
509 /* The UIMM field in a VX form instruction. */
510#define UIMM SIMM + 1
511 { 5, 16, 0, 0, 0 },
512
513 /* The SHB field in a VA form instruction. */
514#define SHB UIMM + 1
515 { 4, 6, 0, 0, 0 },
516
517 /* The other UIMM field in a EVX form instruction. */
518#define EVUIMM SHB + 1
519 { 5, 11, 0, 0, 0 },
520
521 /* The other UIMM field in a half word EVX form instruction. */
522#define EVUIMM_2 EVUIMM + 1
523 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
524
525 /* The other UIMM field in a word EVX form instruction. */
526#define EVUIMM_4 EVUIMM_2 + 1
527 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
528
529 /* The other UIMM field in a double EVX form instruction. */
530#define EVUIMM_8 EVUIMM_4 + 1
531 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
532
533 /* The WS field. */
534#define WS EVUIMM_8 + 1
535#define WS_MASK (0x7 << 11)
536 { 3, 11, 0, 0, 0 },
537
538 /* The L field in an mtmsrd instruction */
539#define MTMSRD_L WS + 1
540 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
541
542};
543
544/* The functions used to insert and extract complicated operands. */
545
546/* The BA field in an XL form instruction when it must be the same as
547 the BT field in the same instruction. This operand is marked FAKE.
548 The insertion function just copies the BT field into the BA field,
549 and the extraction function just checks that the fields are the
550 same. */
551
552/*ARGSUSED*/
553static unsigned long
554insert_bat (unsigned long insn,
555 long value ATTRIBUTE_UNUSED,
556 int dialect ATTRIBUTE_UNUSED,
557 const char **errmsg ATTRIBUTE_UNUSED)
558{
559 return insn | (((insn >> 21) & 0x1f) << 16);
560}
561
562static long
563extract_bat (unsigned long insn,
564 int dialect ATTRIBUTE_UNUSED,
565 int *invalid)
566{
567 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
568 *invalid = 1;
569 return 0;
570}
571
572/* The BB field in an XL form instruction when it must be the same as
573 the BA field in the same instruction. This operand is marked FAKE.
574 The insertion function just copies the BA field into the BB field,
575 and the extraction function just checks that the fields are the
576 same. */
577
578/*ARGSUSED*/
579static unsigned long
580insert_bba (unsigned long insn,
581 long value ATTRIBUTE_UNUSED,
582 int dialect ATTRIBUTE_UNUSED,
583 const char **errmsg ATTRIBUTE_UNUSED)
584{
585 return insn | (((insn >> 16) & 0x1f) << 11);
586}
587
588static long
589extract_bba (unsigned long insn,
590 int dialect ATTRIBUTE_UNUSED,
591 int *invalid)
592{
593 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
594 *invalid = 1;
595 return 0;
596}
597
598/* The BD field in a B form instruction. The lower two bits are
599 forced to zero. */
600
601/*ARGSUSED*/
602static unsigned long
603insert_bd (unsigned long insn,
604 long value,
605 int dialect ATTRIBUTE_UNUSED,
606 const char **errmsg ATTRIBUTE_UNUSED)
607{
608 return insn | (value & 0xfffc);
609}
610
611/*ARGSUSED*/
612static long
613extract_bd (unsigned long insn,
614 int dialect ATTRIBUTE_UNUSED,
615 int *invalid ATTRIBUTE_UNUSED)
616{
617 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
618}
619
620/* The BD field in a B form instruction when the - modifier is used.
621 This modifier means that the branch is not expected to be taken.
622 For chips built to versions of the architecture prior to version 2
623 (ie. not Power4 compatible), we set the y bit of the BO field to 1
624 if the offset is negative. When extracting, we require that the y
625 bit be 1 and that the offset be positive, since if the y bit is 0
626 we just want to print the normal form of the instruction.
627 Power4 compatible targets use two bits, "a", and "t", instead of
628 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
629 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
630 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
631 for branch on CTR. We only handle the taken/not-taken hint here. */
632
633/*ARGSUSED*/
634static unsigned long
635insert_bdm (unsigned long insn,
636 long value,
637 int dialect,
638 const char **errmsg ATTRIBUTE_UNUSED)
639{
640 if ((dialect & PPC_OPCODE_POWER4) == 0)
641 {
642 if ((value & 0x8000) != 0)
643 insn |= 1 << 21;
644 }
645 else
646 {
647 if ((insn & (0x14 << 21)) == (0x04 << 21))
648 insn |= 0x02 << 21;
649 else if ((insn & (0x14 << 21)) == (0x10 << 21))
650 insn |= 0x08 << 21;
651 }
652 return insn | (value & 0xfffc);
653}
654
655static long
656extract_bdm (unsigned long insn,
657 int dialect,
658 int *invalid)
659{
660 if ((dialect & PPC_OPCODE_POWER4) == 0)
661 {
662 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
663 *invalid = 1;
664 }
665 else
666 {
667 if ((insn & (0x17 << 21)) != (0x06 << 21)
668 && (insn & (0x1d << 21)) != (0x18 << 21))
669 *invalid = 1;
670 }
671
672 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
673}
674
675/* The BD field in a B form instruction when the + modifier is used.
676 This is like BDM, above, except that the branch is expected to be
677 taken. */
678
679/*ARGSUSED*/
680static unsigned long
681insert_bdp (unsigned long insn,
682 long value,
683 int dialect,
684 const char **errmsg ATTRIBUTE_UNUSED)
685{
686 if ((dialect & PPC_OPCODE_POWER4) == 0)
687 {
688 if ((value & 0x8000) == 0)
689 insn |= 1 << 21;
690 }
691 else
692 {
693 if ((insn & (0x14 << 21)) == (0x04 << 21))
694 insn |= 0x03 << 21;
695 else if ((insn & (0x14 << 21)) == (0x10 << 21))
696 insn |= 0x09 << 21;
697 }
698 return insn | (value & 0xfffc);
699}
700
701static long
702extract_bdp (unsigned long insn,
703 int dialect,
704 int *invalid)
705{
706 if ((dialect & PPC_OPCODE_POWER4) == 0)
707 {
708 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
709 *invalid = 1;
710 }
711 else
712 {
713 if ((insn & (0x17 << 21)) != (0x07 << 21)
714 && (insn & (0x1d << 21)) != (0x19 << 21))
715 *invalid = 1;
716 }
717
718 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
719}
720
721/* Check for legal values of a BO field. */
722
723static int
724valid_bo (long value, int dialect)
725{
726 if ((dialect & PPC_OPCODE_POWER4) == 0)
727 {
728 /* Certain encodings have bits that are required to be zero.
729 These are (z must be zero, y may be anything):
730 001zy
731 011zy
732 1z00y
733 1z01y
734 1z1zz
735 */
736 switch (value & 0x14)
737 {
738 default:
739 case 0:
740 return 1;
741 case 0x4:
742 return (value & 0x2) == 0;
743 case 0x10:
744 return (value & 0x8) == 0;
745 case 0x14:
746 return value == 0x14;
747 }
748 }
749 else
750 {
751 /* Certain encodings have bits that are required to be zero.
752 These are (z must be zero, a & t may be anything):
753 0000z
754 0001z
755 0100z
756 0101z
757 001at
758 011at
759 1a00t
760 1a01t
761 1z1zz
762 */
763 if ((value & 0x14) == 0)
764 return (value & 0x1) == 0;
765 else if ((value & 0x14) == 0x14)
766 return value == 0x14;
767 else
768 return 1;
769 }
770}
771
772/* The BO field in a B form instruction. Warn about attempts to set
773 the field to an illegal value. */
774
775static unsigned long
776insert_bo (unsigned long insn,
777 long value,
778 int dialect,
779 const char **errmsg)
780{
781 if (!valid_bo (value, dialect))
782 *errmsg = _("invalid conditional option");
783 return insn | ((value & 0x1f) << 21);
784}
785
786static long
787extract_bo (unsigned long insn,
788 int dialect,
789 int *invalid)
790{
791 long value;
792
793 value = (insn >> 21) & 0x1f;
794 if (!valid_bo (value, dialect))
795 *invalid = 1;
796 return value;
797}
798
799/* The BO field in a B form instruction when the + or - modifier is
800 used. This is like the BO field, but it must be even. When
801 extracting it, we force it to be even. */
802
803static unsigned long
804insert_boe (unsigned long insn,
805 long value,
806 int dialect,
807 const char **errmsg)
808{
809 if (!valid_bo (value, dialect))
810 *errmsg = _("invalid conditional option");
811 else if ((value & 1) != 0)
812 *errmsg = _("attempt to set y bit when using + or - modifier");
813
814 return insn | ((value & 0x1f) << 21);
815}
816
817static long
818extract_boe (unsigned long insn,
819 int dialect,
820 int *invalid)
821{
822 long value;
823
824 value = (insn >> 21) & 0x1f;
825 if (!valid_bo (value, dialect))
826 *invalid = 1;
827 return value & 0x1e;
828}
829
830/* The DQ field in a DQ form instruction. This is like D, but the
831 lower four bits are forced to zero. */
832
833/*ARGSUSED*/
834static unsigned long
835insert_dq (unsigned long insn,
836 long value,
837 int dialect ATTRIBUTE_UNUSED,
838 const char **errmsg)
839{
840 if ((value & 0xf) != 0)
841 *errmsg = _("offset not a multiple of 16");
842 return insn | (value & 0xfff0);
843}
844
845/*ARGSUSED*/
846static long
847extract_dq (unsigned long insn,
848 int dialect ATTRIBUTE_UNUSED,
849 int *invalid ATTRIBUTE_UNUSED)
850{
851 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
852}
853
854static unsigned long
855insert_ev2 (unsigned long insn,
856 long value,
857 int dialect ATTRIBUTE_UNUSED,
858 const char **errmsg)
859{
860 if ((value & 1) != 0)
861 *errmsg = _("offset not a multiple of 2");
862 if ((value > 62) != 0)
863 *errmsg = _("offset greater than 62");
864 return insn | ((value & 0x3e) << 10);
865}
866
867static long
868extract_ev2 (unsigned long insn,
869 int dialect ATTRIBUTE_UNUSED,
870 int *invalid ATTRIBUTE_UNUSED)
871{
872 return (insn >> 10) & 0x3e;
873}
874
875static unsigned long
876insert_ev4 (unsigned long insn,
877 long value,
878 int dialect ATTRIBUTE_UNUSED,
879 const char **errmsg)
880{
881 if ((value & 3) != 0)
882 *errmsg = _("offset not a multiple of 4");
883 if ((value > 124) != 0)
884 *errmsg = _("offset greater than 124");
885 return insn | ((value & 0x7c) << 9);
886}
887
888static long
889extract_ev4 (unsigned long insn,
890 int dialect ATTRIBUTE_UNUSED,
891 int *invalid ATTRIBUTE_UNUSED)
892{
893 return (insn >> 9) & 0x7c;
894}
895
896static unsigned long
897insert_ev8 (unsigned long insn,
898 long value,
899 int dialect ATTRIBUTE_UNUSED,
900 const char **errmsg)
901{
902 if ((value & 7) != 0)
903 *errmsg = _("offset not a multiple of 8");
904 if ((value > 248) != 0)
905 *errmsg = _("offset greater than 248");
906 return insn | ((value & 0xf8) << 8);
907}
908
909static long
910extract_ev8 (unsigned long insn,
911 int dialect ATTRIBUTE_UNUSED,
912 int *invalid ATTRIBUTE_UNUSED)
913{
914 return (insn >> 8) & 0xf8;
915}
916
917/* The DS field in a DS form instruction. This is like D, but the
918 lower two bits are forced to zero. */
919
920/*ARGSUSED*/
921static unsigned long
922insert_ds (unsigned long insn,
923 long value,
924 int dialect ATTRIBUTE_UNUSED,
925 const char **errmsg)
926{
927 if ((value & 3) != 0)
928 *errmsg = _("offset not a multiple of 4");
929 return insn | (value & 0xfffc);
930}
931
932/*ARGSUSED*/
933static long
934extract_ds (unsigned long insn,
935 int dialect ATTRIBUTE_UNUSED,
936 int *invalid ATTRIBUTE_UNUSED)
937{
938 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
939}
940
941/* The DE field in a DE form instruction. */
942
943/*ARGSUSED*/
944static unsigned long
945insert_de (unsigned long insn,
946 long value,
947 int dialect ATTRIBUTE_UNUSED,
948 const char **errmsg)
949{
950 if (value > 2047 || value < -2048)
951 *errmsg = _("offset not between -2048 and 2047");
952 return insn | ((value << 4) & 0xfff0);
953}
954
955/*ARGSUSED*/
956static long
957extract_de (unsigned long insn,
958 int dialect ATTRIBUTE_UNUSED,
959 int *invalid ATTRIBUTE_UNUSED)
960{
961 return (insn & 0xfff0) >> 4;
962}
963
964/* The DES field in a DES form instruction. */
965
966/*ARGSUSED*/
967static unsigned long
968insert_des (unsigned long insn,
969 long value,
970 int dialect ATTRIBUTE_UNUSED,
971 const char **errmsg)
972{
973 if (value > 8191 || value < -8192)
974 *errmsg = _("offset not between -8192 and 8191");
975 else if ((value & 3) != 0)
976 *errmsg = _("offset not a multiple of 4");
977 return insn | ((value << 2) & 0xfff0);
978}
979
980/*ARGSUSED*/
981static long
982extract_des (unsigned long insn,
983 int dialect ATTRIBUTE_UNUSED,
984 int *invalid ATTRIBUTE_UNUSED)
985{
986 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
987}
988
989/* FXM mask in mfcr and mtcrf instructions. */
990
991static unsigned long
992insert_fxm (unsigned long insn,
993 long value,
994 int dialect,
995 const char **errmsg)
996{
997 /* If the optional field on mfcr is missing that means we want to use
998 the old form of the instruction that moves the whole cr. In that
999 case we'll have VALUE zero. There doesn't seem to be a way to
1000 distinguish this from the case where someone writes mfcr %r3,0. */
1001 if (value == 0)
1002 ;
1003
1004 /* If only one bit of the FXM field is set, we can use the new form
1005 of the instruction, which is faster. Unlike the Power4 branch hint
1006 encoding, this is not backward compatible. */
1007 else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
1008 insn |= 1 << 20;
1009
1010 /* Any other value on mfcr is an error. */
1011 else if ((insn & (0x3ff << 1)) == 19 << 1)
1012 {
1013 *errmsg = _("ignoring invalid mfcr mask");
1014 value = 0;
1015 }
1016
1017 return insn | ((value & 0xff) << 12);
1018}
1019
1020static long
1021extract_fxm (unsigned long insn,
1022 int dialect,
1023 int *invalid)
1024{
1025 long mask = (insn >> 12) & 0xff;
1026
1027 /* Is this a Power4 insn? */
1028 if ((insn & (1 << 20)) != 0)
1029 {
1030 if ((dialect & PPC_OPCODE_POWER4) == 0)
1031 *invalid = 1;
1032 else
1033 {
1034 /* Exactly one bit of MASK should be set. */
1035 if (mask == 0 || (mask & -mask) != mask)
1036 *invalid = 1;
1037 }
1038 }
1039
1040 /* Check that non-power4 form of mfcr has a zero MASK. */
1041 else if ((insn & (0x3ff << 1)) == 19 << 1)
1042 {
1043 if (mask != 0)
1044 *invalid = 1;
1045 }
1046
1047 return mask;
1048}
1049
1050/* The LI field in an I form instruction. The lower two bits are
1051 forced to zero. */
1052
1053/*ARGSUSED*/
1054static unsigned long
1055insert_li (unsigned long insn,
1056 long value,
1057 int dialect ATTRIBUTE_UNUSED,
1058 const char **errmsg)
1059{
1060 if ((value & 3) != 0)
1061 *errmsg = _("ignoring least significant bits in branch offset");
1062 return insn | (value & 0x3fffffc);
1063}
1064
1065/*ARGSUSED*/
1066static long
1067extract_li (unsigned long insn,
1068 int dialect ATTRIBUTE_UNUSED,
1069 int *invalid ATTRIBUTE_UNUSED)
1070{
1071 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1072}
1073
1074/* The MB and ME fields in an M form instruction expressed as a single
1075 operand which is itself a bitmask. The extraction function always
1076 marks it as invalid, since we never want to recognize an
1077 instruction which uses a field of this type. */
1078
1079static unsigned long
1080insert_mbe (unsigned long insn,
1081 long value,
1082 int dialect ATTRIBUTE_UNUSED,
1083 const char **errmsg)
1084{
1085 unsigned long uval, mask;
1086 int mb, me, mx, count, last;
1087
1088 uval = value;
1089
1090 if (uval == 0)
1091 {
1092 *errmsg = _("illegal bitmask");
1093 return insn;
1094 }
1095
1096 mb = 0;
1097 me = 32;
1098 if ((uval & 1) != 0)
1099 last = 1;
1100 else
1101 last = 0;
1102 count = 0;
1103
1104 /* mb: location of last 0->1 transition */
1105 /* me: location of last 1->0 transition */
1106 /* count: # transitions */
1107
1108 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1109 {
1110 if ((uval & mask) && !last)
1111 {
1112 ++count;
1113 mb = mx;
1114 last = 1;
1115 }
1116 else if (!(uval & mask) && last)
1117 {
1118 ++count;
1119 me = mx;
1120 last = 0;
1121 }
1122 }
1123 if (me == 0)
1124 me = 32;
1125
1126 if (count != 2 && (count != 0 || ! last))
1127 *errmsg = _("illegal bitmask");
1128
1129 return insn | (mb << 6) | ((me - 1) << 1);
1130}
1131
1132static long
1133extract_mbe (unsigned long insn,
1134 int dialect ATTRIBUTE_UNUSED,
1135 int *invalid)
1136{
1137 long ret;
1138 int mb, me;
1139 int i;
1140
1141 *invalid = 1;
1142
1143 mb = (insn >> 6) & 0x1f;
1144 me = (insn >> 1) & 0x1f;
1145 if (mb < me + 1)
1146 {
1147 ret = 0;
1148 for (i = mb; i <= me; i++)
1149 ret |= 1L << (31 - i);
1150 }
1151 else if (mb == me + 1)
1152 ret = ~0;
1153 else /* (mb > me + 1) */
1154 {
1155 ret = ~0;
1156 for (i = me + 1; i < mb; i++)
1157 ret &= ~(1L << (31 - i));
1158 }
1159 return ret;
1160}
1161
1162/* The MB or ME field in an MD or MDS form instruction. The high bit
1163 is wrapped to the low end. */
1164
1165/*ARGSUSED*/
1166static unsigned long
1167insert_mb6 (unsigned long insn,
1168 long value,
1169 int dialect ATTRIBUTE_UNUSED,
1170 const char **errmsg ATTRIBUTE_UNUSED)
1171{
1172 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1173}
1174
1175/*ARGSUSED*/
1176static long
1177extract_mb6 (unsigned long insn,
1178 int dialect ATTRIBUTE_UNUSED,
1179 int *invalid ATTRIBUTE_UNUSED)
1180{
1181 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1182}
1183
1184/* The NB field in an X form instruction. The value 32 is stored as
1185 0. */
1186
1187static unsigned long
1188insert_nb (unsigned long insn,
1189 long value,
1190 int dialect ATTRIBUTE_UNUSED,
1191 const char **errmsg)
1192{
1193 if (value < 0 || value > 32)
1194 *errmsg = _("value out of range");
1195 if (value == 32)
1196 value = 0;
1197 return insn | ((value & 0x1f) << 11);
1198}
1199
1200/*ARGSUSED*/
1201static long
1202extract_nb (unsigned long insn,
1203 int dialect ATTRIBUTE_UNUSED,
1204 int *invalid ATTRIBUTE_UNUSED)
1205{
1206 long ret;
1207
1208 ret = (insn >> 11) & 0x1f;
1209 if (ret == 0)
1210 ret = 32;
1211 return ret;
1212}
1213
1214/* The NSI field in a D form instruction. This is the same as the SI
1215 field, only negated. The extraction function always marks it as
1216 invalid, since we never want to recognize an instruction which uses
1217 a field of this type. */
1218
1219/*ARGSUSED*/
1220static unsigned long
1221insert_nsi (unsigned long insn,
1222 long value,
1223 int dialect ATTRIBUTE_UNUSED,
1224 const char **errmsg ATTRIBUTE_UNUSED)
1225{
1226 return insn | (-value & 0xffff);
1227}
1228
1229static long
1230extract_nsi (unsigned long insn,
1231 int dialect ATTRIBUTE_UNUSED,
1232 int *invalid)
1233{
1234 *invalid = 1;
1235 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1236}
1237
1238/* The RA field in a D or X form instruction which is an updating
1239 load, which means that the RA field may not be zero and may not
1240 equal the RT field. */
1241
1242static unsigned long
1243insert_ral (unsigned long insn,
1244 long value,
1245 int dialect ATTRIBUTE_UNUSED,
1246 const char **errmsg)
1247{
1248 if (value == 0
1249 || (unsigned long) value == ((insn >> 21) & 0x1f))
1250 *errmsg = "invalid register operand when updating";
1251 return insn | ((value & 0x1f) << 16);
1252}
1253
1254/* The RA field in an lmw instruction, which has special value
1255 restrictions. */
1256
1257static unsigned long
1258insert_ram (unsigned long insn,
1259 long value,
1260 int dialect ATTRIBUTE_UNUSED,
1261 const char **errmsg)
1262{
1263 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1264 *errmsg = _("index register in load range");
1265 return insn | ((value & 0x1f) << 16);
1266}
1267
1268/* The RA field in the DQ form lq instruction, which has special
1269 value restrictions. */
1270
1271/*ARGSUSED*/
1272static unsigned long
1273insert_raq (unsigned long insn,
1274 long value,
1275 int dialect ATTRIBUTE_UNUSED,
1276 const char **errmsg)
1277{
1278 long rtvalue = (insn & RT_MASK) >> 21;
1279
1280 if (value == rtvalue)
1281 *errmsg = _("source and target register operands must be different");
1282 return insn | ((value & 0x1f) << 16);
1283}
1284
1285/* The RA field in a D or X form instruction which is an updating
1286 store or an updating floating point load, which means that the RA
1287 field may not be zero. */
1288
1289static unsigned long
1290insert_ras (unsigned long insn,
1291 long value,
1292 int dialect ATTRIBUTE_UNUSED,
1293 const char **errmsg)
1294{
1295 if (value == 0)
1296 *errmsg = _("invalid register operand when updating");
1297 return insn | ((value & 0x1f) << 16);
1298}
1299
1300/* The RB field in an X form instruction when it must be the same as
1301 the RS field in the instruction. This is used for extended
1302 mnemonics like mr. This operand is marked FAKE. The insertion
1303 function just copies the BT field into the BA field, and the
1304 extraction function just checks that the fields are the same. */
1305
1306/*ARGSUSED*/
1307static unsigned long
1308insert_rbs (unsigned long insn,
1309 long value ATTRIBUTE_UNUSED,
1310 int dialect ATTRIBUTE_UNUSED,
1311 const char **errmsg ATTRIBUTE_UNUSED)
1312{
1313 return insn | (((insn >> 21) & 0x1f) << 11);
1314}
1315
1316static long
1317extract_rbs (unsigned long insn,
1318 int dialect ATTRIBUTE_UNUSED,
1319 int *invalid)
1320{
1321 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1322 *invalid = 1;
1323 return 0;
1324}
1325
1326/* The RT field of the DQ form lq instruction, which has special
1327 value restrictions. */
1328
1329/*ARGSUSED*/
1330static unsigned long
1331insert_rtq (unsigned long insn,
1332 long value,
1333 int dialect ATTRIBUTE_UNUSED,
1334 const char **errmsg)
1335{
1336 if ((value & 1) != 0)
1337 *errmsg = _("target register operand must be even");
1338 return insn | ((value & 0x1f) << 21);
1339}
1340
1341/* The RS field of the DS form stq instruction, which has special
1342 value restrictions. */
1343
1344/*ARGSUSED*/
1345static unsigned long
1346insert_rsq (unsigned long insn,
1347 long value ATTRIBUTE_UNUSED,
1348 int dialect ATTRIBUTE_UNUSED,
1349 const char **errmsg)
1350{
1351 if ((value & 1) != 0)
1352 *errmsg = _("source register operand must be even");
1353 return insn | ((value & 0x1f) << 21);
1354}
1355
1356/* The SH field in an MD form instruction. This is split. */
1357
1358/*ARGSUSED*/
1359static unsigned long
1360insert_sh6 (unsigned long insn,
1361 long value,
1362 int dialect ATTRIBUTE_UNUSED,
1363 const char **errmsg ATTRIBUTE_UNUSED)
1364{
1365 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1366}
1367
1368/*ARGSUSED*/
1369static long
1370extract_sh6 (unsigned long insn,
1371 int dialect ATTRIBUTE_UNUSED,
1372 int *invalid ATTRIBUTE_UNUSED)
1373{
1374 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1375}
1376
1377/* The SPR field in an XFX form instruction. This is flipped--the
1378 lower 5 bits are stored in the upper 5 and vice- versa. */
1379
1380static unsigned long
1381insert_spr (unsigned long insn,
1382 long value,
1383 int dialect ATTRIBUTE_UNUSED,
1384 const char **errmsg ATTRIBUTE_UNUSED)
1385{
1386 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1387}
1388
1389static long
1390extract_spr (unsigned long insn,
1391 int dialect ATTRIBUTE_UNUSED,
1392 int *invalid ATTRIBUTE_UNUSED)
1393{
1394 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1395}
1396
1397/* The TBR field in an XFX instruction. This is just like SPR, but it
1398 is optional. When TBR is omitted, it must be inserted as 268 (the
1399 magic number of the TB register). These functions treat 0
1400 (indicating an omitted optional operand) as 268. This means that
1401 ``mftb 4,0'' is not handled correctly. This does not matter very
1402 much, since the architecture manual does not define mftb as
1403 accepting any values other than 268 or 269. */
1404
1405#define TB (268)
1406
1407static unsigned long
1408insert_tbr (unsigned long insn,
1409 long value,
1410 int dialect ATTRIBUTE_UNUSED,
1411 const char **errmsg ATTRIBUTE_UNUSED)
1412{
1413 if (value == 0)
1414 value = TB;
1415 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1416}
1417
1418static long
1419extract_tbr (unsigned long insn,
1420 int dialect ATTRIBUTE_UNUSED,
1421 int *invalid ATTRIBUTE_UNUSED)
1422{
1423 long ret;
1424
1425 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1426 if (ret == TB)
1427 ret = 0;
1428 return ret;
1429}
1430
1431/* Macros used to form opcodes. */
1432
1433/* The main opcode. */
1434#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1435#define OP_MASK OP (0x3f)
1436
1437/* The main opcode combined with a trap code in the TO field of a D
1438 form instruction. Used for extended mnemonics for the trap
1439 instructions. */
1440#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1441#define OPTO_MASK (OP_MASK | TO_MASK)
1442
1443/* The main opcode combined with a comparison size bit in the L field
1444 of a D form or X form instruction. Used for extended mnemonics for
1445 the comparison instructions. */
1446#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1447#define OPL_MASK OPL (0x3f,1)
1448
1449/* An A form instruction. */
1450#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1451#define A_MASK A (0x3f, 0x1f, 1)
1452
1453/* An A_MASK with the FRB field fixed. */
1454#define AFRB_MASK (A_MASK | FRB_MASK)
1455
1456/* An A_MASK with the FRC field fixed. */
1457#define AFRC_MASK (A_MASK | FRC_MASK)
1458
1459/* An A_MASK with the FRA and FRC fields fixed. */
1460#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1461
1462/* A B form instruction. */
1463#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1464#define B_MASK B (0x3f, 1, 1)
1465
1466/* A B form instruction setting the BO field. */
1467#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1468#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1469
1470/* A BBO_MASK with the y bit of the BO field removed. This permits
1471 matching a conditional branch regardless of the setting of the y
1472 bit. Similarly for the 'at' bits used for power4 branch hints. */
1473#define Y_MASK (((unsigned long) 1) << 21)
1474#define AT1_MASK (((unsigned long) 3) << 21)
1475#define AT2_MASK (((unsigned long) 9) << 21)
1476#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1477#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1478
1479/* A B form instruction setting the BO field and the condition bits of
1480 the BI field. */
1481#define BBOCB(op, bo, cb, aa, lk) \
1482 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1483#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1484
1485/* A BBOCB_MASK with the y bit of the BO field removed. */
1486#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1487#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1488#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1489
1490/* A BBOYCB_MASK in which the BI field is fixed. */
1491#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1492#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1493
1494/* An Context form instruction. */
1495#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1496#define CTX_MASK CTX(0x3f, 0x7)
1497
1498/* An User Context form instruction. */
1499#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1500#define UCTX_MASK UCTX(0x3f, 0x1f)
1501
1502/* The main opcode mask with the RA field clear. */
1503#define DRA_MASK (OP_MASK | RA_MASK)
1504
1505/* A DS form instruction. */
1506#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1507#define DS_MASK DSO (0x3f, 3)
1508
1509/* A DE form instruction. */
1510#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1511#define DE_MASK DEO (0x3e, 0xf)
1512
1513/* An EVSEL form instruction. */
1514#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1515#define EVSEL_MASK EVSEL(0x3f, 0xff)
1516
1517/* An M form instruction. */
1518#define M(op, rc) (OP (op) | ((rc) & 1))
1519#define M_MASK M (0x3f, 1)
1520
1521/* An M form instruction with the ME field specified. */
1522#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1523
1524/* An M_MASK with the MB and ME fields fixed. */
1525#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1526
1527/* An M_MASK with the SH and ME fields fixed. */
1528#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1529
1530/* An MD form instruction. */
1531#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1532#define MD_MASK MD (0x3f, 0x7, 1)
1533
1534/* An MD_MASK with the MB field fixed. */
1535#define MDMB_MASK (MD_MASK | MB6_MASK)
1536
1537/* An MD_MASK with the SH field fixed. */
1538#define MDSH_MASK (MD_MASK | SH6_MASK)
1539
1540/* An MDS form instruction. */
1541#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1542#define MDS_MASK MDS (0x3f, 0xf, 1)
1543
1544/* An MDS_MASK with the MB field fixed. */
1545#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1546
1547/* An SC form instruction. */
1548#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1549#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1550
1551/* An VX form instruction. */
1552#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1553
1554/* The mask for an VX form instruction. */
1555#define VX_MASK VX(0x3f, 0x7ff)
1556
1557/* An VA form instruction. */
1558#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1559
1560/* The mask for an VA form instruction. */
1561#define VXA_MASK VXA(0x3f, 0x3f)
1562
1563/* An VXR form instruction. */
1564#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1565
1566/* The mask for a VXR form instruction. */
1567#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1568
1569/* An X form instruction. */
1570#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1571
1572/* An X form instruction with the RC bit specified. */
1573#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1574
1575/* The mask for an X form instruction. */
1576#define X_MASK XRC (0x3f, 0x3ff, 1)
1577
1578/* An X_MASK with the RA field fixed. */
1579#define XRA_MASK (X_MASK | RA_MASK)
1580
1581/* An X_MASK with the RB field fixed. */
1582#define XRB_MASK (X_MASK | RB_MASK)
1583
1584/* An X_MASK with the RT field fixed. */
1585#define XRT_MASK (X_MASK | RT_MASK)
1586
1587/* An X_MASK with the RA and RB fields fixed. */
1588#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1589
1590/* An XRARB_MASK, but with the L bit clear. */
1591#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1592
1593/* An X_MASK with the RT and RA fields fixed. */
1594#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1595
1596/* An XRTRA_MASK, but with L bit clear. */
1597#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1598
1599/* An X form comparison instruction. */
1600#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1601
1602/* The mask for an X form comparison instruction. */
1603#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1604
1605/* The mask for an X form comparison instruction with the L field
1606 fixed. */
1607#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1608
1609/* An X form trap instruction with the TO field specified. */
1610#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1611#define XTO_MASK (X_MASK | TO_MASK)
1612
1613/* An X form tlb instruction with the SH field specified. */
1614#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1615#define XTLB_MASK (X_MASK | SH_MASK)
1616
1617/* An X form sync instruction. */
1618#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1619
1620/* An X form sync instruction with everything filled in except the LS field. */
1621#define XSYNC_MASK (0xff9fffff)
1622
1623/* An X form AltiVec dss instruction. */
1624#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1625#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1626
1627/* An XFL form instruction. */
1628#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1629#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1630
1631/* An X form isel instruction. */
1632#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1633#define XISEL_MASK XISEL(0x3f, 0x1f)
1634
1635/* An XL form instruction with the LK field set to 0. */
1636#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1637
1638/* An XL form instruction which uses the LK field. */
1639#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1640
1641/* The mask for an XL form instruction. */
1642#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1643
1644/* An XL form instruction which explicitly sets the BO field. */
1645#define XLO(op, bo, xop, lk) \
1646 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1647#define XLO_MASK (XL_MASK | BO_MASK)
1648
1649/* An XL form instruction which explicitly sets the y bit of the BO
1650 field. */
1651#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1652#define XLYLK_MASK (XL_MASK | Y_MASK)
1653
1654/* An XL form instruction which sets the BO field and the condition
1655 bits of the BI field. */
1656#define XLOCB(op, bo, cb, xop, lk) \
1657 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1658#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1659
1660/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1661#define XLBB_MASK (XL_MASK | BB_MASK)
1662#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1663#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1664
1665/* An XL_MASK with the BO and BB fields fixed. */
1666#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1667
1668/* An XL_MASK with the BO, BI and BB fields fixed. */
1669#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1670
1671/* An XO form instruction. */
1672#define XO(op, xop, oe, rc) \
1673 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1674#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1675
1676/* An XO_MASK with the RB field fixed. */
1677#define XORB_MASK (XO_MASK | RB_MASK)
1678
1679/* An XS form instruction. */
1680#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1681#define XS_MASK XS (0x3f, 0x1ff, 1)
1682
1683/* A mask for the FXM version of an XFX form instruction. */
1684#define XFXFXM_MASK (X_MASK | (1 << 11))
1685
1686/* An XFX form instruction with the FXM field filled in. */
1687#define XFXM(op, xop, fxm) \
1688 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1689
1690/* An XFX form instruction with the SPR field filled in. */
1691#define XSPR(op, xop, spr) \
1692 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1693#define XSPR_MASK (X_MASK | SPR_MASK)
1694
1695/* An XFX form instruction with the SPR field filled in except for the
1696 SPRBAT field. */
1697#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1698
1699/* An XFX form instruction with the SPR field filled in except for the
1700 SPRG field. */
1701#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1702
1703/* An X form instruction with everything filled in except the E field. */
1704#define XE_MASK (0xffff7fff)
1705
1706/* An X form user context instruction. */
1707#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1708#define XUC_MASK XUC(0x3f, 0x1f)
1709
1710/* The BO encodings used in extended conditional branch mnemonics. */
1711#define BODNZF (0x0)
1712#define BODNZFP (0x1)
1713#define BODZF (0x2)
1714#define BODZFP (0x3)
1715#define BODNZT (0x8)
1716#define BODNZTP (0x9)
1717#define BODZT (0xa)
1718#define BODZTP (0xb)
1719
1720#define BOF (0x4)
1721#define BOFP (0x5)
1722#define BOFM4 (0x6)
1723#define BOFP4 (0x7)
1724#define BOT (0xc)
1725#define BOTP (0xd)
1726#define BOTM4 (0xe)
1727#define BOTP4 (0xf)
1728
1729#define BODNZ (0x10)
1730#define BODNZP (0x11)
1731#define BODZ (0x12)
1732#define BODZP (0x13)
1733#define BODNZM4 (0x18)
1734#define BODNZP4 (0x19)
1735#define BODZM4 (0x1a)
1736#define BODZP4 (0x1b)
1737
1738#define BOU (0x14)
1739
1740/* The BI condition bit encodings used in extended conditional branch
1741 mnemonics. */
1742#define CBLT (0)
1743#define CBGT (1)
1744#define CBEQ (2)
1745#define CBSO (3)
1746
1747/* The TO encodings used in extended trap mnemonics. */
1748#define TOLGT (0x1)
1749#define TOLLT (0x2)
1750#define TOEQ (0x4)
1751#define TOLGE (0x5)
1752#define TOLNL (0x5)
1753#define TOLLE (0x6)
1754#define TOLNG (0x6)
1755#define TOGT (0x8)
1756#define TOGE (0xc)
1757#define TONL (0xc)
1758#define TOLT (0x10)
1759#define TOLE (0x14)
1760#define TONG (0x14)
1761#define TONE (0x18)
1762#define TOU (0x1f)
1763
1764/* Smaller names for the flags so each entry in the opcodes table will
1765 fit on a single line. */
1766#undef PPC
1767#define PPC PPC_OPCODE_PPC
1768#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1769#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1770#define POWER4 PPC_OPCODE_POWER4
1771#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1772#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1773#define PPC403 PPC_OPCODE_403
1774#define PPC405 PPC403
1775#define PPC440 PPC_OPCODE_440
1776#define PPC750 PPC
1777#define PPC860 PPC
1778#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
1779#define POWER PPC_OPCODE_POWER
1780#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1781#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1782#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1783#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1784#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1785#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1786#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1787#define MFDEC1 PPC_OPCODE_POWER
1788#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1789#define BOOKE PPC_OPCODE_BOOKE
1790#define BOOKE64 PPC_OPCODE_BOOKE64
1791#define CLASSIC PPC_OPCODE_CLASSIC
1792#define PPCSPE PPC_OPCODE_SPE
1793#define PPCISEL PPC_OPCODE_ISEL
1794#define PPCEFS PPC_OPCODE_EFS
1795#define PPCBRLK PPC_OPCODE_BRLOCK
1796#define PPCPMR PPC_OPCODE_PMR
1797#define PPCCHLK PPC_OPCODE_CACHELCK
1798#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1799#define PPCRFMCI PPC_OPCODE_RFMCI
1800
1801/* The opcode table.
1802
1803 The format of the opcode table is:
1804
1805 NAME OPCODE MASK FLAGS { OPERANDS }
1806
1807 NAME is the name of the instruction.
1808 OPCODE is the instruction opcode.
1809 MASK is the opcode mask; this is used to tell the disassembler
1810 which bits in the actual opcode must match OPCODE.
1811 FLAGS are flags indicated what processors support the instruction.
1812 OPERANDS is the list of operands.
1813
1814 The disassembler reads the table in order and prints the first
1815 instruction which matches, so this table is sorted to put more
1816 specific instructions before more general instructions. It is also
1817 sorted by major opcode. */
1818
1819const struct powerpc_opcode powerpc_opcodes[] = {
1820{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
1821{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1822{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1823{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1824{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1825{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1826{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1827{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1828{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1829{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1830{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1831{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1832{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1833{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1834{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1835{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1836
1837{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1838{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1839{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1840{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1841{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1842{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1843{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1844{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1845{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1846{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1847{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1848{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1849{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1850{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1851{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1852{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1853{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1854{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1855{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1856{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1857{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1858{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1859{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1860{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1861{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1862{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1863{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1864{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1865{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1866{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1867
1868{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1869{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1870{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1871{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1872{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1873{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1874{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1875{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1876{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1877{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1878{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1879{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1880{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1881{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1882{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1883{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1884{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1885{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1886{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1887{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1888{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1889{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1890{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1891{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1892{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1893{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1894{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1895{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1896{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1897{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1898{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1899{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1900{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1901{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1902{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1903{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1904{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1905{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1906{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1907{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1908{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1909{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1910{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1911{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1912{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1913{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1914{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1915{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1916{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1917{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1918{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1919{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1920{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1921{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1922{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1923{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1924{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1925{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1926{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1927{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1928{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1929{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1930{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1931{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1932{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1933{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1934{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1935{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1936{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1937{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1938{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1939{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1940{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1941{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1942{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1943{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1944{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1945{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1946{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1947{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1948{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1949{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1950{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1951{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1952{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1953{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1954{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1955{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1956{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1957{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1958{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1959{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1960{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1961{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1962{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1963{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1964{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1965{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1966{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1967{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1968{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1969{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1970{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1971{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1972{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1973{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1974{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1975{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1976{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1977{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1978{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1979{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1980{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1981{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1982{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1983{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1984{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1985{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1986{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1987{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1988{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1989{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1990{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1991{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1992{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1993{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1994{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1995{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1996{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1997{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1998{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1999{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2000{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2001{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2002{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2003{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2004{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2005{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2006{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2007{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2008{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2009{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2010{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2011{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2012{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2013{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2014{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2015{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2016{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2017{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2018{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2019{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2020{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2021{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2022{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2023{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2024{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2025{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2026{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2027{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2028{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2029{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2030{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2031{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2032{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2033{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2034{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2035{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2036{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2037{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2038{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2039{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2040{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2041{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2042{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2043{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2044{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2045{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2046{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2047{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2048{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2049{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2050{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2051{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2052{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2053{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2054{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2055{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2056{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2057{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2058{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2059{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2060{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2061{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2062{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2063{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2064{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2065{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2066{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2067{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2068{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2069{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2070{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2071{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2072{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2073{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2074{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2075{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2076{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2077{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2078{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2079{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2080{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2081{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2082{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2083{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2084{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2085{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2086{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2087{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2088{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2089{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2090{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2091{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2092{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2093{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2094{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2095{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2096{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2097{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2098{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2099{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2100{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2101{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2102{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2103{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2104{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2105{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2106{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2107{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2108{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2109
2110{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2111{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2112{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2113{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2114{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2115{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2116{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2117{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2118{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2119{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2120{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2121{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2122{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2123
2124{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2125
2126{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2127{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2128{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2129{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2130{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2131{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2132{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2133{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2134{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2135{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2136
2137{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2138{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2139{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2140{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2141{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2142{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2143{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2144{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2145{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2146{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2147{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2148{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2149{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2150{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2151
2152{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2153{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2154{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2155{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2156{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2157{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2158
2159{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2160{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2161{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2162{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2163{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2164{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2165{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2166{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2167{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2168{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2169{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2170{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2171{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2172{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2173{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2174{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2175{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2176{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2177{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2178{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2179{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2180{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2181
2182{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2183{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2184{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2185{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2186{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2187{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2188{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2189{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2190{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2191{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2192{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2193{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2194{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2195{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2196
2197{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2198{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2199{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2200{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2201{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2202{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2203{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2204{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2205{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2206{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2207{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2208{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2209{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2210{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2211{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2212{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2213{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2214{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2215{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2216{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2217{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2218{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2219{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2220
2221{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2222{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2223{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2224{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2225{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2226{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2227{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2228{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2229{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2230{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2231{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2232{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2233{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2234{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2235{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2236{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2237{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2238{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2239{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2240{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2241{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2242{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2243{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2244
2245{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2246{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2247{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2248{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2249{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2250{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2251{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2252{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2253{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2254{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2255{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2256{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2257{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2258{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2259{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2260{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2261
2262{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2263{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2264{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2265{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2266{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2267{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2268{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2269{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2270{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2271{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2272{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2273{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2274
2275{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2276{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2277{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2278{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2279{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2280{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2281{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2282{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2283{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2284{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2285{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2286{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2287
2288{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2289{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2290{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2291{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2292{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2293{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2294
2295{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2296{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2297{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2298{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2299{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2300{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2301
2302{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2303{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2304{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2305{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2306{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2307{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2308{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2309{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2310
2311{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2312{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2313
2314{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2315{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2316{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2317{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2318
2319{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2320{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2321{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2322{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2323
2324{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2325{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2326{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2327{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2328{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2329{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2330{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2331{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2332
2333{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2334{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2335{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2336{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2337
2338{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2339{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2340{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2341{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2342
2343{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2344{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2345{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2346{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2347
2348{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2349{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2350{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2351{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2352
2353{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2354
2355{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2356{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2357
2358{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2359{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2360
2361{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2362{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2363
2364{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2365
2366{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2367{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2368{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2369{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2370
2371{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2372{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2373{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2374{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2375
2376{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2377{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2378{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2379{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2380
2381{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2382{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2383{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2384
2385{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2386{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2387{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2388
2389{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2390{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2391{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
2392{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
2393{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
2394{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
2395
2396{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2397{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2398{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
2399{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
2400{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
2401
2402{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2403{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2404{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2405{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2406{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2407{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2408{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2409{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2410{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2411{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2412{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2413{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2414{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2415{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2416{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2417{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2418{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2419{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2420{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2421{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2422{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2423{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2424{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2425{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2426{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2427{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2428{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2429{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2430{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2431{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2432{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2433{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2434{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2435{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2436{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2437{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2438{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2439{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2440{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2441{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2442{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2443{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2444{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2445{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2446{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2447{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2448{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2449{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2450{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2451{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2452{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2453{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2454{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2455{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2456{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2457{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2458{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2459{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2460{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2461{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2462{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2463{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2464{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2465{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2466{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2467{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2468{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2469{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2470{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2471{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2472{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2473{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2474{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2475{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2476{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2477{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2478{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2479{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2480{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2481{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2482{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2483{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2484{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2485{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2486{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2487{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2488{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2489{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2490{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2491{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2492{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2493{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2494{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2495{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2496{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2497{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2498{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2499{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2500{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2501{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2502{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2503{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2504{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2505{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2506{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2507{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2508{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2509{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2510{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2511{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2512{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2513{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2514{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2515{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2516{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2517{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2518{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2519{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2520{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2521{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2522{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2523{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2524{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2525{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2526{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2527{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2528{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2529{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2530{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2531{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2532{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2533{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2534{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2535{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2536{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2537{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2538{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2539{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2540{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2541{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2542{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2543{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2544{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2545{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2546{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2547{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2548{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2549{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2550{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2551{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2552{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2553{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2554{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2555{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2556{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2557{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2558{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2559{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2560{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2561{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2562{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2563{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2564{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2565{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2566{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2567{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2568{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2569{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2570{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2571{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2572{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2573{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2574{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2575{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2576{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2577{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2578{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2579{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2580{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2581{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2582{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2583{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2584{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2585{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2586{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2587{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2588{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2589{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2590{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2591{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2592{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2593{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2594{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2595{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2596{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2597{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2598{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2599{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2600{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2601{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2602{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2603{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2604{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2605{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2606{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2607{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2608{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2609{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2610{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2611{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2612{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2613{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2614{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2615{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2616{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2617{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2618{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2619{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2620{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2621{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2622{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2623{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2624{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2625{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2626{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2627{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2628{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2629{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2630{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2631{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2632{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2633{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2634{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2635{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2636{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2637{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2638{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2639{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2640{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2641{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2642{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2643{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2644{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2645{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2646{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2647{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2648{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2649{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2650{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2651{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2652{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2653{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2654{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2655{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2656{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2657{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2658{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2659{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2660{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2661{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2662{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2663{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2664{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2665{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2666
2667{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2668{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2669{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2670{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2671{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2672
2673{ "b", B(18,0,0), B_MASK, COM, { LI } },
2674{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2675{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2676{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
2677
2678{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2679
2680{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2681{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2682{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2683{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2684{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2685{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2686{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2687{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2688{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2689{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2690{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2691{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2692{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2693{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2694{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2695{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2696{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2697{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2698{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2699{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2700{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2701{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2702{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2703{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2704{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2705{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2706{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2707{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2708{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2709{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2710{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2711{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2712{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2713{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2714{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2715{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2716{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2717{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2718{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2719{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2720{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2721{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2722{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2723{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2724{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2725{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2726{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2727{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2728{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2729{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2730{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2731{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2732{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2733{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2734{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2735{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2736{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2737{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2738{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2739{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2740{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2741{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2742{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2743{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2744{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2745{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2746{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2747{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2748{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2749{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2750{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2751{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2752{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2753{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2754{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2755{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2756{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2757{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2758{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2759{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2760{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2761{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2762{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2763{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2764{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2765{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2766{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2767{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2768{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2769{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2770{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2771{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2772{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2773{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2774{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2775{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2776{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2777{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2778{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2779{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2780{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2781{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2782{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2783{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2784{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2785{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2786{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2787{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2788{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2789{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2790{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2791{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2792{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2793{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2794{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2795{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2796{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2797{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2798{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2799{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2800{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2801{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2802{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2803{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2804{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2805{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2806{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2807{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2808{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2809{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2810{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2811{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2812{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2813{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2814{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2815{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2816{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2817{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2818{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2819{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2820{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2821{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2822{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2823{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2824{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2825{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2826{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2827{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2828{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2829{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2830{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2831{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2832{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2833{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2834{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2835{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2836{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2837{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2838{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2839{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2840{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2841{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2842{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2843{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2844{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2845{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2846{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2847{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2848{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2849{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2850{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2851{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2852{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2853{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2854{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2855{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2856{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2857{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2858{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2859{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2860{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2861{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2862{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2863{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2864{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2865{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2866{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2867{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2868{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2869{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2870{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2871{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2872{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2873{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2874{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2875{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2876{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2877{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2878{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2879{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2880{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2881{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2882{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2883{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2884{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2885{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2886{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2887{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2888{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2889{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2890{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2891{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2892{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2893{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2894{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2895{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2896{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2897{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2898{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2899{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2900{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2901{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2902
2903{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2904
2905{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2906{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2907{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2908
2909{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2910{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
2911
2912{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2913
2914{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2915
2916{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2917{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2918
2919{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2920{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2921
2922{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2923
2924{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2925
2926{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2927{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2928
2929{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2930
2931{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2932{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2933
2934{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2935{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2936{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2937{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2938{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2939{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2940{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2941{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2942{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2943{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2944{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2945{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2946{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2947{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2948{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2949{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2950{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2951{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2952{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2953{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2954{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2955{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2956{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2957{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2958{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2959{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2960{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2961{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2962{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2963{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2964{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2965{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2966{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2967{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2968{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2969{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2970{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2971{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2972{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2973{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2974{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2975{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2976{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2977{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2978{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2979{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2980{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2981{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2982{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2983{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2984{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2986{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2987{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2988{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2989{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2991{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2992{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2993{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2994{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2995{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2996{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2997{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2998{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2999{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3000{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3001{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3002{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3003{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3004{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3005{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3006{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3007{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3008{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3009{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3010{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3011{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3012{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3013{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3014{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3015{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3016{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3017{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3018{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3019{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3020{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3021{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3022{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3023{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3024{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3025{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3026{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3027{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3028{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3029{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3030{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3031{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3032{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3033{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3034{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3035{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3036{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3037{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3038{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3039{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3040{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3041{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3042{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3043{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3044{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3045{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3046{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3047{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3048{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3049{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3050{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3051{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3052{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3053{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3054{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3055{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3056{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3057{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3058{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3059{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3060{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3061{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3062{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3063{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3064{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3065{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3066{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3067{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3068{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3069{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3070{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3071{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3072{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3073{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3074{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3075{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3076{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
3077{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3078{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3079{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
3080{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3081{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3082{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3083{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3084{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3085{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3086
3087{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3088{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3089
3090{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3091{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3092
3093{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3094{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3095{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3096{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3097{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3098{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3099{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3100{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3101
3102{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3103{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3104
3105{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3106{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3107{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3108{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3109
3110{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3111{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3112{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3113{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3114{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3115{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3116
3117{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3118{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3119{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3120
3121{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3122{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3123
3124{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3125{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3126
3127{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3128{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3129
3130{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3131{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3132
3133{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3134{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3135
3136{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3137{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3138{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3139{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3140{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3141{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3142
3143{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3144{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3145
3146{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3147{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3148
3149{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3150{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3151
3152{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3153{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3154{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3155{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3156
3157{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3158{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3159
3160{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3161{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3162{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3163{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3164
3165{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3166{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3167{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3168{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3169{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3170{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3171{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3172{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3173{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3174{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3175{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3176{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3177{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3178{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3179{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3180{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3181{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3182{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3183{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3184{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3185{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3186{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3187{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3188{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3189{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3190{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3191{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3192{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3193{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3194{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3195{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3196
3197{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3198{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3199{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3200{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3201{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3202{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3203{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3204{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3205{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3206{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3207{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3208{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3209
3210{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3211{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3212
3213{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3214{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3215{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3216{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3217{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3218{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3219{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3220{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3221
3222{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3223{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3224
3225{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3226{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3227{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3228{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3229
3230{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3231{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3232
3233{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
3234
3235{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
3236
3237{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3238{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3239
3240{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
3241{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3242
3243{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3244{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3245{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3246{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3247
3248{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3249{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3250{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3251{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3252
3253{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3254{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3255
3256{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3257{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3258
3259{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3260{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3261
3262{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3263
3264{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
3265
3266{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3267{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3268{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3269{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3270
3271{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3272{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3273{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3274{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3275{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3276{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3277{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3278{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3279
3280{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3281
3282{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3283
3284{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3285{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3286
3287{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3288
3289{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3290
3291{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3292{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3293
3294{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3295{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3296
3297{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3298{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3299{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3300{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3301{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3302{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3303{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3304{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3305{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3306{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3307{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3308{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3309{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3310{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3311{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3312
3313{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3314{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3315
3316{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3317{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3318
3319{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3320{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3321
3322{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3323
3324{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3325
3326{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
3327
3328{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3329
3330{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
3331
3332{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3333
3334{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
3335
3336{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3337{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3338{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3339{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3340
3341{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3342{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3343{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3344{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3345
3346{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3347
3348{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3349
3350{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3351
3352{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3353{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3354{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3355{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3356
3357{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
3358
3359{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3360
3361{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3362
3363{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3364
3365{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3366{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3367{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3368{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3369{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3370{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3371{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3372{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3373
3374{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3375{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3376{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3377{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3378{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3379{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3380{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3381{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3382
3383{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3384
3385{ "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }},
3386{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3387
3388{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3389
3390{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
3391
3392{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
3393
3394{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
3395{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3396
3397{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
3398
3399{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
3400
3401{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3402{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3403
3404{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3405{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3406
3407{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3408
3409{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3410{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3411
3412{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3413
3414{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3415
3416{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3417{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
3418
3419{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3420{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3421
3422{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3423
3424{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3425{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3426{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3427{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3428{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3429{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3430{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3431{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3432
3433{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3434{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3435{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3436{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3437{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3438{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3439{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3440{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3441
3442{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3443
3444{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
3445
3446{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
3447
3448{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3449{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3450
3451{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3452{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3453
3454{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
3455
3456{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3457
3458{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3459{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3460{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3461{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3462{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3463{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3464{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3465{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3466
3467{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3468{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3469{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3470{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3471
3472{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3473{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3474{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3475{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3476{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3477{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3478{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3479{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3480
3481{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3482{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3483{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3484{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3485{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3486{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3487{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3488{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3489
3490{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3491{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3492{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3493
3494{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
3495
3496{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3497
3498{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3499{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3500
3501{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3502
3503{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3504
3505{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3506
3507{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3508{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3509{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3510{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3511
3512{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3513{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3514{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3515{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3516{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3517{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3518{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3519{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3520
3521{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3522
3523{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3524
3525{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3526{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3527
3528{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
3529
3530{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3531
3532{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3533{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3534
3535{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3536
3537{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3538
3539{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3540{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3541
3542{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3543
3544{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3545
3546{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3547{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3548
3549{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3550
3551{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3552{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3553{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3554{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3555{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3556{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3557{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3558{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3559{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3560{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3561{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3562{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3563{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3564{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3565{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3566{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3567{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3568{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3569{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3570{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3571{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3572{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3573{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3574{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3575{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3576{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3577{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3578{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3579{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3580{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3581{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3582{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3583{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3584{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3585{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3586
3587{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3588{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3589{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3590{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3591
3592{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3593
3594{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3595{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3596{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3597{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3598{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3599{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3600{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3601{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3602{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3603{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3604{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3605{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3606{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3607{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3608{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3609{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3610{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3611{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3612{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3613{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3614{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3615{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3616{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3617{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3618{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3619{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3620{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3621{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3622{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3623{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3624{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3625{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3626{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3627{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3628{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3629{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3630{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3631{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3632{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3633{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3634{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3635{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3636{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3637{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3638{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3639{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3640{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3641{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3642{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3643{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3644{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3645{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3646{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3647{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3648{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3649{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3650{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3651{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3652{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3653{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3654{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3655{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3656{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3657{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3658{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3659{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3660{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3661{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3662{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3663{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3664{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3665{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3666{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3667{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3668{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3669{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3670{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3671{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3672{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3673{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3674{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3675{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3676{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3677{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3678{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3679{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3680{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3681{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3682{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3683{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3684{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3685{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3686{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3687{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3688{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3689{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3690{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3691{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3692{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3693{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3694{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3695{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3696{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3697{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3698{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3699{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3700{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3701{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3702{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3703{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3704{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3705{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3706{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3707{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3708{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3709{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3710{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3711{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3712{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3713{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3714{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3715{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3716{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3717{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3718{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3719{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3720{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3721{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3722{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3723{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3724{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3725{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3726{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3727{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3728{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3729{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3730{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3731{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3732{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3733{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3734{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3735{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3736{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3737{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3738{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3739{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3740{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3741{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3742{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3743{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3744{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3745{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3746{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3747{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3748{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3749{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3750{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3751{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3752{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3753{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3754{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3755{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3756{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3757{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3758{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3759{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3760{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3761{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3762{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3763{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3764{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3765{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3766{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3767{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3768{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3769{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3770{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3771{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3772{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3773{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3774{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3775{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3776
3777{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3778
3779{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3780{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3781
3782{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3783
3784{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3785
3786{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3787{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3788
3789{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3790
3791{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3792{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3793{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3794{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3795
3796{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3797{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3798{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3799{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3800
3801{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3802
3803{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3804
3805{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3806
3807{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3808
3809{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3810
3811{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3812
3813{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3814{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3815
3816{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3817{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3818
3819{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3820
3821{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3822
3823{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3824
3825{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3826
3827{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3828
3829{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3830
3831{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3832
3833{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3834{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3835
3836{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3837{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3838
3839{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3840
3841{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3842
3843{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3844
3845{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3846
3847{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3848
3849{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3850{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3851{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3852{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3853
3854{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3855{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3856{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3857{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3858{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3859{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3860{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3861{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3862{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3863{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3864{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3865{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3866{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3867{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3868{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3869{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3870{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3871{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3872{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3873{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3874{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3875{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3876{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3877{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3878{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3879{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3880{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3881{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3882{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3883{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3884{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3885{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3886{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3887{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3888{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3889
3890{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3891{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3892
3893{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3894{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3895{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3896{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3897
3898{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3899{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3900
3901{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3902{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3903{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3904{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3905
3906{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3907{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3908{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3909{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3910{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3911{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3912{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3913{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3914{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3915{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3916{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3917{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3918{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3919{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3920{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3921{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3922{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3923{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3924{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3925{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3926{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
3927{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3928{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
3929{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3930{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3931{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3932{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3933{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3934{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3935{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3936{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3937{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3938{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3939{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3940{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3941{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3942{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3943{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3944{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3945{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3946{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
3947{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3948{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
3949{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3950{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3951{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
3952{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
3953{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
3954{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
3955{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
3956{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
3957{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3958{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3959{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3960{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3961{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3962{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
3963{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3964{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
3965{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3966{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
3967{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3968{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3969{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
3970{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3971{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
3972{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3973{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
3974{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3975{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
3976{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3977{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
3978{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3979{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
3980{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3981{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
3982{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3983{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
3984{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3985{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
3986{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3987{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
3988{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3989{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3990{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3991{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3992{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3993{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3994{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3995{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3996{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3997{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3998{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
3999{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4000{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4001{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4002{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4003{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4004{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4005{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4006{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4007{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4008{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4009{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4010{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4011{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4012{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4013{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4014{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4015{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4016{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4017{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4018{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4019{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4020{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4021{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4022{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4023{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4024{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4025{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4026{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4027{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4028{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4029{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4030{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4031{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4032{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4033{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4034{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4035{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4036{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4037{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4038{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4039{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4040{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4041{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4042{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4043{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4044{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4045{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4046{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4047{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4048{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4049{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4050{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4051{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4052{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4053{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4054
4055{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4056
4057{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4058{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4059
4060{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4061
4062{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4063
4064{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4065
4066{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4067
4068{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4069{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4070{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4071{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4072{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4073{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4074
4075{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4076{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4077{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4078{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4079
4080{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4081{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4082
4083{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4084{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4085{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4086{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4087
4088{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4089
4090{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4091
4092{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4093
4094{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4095
4096{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4097
4098{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4099{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4100
4101{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4102
4103{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
4104{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4105
4106{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
4107{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4108
4109{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
4110
4111{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4112{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4113{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4114{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4115
4116{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4117{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4118
4119{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4120{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4121
4122{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4123{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4124
4125{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
4126
4127{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
4128
4129{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4130{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4131
4132{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4133
4134{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4135
4136{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4137
4138{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
4139{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
4140
4141{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4142{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4143{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4144{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4145{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4146
4147{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
4148
4149{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
4150
4151{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4152
4153{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4154
4155{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4156
4157{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4158
4159{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4160
4161{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
4162{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
4163
4164{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
4165{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
4166
4167{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
4168
4169{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4170{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4171
4172{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4173{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4174
4175{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
4176
4177{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
4178
4179{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4180
4181{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4182{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4183
4184{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4185
4186{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
4187{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
4188
4189{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
4190
4191{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4192{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4193
4194{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4195{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4196
4197{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
4198
4199{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4200
4201{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4202
4203{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4204{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4205
4206{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4207
4208{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4209
4210{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4211{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4212
4213{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
4214
4215{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4216{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4217{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4218{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4219
4220{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4221{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4222
4223{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
4224
4225{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
4226{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
4227
4228{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4229
4230{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4231{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4232
4233{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4234{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4235{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4236{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4237
4238{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4239
4240{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4241{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4242
4243{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
4244{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4245{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
4246{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
4247{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4248{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4249
4250{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4251
4252{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
4253
4254{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4255{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4256
4257{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4258{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4259
4260{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4261{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4262{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4263{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4264
4265{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
4266
4267{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
4268
4269{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4270{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4271{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
4272{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
4273
4274{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4275{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4276
4277{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4278{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4279
4280{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4281
4282{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4283
4284{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4285{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4286{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
4287{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4288{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4289
4290{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4291
4292{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
4293
4294{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4295{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4296
4297{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4298
4299{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4300{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
4301
4302{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4303
4304{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4305{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4306
4307{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4308
4309{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4310{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4311{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4312{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4313{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4314{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4315{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4316{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4317{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4318{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4319{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4320{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4321
4322{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
4323{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
4324
4325{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4326{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
4327
4328{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
4329
4330{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4331
4332{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
4333{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
4334
4335{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4336{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
4337
4338{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
4339
4340{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4341
4342{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
4343
4344{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4345
4346{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
4347
4348{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4349
4350{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
4351
4352{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4353
4354{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4355{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
4356
4357{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
4358{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
4359
4360{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
4361
4362{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4363
4364{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
4365
4366{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4367
4368{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
4369
4370{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4371
4372{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
4373
4374{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4375
4376{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4377
4378{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
4379
4380{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
4381
4382{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
4383{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4384{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
4385{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4386{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
4387{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4388{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
4389{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4390{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
4391{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4392{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
4393{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4394{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
4395{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4396
4397{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
4398
4399{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4400
4401{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
4402
4403{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4404{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4405
4406{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4407{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4408
4409{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4410{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4411
4412{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4413{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4414
4415{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4416{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4417
4418{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4419{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4420
4421{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4422{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4423
4424{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4425{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4426
4427{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4428{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4429
4430{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4431{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4432
4433{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4434
4435{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4436
4437{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
4438{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
4439{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
4440{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4441{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
4442{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4443{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
4444{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4445{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
4446{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4447{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
4448{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4449
4450{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
4451
4452{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4453
4454{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
4455
4456{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4457
4458{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4459{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4460
4461{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4462{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4463{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4464{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4465
4466{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4467{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4468{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4469{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4470
4471{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4472{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4473{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4474{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4475
4476{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4477{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4478{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4479{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4480
4481{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4482{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4483{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4484{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4485
4486{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4487{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4488
4489{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4490{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4491
4492{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4493{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4494{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4495{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4496
4497{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4498{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4499
4500{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4501{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4502{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4503{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4504
4505{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4506{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4507{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4508{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4509
4510{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4511{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4512{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4513{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4514
4515{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4516{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4517{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4518{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4519
4520{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4521
4522{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4523{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4524
4525{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4526{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4527
4528{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4529
4530{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4531{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4532
4533{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4534{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4535
4536{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4537{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4538
4539{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4540{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4541
4542{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4543{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4544
4545{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4546{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4547
4548{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4549{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4550
4551{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4552{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4553
4554{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4555{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4556
4557{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4558{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4559
4560};
4561
4562const int powerpc_num_opcodes =
4563 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4564
4565/* The macro table. This is only used by the assembler. */
4566
4567/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4568 when x=0; 32-x when x is between 1 and 31; are negative if x is
4569 negative; and are 32 or more otherwise. This is what you want
4570 when, for instance, you are emulating a right shift by a
4571 rotate-left-and-mask, because the underlying instructions support
4572 shifts of size 0 but not shifts of size 32. By comparison, when
4573 extracting x bits from some word you want to use just 32-x, because
4574 the underlying instructions don't support extracting 0 bits but do
4575 support extracting the whole word (32 bits in this case). */
4576
4577const struct powerpc_macro powerpc_macros[] = {
4578{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4579{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4580{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4581{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4582{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4583{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4584{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4585{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4586{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4587{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4588{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4589{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4590{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4591{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4592{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4593{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4594
4595{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4596{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4597{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4598{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4599{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4600{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4601{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4602{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4603{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4604{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4605{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4606{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4607{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4608{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4609{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4610{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4611{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4612{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4613{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4614{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4615{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4616{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4617};
4618
4619const int powerpc_num_macros =
4620 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
diff --git a/arch/ppc64/xmon/ppc.h b/arch/ppc64/xmon/ppc.h
new file mode 100644
index 000000000000..342237e8dd69
--- /dev/null
+++ b/arch/ppc64/xmon/ppc.h
@@ -0,0 +1,307 @@
1/* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
111, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free
20Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22#ifndef PPC_H
23#define PPC_H
24
25/* The opcode table is an array of struct powerpc_opcode. */
26
27struct powerpc_opcode
28{
29 /* The opcode name. */
30 const char *name;
31
32 /* The opcode itself. Those bits which will be filled in with
33 operands are zeroes. */
34 unsigned long opcode;
35
36 /* The opcode mask. This is used by the disassembler. This is a
37 mask containing ones indicating those bits which must match the
38 opcode field, and zeroes indicating those bits which need not
39 match (and are presumably filled in by operands). */
40 unsigned long mask;
41
42 /* One bit flags for the opcode. These are used to indicate which
43 specific processors support the instructions. The defined values
44 are listed below. */
45 unsigned long flags;
46
47 /* An array of operand codes. Each code is an index into the
48 operand table. They appear in the order which the operands must
49 appear in assembly code, and are terminated by a zero. */
50 unsigned char operands[8];
51};
52
53/* The table itself is sorted by major opcode number, and is otherwise
54 in the order in which the disassembler should consider
55 instructions. */
56extern const struct powerpc_opcode powerpc_opcodes[];
57extern const int powerpc_num_opcodes;
58
59/* Values defined for the flags field of a struct powerpc_opcode. */
60
61/* Opcode is defined for the PowerPC architecture. */
62#define PPC_OPCODE_PPC 1
63
64/* Opcode is defined for the POWER (RS/6000) architecture. */
65#define PPC_OPCODE_POWER 2
66
67/* Opcode is defined for the POWER2 (Rios 2) architecture. */
68#define PPC_OPCODE_POWER2 4
69
70/* Opcode is only defined on 32 bit architectures. */
71#define PPC_OPCODE_32 8
72
73/* Opcode is only defined on 64 bit architectures. */
74#define PPC_OPCODE_64 0x10
75
76/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
77 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
78 but it also supports many additional POWER instructions. */
79#define PPC_OPCODE_601 0x20
80
81/* Opcode is supported in both the Power and PowerPC architectures
82 (ie, compiler's -mcpu=common or assembler's -mcom). */
83#define PPC_OPCODE_COMMON 0x40
84
85/* Opcode is supported for any Power or PowerPC platform (this is
86 for the assembler's -many option, and it eliminates duplicates). */
87#define PPC_OPCODE_ANY 0x80
88
89/* Opcode is supported as part of the 64-bit bridge. */
90#define PPC_OPCODE_64_BRIDGE 0x100
91
92/* Opcode is supported by Altivec Vector Unit */
93#define PPC_OPCODE_ALTIVEC 0x200
94
95/* Opcode is supported by PowerPC 403 processor. */
96#define PPC_OPCODE_403 0x400
97
98/* Opcode is supported by PowerPC BookE processor. */
99#define PPC_OPCODE_BOOKE 0x800
100
101/* Opcode is only supported by 64-bit PowerPC BookE processor. */
102#define PPC_OPCODE_BOOKE64 0x1000
103
104/* Opcode is supported by PowerPC 440 processor. */
105#define PPC_OPCODE_440 0x2000
106
107/* Opcode is only supported by Power4 architecture. */
108#define PPC_OPCODE_POWER4 0x4000
109
110/* Opcode isn't supported by Power4 architecture. */
111#define PPC_OPCODE_NOPOWER4 0x8000
112
113/* Opcode is only supported by POWERPC Classic architecture. */
114#define PPC_OPCODE_CLASSIC 0x10000
115
116/* Opcode is only supported by e500x2 Core. */
117#define PPC_OPCODE_SPE 0x20000
118
119/* Opcode is supported by e500x2 Integer select APU. */
120#define PPC_OPCODE_ISEL 0x40000
121
122/* Opcode is an e500 SPE floating point instruction. */
123#define PPC_OPCODE_EFS 0x80000
124
125/* Opcode is supported by branch locking APU. */
126#define PPC_OPCODE_BRLOCK 0x100000
127
128/* Opcode is supported by performance monitor APU. */
129#define PPC_OPCODE_PMR 0x200000
130
131/* Opcode is supported by cache locking APU. */
132#define PPC_OPCODE_CACHELCK 0x400000
133
134/* Opcode is supported by machine check APU. */
135#define PPC_OPCODE_RFMCI 0x800000
136
137/* A macro to extract the major opcode from an instruction. */
138#define PPC_OP(i) (((i) >> 26) & 0x3f)
139
140/* The operands table is an array of struct powerpc_operand. */
141
142struct powerpc_operand
143{
144 /* The number of bits in the operand. */
145 int bits;
146
147 /* How far the operand is left shifted in the instruction. */
148 int shift;
149
150 /* Insertion function. This is used by the assembler. To insert an
151 operand value into an instruction, check this field.
152
153 If it is NULL, execute
154 i |= (op & ((1 << o->bits) - 1)) << o->shift;
155 (i is the instruction which we are filling in, o is a pointer to
156 this structure, and op is the opcode value; this assumes twos
157 complement arithmetic).
158
159 If this field is not NULL, then simply call it with the
160 instruction and the operand value. It will return the new value
161 of the instruction. If the ERRMSG argument is not NULL, then if
162 the operand value is illegal, *ERRMSG will be set to a warning
163 string (the operand will be inserted in any case). If the
164 operand value is legal, *ERRMSG will be unchanged (most operands
165 can accept any value). */
166 unsigned long (*insert)
167 (unsigned long instruction, long op, int dialect, const char **errmsg);
168
169 /* Extraction function. This is used by the disassembler. To
170 extract this operand type from an instruction, check this field.
171
172 If it is NULL, compute
173 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
174 if ((o->flags & PPC_OPERAND_SIGNED) != 0
175 && (op & (1 << (o->bits - 1))) != 0)
176 op -= 1 << o->bits;
177 (i is the instruction, o is a pointer to this structure, and op
178 is the result; this assumes twos complement arithmetic).
179
180 If this field is not NULL, then simply call it with the
181 instruction value. It will return the value of the operand. If
182 the INVALID argument is not NULL, *INVALID will be set to
183 non-zero if this operand type can not actually be extracted from
184 this operand (i.e., the instruction does not match). If the
185 operand is valid, *INVALID will not be changed. */
186 long (*extract) (unsigned long instruction, int dialect, int *invalid);
187
188 /* One bit syntax flags. */
189 unsigned long flags;
190};
191
192/* Elements in the table are retrieved by indexing with values from
193 the operands field of the powerpc_opcodes table. */
194
195extern const struct powerpc_operand powerpc_operands[];
196
197/* Values defined for the flags field of a struct powerpc_operand. */
198
199/* This operand takes signed values. */
200#define PPC_OPERAND_SIGNED (01)
201
202/* This operand takes signed values, but also accepts a full positive
203 range of values when running in 32 bit mode. That is, if bits is
204 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
205 this flag is ignored. */
206#define PPC_OPERAND_SIGNOPT (02)
207
208/* This operand does not actually exist in the assembler input. This
209 is used to support extended mnemonics such as mr, for which two
210 operands fields are identical. The assembler should call the
211 insert function with any op value. The disassembler should call
212 the extract function, ignore the return value, and check the value
213 placed in the valid argument. */
214#define PPC_OPERAND_FAKE (04)
215
216/* The next operand should be wrapped in parentheses rather than
217 separated from this one by a comma. This is used for the load and
218 store instructions which want their operands to look like
219 reg,displacement(reg)
220 */
221#define PPC_OPERAND_PARENS (010)
222
223/* This operand may use the symbolic names for the CR fields, which
224 are
225 lt 0 gt 1 eq 2 so 3 un 3
226 cr0 0 cr1 1 cr2 2 cr3 3
227 cr4 4 cr5 5 cr6 6 cr7 7
228 These may be combined arithmetically, as in cr2*4+gt. These are
229 only supported on the PowerPC, not the POWER. */
230#define PPC_OPERAND_CR (020)
231
232/* This operand names a register. The disassembler uses this to print
233 register names with a leading 'r'. */
234#define PPC_OPERAND_GPR (040)
235
236/* This operand names a floating point register. The disassembler
237 prints these with a leading 'f'. */
238#define PPC_OPERAND_FPR (0100)
239
240/* This operand is a relative branch displacement. The disassembler
241 prints these symbolically if possible. */
242#define PPC_OPERAND_RELATIVE (0200)
243
244/* This operand is an absolute branch address. The disassembler
245 prints these symbolically if possible. */
246#define PPC_OPERAND_ABSOLUTE (0400)
247
248/* This operand is optional, and is zero if omitted. This is used for
249 the optional BF and L fields in the comparison instructions. The
250 assembler must count the number of operands remaining on the line,
251 and the number of operands remaining for the opcode, and decide
252 whether this operand is present or not. The disassembler should
253 print this operand out only if it is not zero. */
254#define PPC_OPERAND_OPTIONAL (01000)
255
256/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
257 is omitted, then for the next operand use this operand value plus
258 1, ignoring the next operand field for the opcode. This wretched
259 hack is needed because the Power rotate instructions can take
260 either 4 or 5 operands. The disassembler should print this operand
261 out regardless of the PPC_OPERAND_OPTIONAL field. */
262#define PPC_OPERAND_NEXT (02000)
263
264/* This operand should be regarded as a negative number for the
265 purposes of overflow checking (i.e., the normal most negative
266 number is disallowed and one more than the normal most positive
267 number is allowed). This flag will only be set for a signed
268 operand. */
269#define PPC_OPERAND_NEGATIVE (04000)
270
271/* This operand names a vector unit register. The disassembler
272 prints these with a leading 'v'. */
273#define PPC_OPERAND_VR (010000)
274
275/* This operand is for the DS field in a DS form instruction. */
276#define PPC_OPERAND_DS (020000)
277
278/* This operand is for the DQ field in a DQ form instruction. */
279#define PPC_OPERAND_DQ (040000)
280
281/* The POWER and PowerPC assemblers use a few macros. We keep them
282 with the operands table for simplicity. The macro table is an
283 array of struct powerpc_macro. */
284
285struct powerpc_macro
286{
287 /* The macro name. */
288 const char *name;
289
290 /* The number of operands the macro takes. */
291 unsigned int operands;
292
293 /* One bit flags for the opcode. These are used to indicate which
294 specific processors support the instructions. The values are the
295 same as those for the struct powerpc_opcode flags field. */
296 unsigned long flags;
297
298 /* A format string to turn the macro into a normal instruction.
299 Each %N in the string is replaced with operand number N (zero
300 based). */
301 const char *format;
302};
303
304extern const struct powerpc_macro powerpc_macros[];
305extern const int powerpc_num_macros;
306
307#endif /* PPC_H */
diff --git a/arch/ppc64/xmon/privinst.h b/arch/ppc64/xmon/privinst.h
new file mode 100644
index 000000000000..183c3e400258
--- /dev/null
+++ b/arch/ppc64/xmon/privinst.h
@@ -0,0 +1,65 @@
1/*
2 * Copyright (C) 1996 Paul Mackerras.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#define GETREG(reg) \
11 static inline unsigned long get_ ## reg (void) \
12 { unsigned long ret; asm volatile ("mf" #reg " %0" : "=r" (ret) :); return ret; }
13
14#define SETREG(reg) \
15 static inline void set_ ## reg (unsigned long val) \
16 { asm volatile ("mt" #reg " %0" : : "r" (val)); }
17
18GETREG(msr)
19SETREG(msrd)
20GETREG(cr)
21
22#define GSETSPR(n, name) \
23 static inline long get_ ## name (void) \
24 { long ret; asm volatile ("mfspr %0," #n : "=r" (ret) : ); return ret; } \
25 static inline void set_ ## name (long val) \
26 { asm volatile ("mtspr " #n ",%0" : : "r" (val)); }
27
28GSETSPR(0, mq)
29GSETSPR(1, xer)
30GSETSPR(4, rtcu)
31GSETSPR(5, rtcl)
32GSETSPR(8, lr)
33GSETSPR(9, ctr)
34GSETSPR(18, dsisr)
35GSETSPR(19, dar)
36GSETSPR(22, dec)
37GSETSPR(25, sdr1)
38GSETSPR(26, srr0)
39GSETSPR(27, srr1)
40GSETSPR(272, sprg0)
41GSETSPR(273, sprg1)
42GSETSPR(274, sprg2)
43GSETSPR(275, sprg3)
44GSETSPR(282, ear)
45GSETSPR(287, pvr)
46GSETSPR(1008, hid0)
47GSETSPR(1009, hid1)
48GSETSPR(1010, iabr)
49GSETSPR(1013, dabr)
50GSETSPR(1023, pir)
51
52static inline void store_inst(void *p)
53{
54 asm volatile ("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r" (p));
55}
56
57static inline void cflush(void *p)
58{
59 asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p));
60}
61
62static inline void cinval(void *p)
63{
64 asm volatile ("dcbi 0,%0; icbi 0,%0" : : "r" (p));
65}
diff --git a/arch/ppc64/xmon/setjmp.S b/arch/ppc64/xmon/setjmp.S
new file mode 100644
index 000000000000..30ee643d557c
--- /dev/null
+++ b/arch/ppc64/xmon/setjmp.S
@@ -0,0 +1,73 @@
1/*
2 * Copyright (C) 1996 Paul Mackerras.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * NOTE: assert(sizeof(buf) > 184)
10 */
11#include <asm/processor.h>
12#include <asm/ppc_asm.h>
13
14_GLOBAL(xmon_setjmp)
15 mflr r0
16 std r0,0(r3)
17 std r1,8(r3)
18 std r2,16(r3)
19 mfcr r0
20 std r0,24(r3)
21 std r13,32(r3)
22 std r14,40(r3)
23 std r15,48(r3)
24 std r16,56(r3)
25 std r17,64(r3)
26 std r18,72(r3)
27 std r19,80(r3)
28 std r20,88(r3)
29 std r21,96(r3)
30 std r22,104(r3)
31 std r23,112(r3)
32 std r24,120(r3)
33 std r25,128(r3)
34 std r26,136(r3)
35 std r27,144(r3)
36 std r28,152(r3)
37 std r29,160(r3)
38 std r30,168(r3)
39 std r31,176(r3)
40 li r3,0
41 blr
42
43_GLOBAL(xmon_longjmp)
44 cmpdi r4,0
45 bne 1f
46 li r4,1
471: ld r13,32(r3)
48 ld r14,40(r3)
49 ld r15,48(r3)
50 ld r16,56(r3)
51 ld r17,64(r3)
52 ld r18,72(r3)
53 ld r19,80(r3)
54 ld r20,88(r3)
55 ld r21,96(r3)
56 ld r22,104(r3)
57 ld r23,112(r3)
58 ld r24,120(r3)
59 ld r25,128(r3)
60 ld r26,136(r3)
61 ld r27,144(r3)
62 ld r28,152(r3)
63 ld r29,160(r3)
64 ld r30,168(r3)
65 ld r31,176(r3)
66 ld r0,24(r3)
67 mtcrf 56,r0
68 ld r0,0(r3)
69 ld r1,8(r3)
70 ld r2,16(r3)
71 mtlr r0
72 mr r3,r4
73 blr
diff --git a/arch/ppc64/xmon/start.c b/arch/ppc64/xmon/start.c
new file mode 100644
index 000000000000..a9265bcc79b2
--- /dev/null
+++ b/arch/ppc64/xmon/start.c
@@ -0,0 +1,185 @@
1/*
2 * Copyright (C) 1996 Paul Mackerras.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#include <linux/config.h>
10#include <linux/string.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/sysrq.h>
14#include <linux/init.h>
15#include <asm/machdep.h>
16#include <asm/io.h>
17#include <asm/page.h>
18#include <asm/prom.h>
19#include <asm/processor.h>
20#include <asm/udbg.h>
21#include <asm/system.h>
22#include "nonstdio.h"
23
24#ifdef CONFIG_MAGIC_SYSRQ
25
26static void sysrq_handle_xmon(int key, struct pt_regs *pt_regs,
27 struct tty_struct *tty)
28{
29 /* ensure xmon is enabled */
30 xmon_init();
31 debugger(pt_regs);
32}
33
34static struct sysrq_key_op sysrq_xmon_op =
35{
36 .handler = sysrq_handle_xmon,
37 .help_msg = "Xmon",
38 .action_msg = "Entering xmon",
39};
40
41static int __init setup_xmon_sysrq(void)
42{
43 register_sysrq_key('x', &sysrq_xmon_op);
44 return 0;
45}
46__initcall(setup_xmon_sysrq);
47#endif /* CONFIG_MAGIC_SYSRQ */
48
49int
50xmon_write(void *handle, void *ptr, int nb)
51{
52 return udbg_write(ptr, nb);
53}
54
55int
56xmon_read(void *handle, void *ptr, int nb)
57{
58 return udbg_read(ptr, nb);
59}
60
61int
62xmon_read_poll(void)
63{
64 return udbg_getc_poll();
65}
66
67FILE *xmon_stdin;
68FILE *xmon_stdout;
69
70int
71xmon_putc(int c, void *f)
72{
73 char ch = c;
74
75 if (c == '\n')
76 xmon_putc('\r', f);
77 return xmon_write(f, &ch, 1) == 1? c: -1;
78}
79
80int
81xmon_putchar(int c)
82{
83 return xmon_putc(c, xmon_stdout);
84}
85
86int
87xmon_fputs(char *str, void *f)
88{
89 int n = strlen(str);
90
91 return xmon_write(f, str, n) == n? 0: -1;
92}
93
94int
95xmon_readchar(void)
96{
97 char ch;
98
99 for (;;) {
100 switch (xmon_read(xmon_stdin, &ch, 1)) {
101 case 1:
102 return ch;
103 case -1:
104 xmon_printf("read(stdin) returned -1\r\n", 0, 0);
105 return -1;
106 }
107 }
108}
109
110static char line[256];
111static char *lineptr;
112static int lineleft;
113
114int
115xmon_getchar(void)
116{
117 int c;
118
119 if (lineleft == 0) {
120 lineptr = line;
121 for (;;) {
122 c = xmon_readchar();
123 if (c == -1 || c == 4)
124 break;
125 if (c == '\r' || c == '\n') {
126 *lineptr++ = '\n';
127 xmon_putchar('\n');
128 break;
129 }
130 switch (c) {
131 case 0177:
132 case '\b':
133 if (lineptr > line) {
134 xmon_putchar('\b');
135 xmon_putchar(' ');
136 xmon_putchar('\b');
137 --lineptr;
138 }
139 break;
140 case 'U' & 0x1F:
141 while (lineptr > line) {
142 xmon_putchar('\b');
143 xmon_putchar(' ');
144 xmon_putchar('\b');
145 --lineptr;
146 }
147 break;
148 default:
149 if (lineptr >= &line[sizeof(line) - 1])
150 xmon_putchar('\a');
151 else {
152 xmon_putchar(c);
153 *lineptr++ = c;
154 }
155 }
156 }
157 lineleft = lineptr - line;
158 lineptr = line;
159 }
160 if (lineleft == 0)
161 return -1;
162 --lineleft;
163 return *lineptr++;
164}
165
166char *
167xmon_fgets(char *str, int nb, void *f)
168{
169 char *p;
170 int c;
171
172 for (p = str; p < str + nb - 1; ) {
173 c = xmon_getchar();
174 if (c == -1) {
175 if (p == str)
176 return NULL;
177 break;
178 }
179 *p++ = c;
180 if (c == '\n')
181 break;
182 }
183 *p = 0;
184 return str;
185}
diff --git a/arch/ppc64/xmon/subr_prf.c b/arch/ppc64/xmon/subr_prf.c
new file mode 100644
index 000000000000..5242bd7d0959
--- /dev/null
+++ b/arch/ppc64/xmon/subr_prf.c
@@ -0,0 +1,55 @@
1/*
2 * Written by Cort Dougan to replace the version originally used
3 * by Paul Mackerras, which came from NetBSD and thus had copyright
4 * conflicts with Linux.
5 *
6 * This file makes liberal use of the standard linux utility
7 * routines to reduce the size of the binary. We assume we can
8 * trust some parts of Linux inside the debugger.
9 * -- Cort (cort@cs.nmt.edu)
10 *
11 * Copyright (C) 1999 Cort Dougan.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/string.h>
21#include <stdarg.h>
22#include "nonstdio.h"
23
24extern int xmon_write(void *, void *, int);
25
26void
27xmon_vfprintf(void *f, const char *fmt, va_list ap)
28{
29 static char xmon_buf[2048];
30 int n;
31
32 n = vsprintf(xmon_buf, fmt, ap);
33 xmon_write(f, xmon_buf, n);
34}
35
36void
37xmon_printf(const char *fmt, ...)
38{
39 va_list ap;
40
41 va_start(ap, fmt);
42 xmon_vfprintf(stdout, fmt, ap);
43 va_end(ap);
44}
45
46void
47xmon_fprintf(void *f, const char *fmt, ...)
48{
49 va_list ap;
50
51 va_start(ap, fmt);
52 xmon_vfprintf(f, fmt, ap);
53 va_end(ap);
54}
55
diff --git a/arch/ppc64/xmon/xmon.c b/arch/ppc64/xmon/xmon.c
new file mode 100644
index 000000000000..3c0ccb2623ae
--- /dev/null
+++ b/arch/ppc64/xmon/xmon.c
@@ -0,0 +1,2506 @@
1/*
2 * Routines providing a simple monitor for use on the PowerMac.
3 *
4 * Copyright (C) 1996 Paul Mackerras.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/config.h>
12#include <linux/errno.h>
13#include <linux/sched.h>
14#include <linux/smp.h>
15#include <linux/mm.h>
16#include <linux/reboot.h>
17#include <linux/delay.h>
18#include <linux/kallsyms.h>
19#include <linux/cpumask.h>
20
21#include <asm/ptrace.h>
22#include <asm/string.h>
23#include <asm/prom.h>
24#include <asm/machdep.h>
25#include <asm/processor.h>
26#include <asm/pgtable.h>
27#include <asm/mmu.h>
28#include <asm/mmu_context.h>
29#include <asm/paca.h>
30#include <asm/ppcdebug.h>
31#include <asm/cputable.h>
32#include <asm/rtas.h>
33#include <asm/sstep.h>
34#include <asm/bug.h>
35#include <asm/hvcall.h>
36
37#include "nonstdio.h"
38#include "privinst.h"
39
40#define scanhex xmon_scanhex
41#define skipbl xmon_skipbl
42
43#ifdef CONFIG_SMP
44cpumask_t cpus_in_xmon = CPU_MASK_NONE;
45static unsigned long xmon_taken = 1;
46static int xmon_owner;
47static int xmon_gate;
48#endif /* CONFIG_SMP */
49
50static unsigned long in_xmon = 0;
51
52static unsigned long adrs;
53static int size = 1;
54#define MAX_DUMP (128 * 1024)
55static unsigned long ndump = 64;
56static unsigned long nidump = 16;
57static unsigned long ncsum = 4096;
58static int termch;
59static char tmpstr[128];
60
61#define JMP_BUF_LEN (184/sizeof(long))
62static long bus_error_jmp[JMP_BUF_LEN];
63static int catch_memory_errors;
64static long *xmon_fault_jmp[NR_CPUS];
65#define setjmp xmon_setjmp
66#define longjmp xmon_longjmp
67
68/* Breakpoint stuff */
69struct bpt {
70 unsigned long address;
71 unsigned int instr[2];
72 atomic_t ref_count;
73 int enabled;
74 unsigned long pad;
75};
76
77/* Bits in bpt.enabled */
78#define BP_IABR_TE 1 /* IABR translation enabled */
79#define BP_IABR 2
80#define BP_TRAP 8
81#define BP_DABR 0x10
82
83#define NBPTS 256
84static struct bpt bpts[NBPTS];
85static struct bpt dabr;
86static struct bpt *iabr;
87static unsigned bpinstr = 0x7fe00008; /* trap */
88
89#define BP_NUM(bp) ((bp) - bpts + 1)
90
91/* Prototypes */
92static int cmds(struct pt_regs *);
93static int mread(unsigned long, void *, int);
94static int mwrite(unsigned long, void *, int);
95static int handle_fault(struct pt_regs *);
96static void byterev(unsigned char *, int);
97static void memex(void);
98static int bsesc(void);
99static void dump(void);
100static void prdump(unsigned long, long);
101static int ppc_inst_dump(unsigned long, long, int);
102void print_address(unsigned long);
103static void backtrace(struct pt_regs *);
104static void excprint(struct pt_regs *);
105static void prregs(struct pt_regs *);
106static void memops(int);
107static void memlocate(void);
108static void memzcan(void);
109static void memdiffs(unsigned char *, unsigned char *, unsigned, unsigned);
110int skipbl(void);
111int scanhex(unsigned long *valp);
112static void scannl(void);
113static int hexdigit(int);
114void getstring(char *, int);
115static void flush_input(void);
116static int inchar(void);
117static void take_input(char *);
118static unsigned long read_spr(int);
119static void write_spr(int, unsigned long);
120static void super_regs(void);
121static void remove_bpts(void);
122static void insert_bpts(void);
123static void remove_cpu_bpts(void);
124static void insert_cpu_bpts(void);
125static struct bpt *at_breakpoint(unsigned long pc);
126static struct bpt *in_breakpoint_table(unsigned long pc, unsigned long *offp);
127static int do_step(struct pt_regs *);
128static void bpt_cmds(void);
129static void cacheflush(void);
130static int cpu_cmd(void);
131static void csum(void);
132static void bootcmds(void);
133void dump_segments(void);
134static void symbol_lookup(void);
135static void xmon_print_symbol(unsigned long address, const char *mid,
136 const char *after);
137static const char *getvecname(unsigned long vec);
138
139static void debug_trace(void);
140
141extern int print_insn_powerpc(unsigned long, unsigned long, int);
142extern void printf(const char *fmt, ...);
143extern void xmon_vfprintf(void *f, const char *fmt, va_list ap);
144extern int xmon_putc(int c, void *f);
145extern int putchar(int ch);
146extern int xmon_read_poll(void);
147extern int setjmp(long *);
148extern void longjmp(long *, int);
149extern unsigned long _ASR;
150
151#define GETWORD(v) (((v)[0] << 24) + ((v)[1] << 16) + ((v)[2] << 8) + (v)[3])
152
153#define isxdigit(c) (('0' <= (c) && (c) <= '9') \
154 || ('a' <= (c) && (c) <= 'f') \
155 || ('A' <= (c) && (c) <= 'F'))
156#define isalnum(c) (('0' <= (c) && (c) <= '9') \
157 || ('a' <= (c) && (c) <= 'z') \
158 || ('A' <= (c) && (c) <= 'Z'))
159#define isspace(c) (c == ' ' || c == '\t' || c == 10 || c == 13 || c == 0)
160
161static char *help_string = "\
162Commands:\n\
163 b show breakpoints\n\
164 bd set data breakpoint\n\
165 bi set instruction breakpoint\n\
166 bc clear breakpoint\n"
167#ifdef CONFIG_SMP
168 "\
169 c print cpus stopped in xmon\n\
170 c# try to switch to cpu number h (in hex)\n"
171#endif
172 "\
173 C checksum\n\
174 d dump bytes\n\
175 di dump instructions\n\
176 df dump float values\n\
177 dd dump double values\n\
178 e print exception information\n\
179 f flush cache\n\
180 la lookup symbol+offset of specified address\n\
181 ls lookup address of specified symbol\n\
182 m examine/change memory\n\
183 mm move a block of memory\n\
184 ms set a block of memory\n\
185 md compare two blocks of memory\n\
186 ml locate a block of memory\n\
187 mz zero a block of memory\n\
188 mi show information about memory allocation\n\
189 p show the task list\n\
190 r print registers\n\
191 s single step\n\
192 S print special registers\n\
193 t print backtrace\n\
194 T Enable/Disable PPCDBG flags\n\
195 x exit monitor and recover\n\
196 X exit monitor and dont recover\n\
197 u dump segment table or SLB\n\
198 ? help\n"
199 "\
200 zr reboot\n\
201 zh halt\n"
202;
203
204static struct pt_regs *xmon_regs;
205
206extern inline void sync(void)
207{
208 asm volatile("sync; isync");
209}
210
211/* (Ref: 64-bit PowerPC ELF ABI Spplement; Ian Lance Taylor, Zembu Labs).
212 A PPC stack frame looks like this:
213
214 High Address
215 Back Chain
216 FP reg save area
217 GP reg save area
218 Local var space
219 Parameter save area (SP+48)
220 TOC save area (SP+40)
221 link editor doubleword (SP+32)
222 compiler doubleword (SP+24)
223 LR save (SP+16)
224 CR save (SP+8)
225 Back Chain (SP+0)
226
227 Note that the LR (ret addr) may not be saved in the current frame if
228 no functions have been called from the current function.
229 */
230
231/*
232 * Disable surveillance (the service processor watchdog function)
233 * while we are in xmon.
234 * XXX we should re-enable it when we leave. :)
235 */
236#define SURVEILLANCE_TOKEN 9000
237
238static inline void disable_surveillance(void)
239{
240#ifdef CONFIG_PPC_PSERIES
241 /* Since this can't be a module, args should end up below 4GB. */
242 static struct rtas_args args;
243
244 /*
245 * At this point we have got all the cpus we can into
246 * xmon, so there is hopefully no other cpu calling RTAS
247 * at the moment, even though we don't take rtas.lock.
248 * If we did try to take rtas.lock there would be a
249 * real possibility of deadlock.
250 */
251 args.token = rtas_token("set-indicator");
252 if (args.token == RTAS_UNKNOWN_SERVICE)
253 return;
254 args.nargs = 3;
255 args.nret = 1;
256 args.rets = &args.args[3];
257 args.args[0] = SURVEILLANCE_TOKEN;
258 args.args[1] = 0;
259 args.args[2] = 0;
260 enter_rtas(__pa(&args));
261#endif /* CONFIG_PPC_PSERIES */
262}
263
264#ifdef CONFIG_SMP
265static int xmon_speaker;
266
267static void get_output_lock(void)
268{
269 int me = smp_processor_id() + 0x100;
270 int last_speaker = 0, prev;
271 long timeout;
272
273 if (xmon_speaker == me)
274 return;
275 for (;;) {
276 if (xmon_speaker == 0) {
277 last_speaker = cmpxchg(&xmon_speaker, 0, me);
278 if (last_speaker == 0)
279 return;
280 }
281 timeout = 10000000;
282 while (xmon_speaker == last_speaker) {
283 if (--timeout > 0)
284 continue;
285 /* hostile takeover */
286 prev = cmpxchg(&xmon_speaker, last_speaker, me);
287 if (prev == last_speaker)
288 return;
289 break;
290 }
291 }
292}
293
294static void release_output_lock(void)
295{
296 xmon_speaker = 0;
297}
298#endif
299
300int xmon_core(struct pt_regs *regs, int fromipi)
301{
302 int cmd = 0;
303 unsigned long msr;
304 struct bpt *bp;
305 long recurse_jmp[JMP_BUF_LEN];
306 unsigned long offset;
307#ifdef CONFIG_SMP
308 int cpu;
309 int secondary;
310 unsigned long timeout;
311#endif
312
313 msr = get_msr();
314 set_msrd(msr & ~MSR_EE); /* disable interrupts */
315
316 bp = in_breakpoint_table(regs->nip, &offset);
317 if (bp != NULL) {
318 regs->nip = bp->address + offset;
319 atomic_dec(&bp->ref_count);
320 }
321
322 remove_cpu_bpts();
323
324#ifdef CONFIG_SMP
325 cpu = smp_processor_id();
326 if (cpu_isset(cpu, cpus_in_xmon)) {
327 get_output_lock();
328 excprint(regs);
329 printf("cpu 0x%x: Exception %lx %s in xmon, "
330 "returning to main loop\n",
331 cpu, regs->trap, getvecname(TRAP(regs)));
332 longjmp(xmon_fault_jmp[cpu], 1);
333 }
334
335 if (setjmp(recurse_jmp) != 0) {
336 if (!in_xmon || !xmon_gate) {
337 printf("xmon: WARNING: bad recursive fault "
338 "on cpu 0x%x\n", cpu);
339 goto waiting;
340 }
341 secondary = !(xmon_taken && cpu == xmon_owner);
342 goto cmdloop;
343 }
344
345 xmon_fault_jmp[cpu] = recurse_jmp;
346 cpu_set(cpu, cpus_in_xmon);
347
348 bp = NULL;
349 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) == (MSR_IR|MSR_SF))
350 bp = at_breakpoint(regs->nip);
351 if (bp || (regs->msr & MSR_RI) == 0)
352 fromipi = 0;
353
354 if (!fromipi) {
355 get_output_lock();
356 excprint(regs);
357 if (bp) {
358 printf("cpu 0x%x stopped at breakpoint 0x%x (",
359 cpu, BP_NUM(bp));
360 xmon_print_symbol(regs->nip, " ", ")\n");
361 }
362 if ((regs->msr & MSR_RI) == 0)
363 printf("WARNING: exception is not recoverable, "
364 "can't continue\n");
365 release_output_lock();
366 }
367
368 waiting:
369 secondary = 1;
370 while (secondary && !xmon_gate) {
371 if (in_xmon == 0) {
372 if (fromipi)
373 goto leave;
374 secondary = test_and_set_bit(0, &in_xmon);
375 }
376 barrier();
377 }
378
379 if (!secondary && !xmon_gate) {
380 /* we are the first cpu to come in */
381 /* interrupt other cpu(s) */
382 int ncpus = num_online_cpus();
383
384 xmon_owner = cpu;
385 mb();
386 if (ncpus > 1) {
387 smp_send_debugger_break(MSG_ALL_BUT_SELF);
388 /* wait for other cpus to come in */
389 for (timeout = 100000000; timeout != 0; --timeout) {
390 if (cpus_weight(cpus_in_xmon) >= ncpus)
391 break;
392 barrier();
393 }
394 }
395 remove_bpts();
396 disable_surveillance();
397 /* for breakpoint or single step, print the current instr. */
398 if (bp || TRAP(regs) == 0xd00)
399 ppc_inst_dump(regs->nip, 1, 0);
400 printf("enter ? for help\n");
401 mb();
402 xmon_gate = 1;
403 barrier();
404 }
405
406 cmdloop:
407 while (in_xmon) {
408 if (secondary) {
409 if (cpu == xmon_owner) {
410 if (!test_and_set_bit(0, &xmon_taken)) {
411 secondary = 0;
412 continue;
413 }
414 /* missed it */
415 while (cpu == xmon_owner)
416 barrier();
417 }
418 barrier();
419 } else {
420 cmd = cmds(regs);
421 if (cmd != 0) {
422 /* exiting xmon */
423 insert_bpts();
424 xmon_gate = 0;
425 wmb();
426 in_xmon = 0;
427 break;
428 }
429 /* have switched to some other cpu */
430 secondary = 1;
431 }
432 }
433 leave:
434 cpu_clear(cpu, cpus_in_xmon);
435 xmon_fault_jmp[cpu] = NULL;
436
437#else
438 /* UP is simple... */
439 if (in_xmon) {
440 printf("Exception %lx %s in xmon, returning to main loop\n",
441 regs->trap, getvecname(TRAP(regs)));
442 longjmp(xmon_fault_jmp[0], 1);
443 }
444 if (setjmp(recurse_jmp) == 0) {
445 xmon_fault_jmp[0] = recurse_jmp;
446 in_xmon = 1;
447
448 excprint(regs);
449 bp = at_breakpoint(regs->nip);
450 if (bp) {
451 printf("Stopped at breakpoint %x (", BP_NUM(bp));
452 xmon_print_symbol(regs->nip, " ", ")\n");
453 }
454 if ((regs->msr & MSR_RI) == 0)
455 printf("WARNING: exception is not recoverable, "
456 "can't continue\n");
457 remove_bpts();
458 disable_surveillance();
459 /* for breakpoint or single step, print the current instr. */
460 if (bp || TRAP(regs) == 0xd00)
461 ppc_inst_dump(regs->nip, 1, 0);
462 printf("enter ? for help\n");
463 }
464
465 cmd = cmds(regs);
466
467 insert_bpts();
468 in_xmon = 0;
469#endif
470
471 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) == (MSR_IR|MSR_SF)) {
472 bp = at_breakpoint(regs->nip);
473 if (bp != NULL) {
474 int stepped = emulate_step(regs, bp->instr[0]);
475 if (stepped == 0) {
476 regs->nip = (unsigned long) &bp->instr[0];
477 atomic_inc(&bp->ref_count);
478 } else if (stepped < 0) {
479 printf("Couldn't single-step %s instruction\n",
480 (IS_RFID(bp->instr[0])? "rfid": "mtmsrd"));
481 }
482 }
483 }
484
485 insert_cpu_bpts();
486
487 set_msrd(msr); /* restore interrupt enable */
488
489 return cmd != 'X';
490}
491
492int xmon(struct pt_regs *excp)
493{
494 struct pt_regs regs;
495
496 if (excp == NULL) {
497 /* Ok, grab regs as they are now.
498 This won't do a particularily good job because the
499 prologue has already been executed.
500 ToDo: We could reach back into the callers save
501 area to do a better job of representing the
502 caller's state.
503 */
504 asm volatile ("std 0,0(%0)\n\
505 std 1,8(%0)\n\
506 std 2,16(%0)\n\
507 std 3,24(%0)\n\
508 std 4,32(%0)\n\
509 std 5,40(%0)\n\
510 std 6,48(%0)\n\
511 std 7,56(%0)\n\
512 std 8,64(%0)\n\
513 std 9,72(%0)\n\
514 std 10,80(%0)\n\
515 std 11,88(%0)\n\
516 std 12,96(%0)\n\
517 std 13,104(%0)\n\
518 std 14,112(%0)\n\
519 std 15,120(%0)\n\
520 std 16,128(%0)\n\
521 std 17,136(%0)\n\
522 std 18,144(%0)\n\
523 std 19,152(%0)\n\
524 std 20,160(%0)\n\
525 std 21,168(%0)\n\
526 std 22,176(%0)\n\
527 std 23,184(%0)\n\
528 std 24,192(%0)\n\
529 std 25,200(%0)\n\
530 std 26,208(%0)\n\
531 std 27,216(%0)\n\
532 std 28,224(%0)\n\
533 std 29,232(%0)\n\
534 std 30,240(%0)\n\
535 std 31,248(%0)" : : "b" (&regs));
536
537 regs.nip = regs.link = ((unsigned long *)(regs.gpr[1]))[2];
538 regs.msr = get_msr();
539 regs.ctr = get_ctr();
540 regs.xer = get_xer();
541 regs.ccr = get_cr();
542 regs.trap = 0;
543 excp = &regs;
544 }
545 return xmon_core(excp, 0);
546}
547
548int xmon_bpt(struct pt_regs *regs)
549{
550 struct bpt *bp;
551 unsigned long offset;
552
553 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) != (MSR_IR|MSR_SF))
554 return 0;
555
556 /* Are we at the trap at bp->instr[1] for some bp? */
557 bp = in_breakpoint_table(regs->nip, &offset);
558 if (bp != NULL && offset == 4) {
559 regs->nip = bp->address + 4;
560 atomic_dec(&bp->ref_count);
561 return 1;
562 }
563
564 /* Are we at a breakpoint? */
565 bp = at_breakpoint(regs->nip);
566 if (!bp)
567 return 0;
568
569 xmon_core(regs, 0);
570
571 return 1;
572}
573
574int xmon_sstep(struct pt_regs *regs)
575{
576 if (user_mode(regs))
577 return 0;
578 xmon_core(regs, 0);
579 return 1;
580}
581
582int xmon_dabr_match(struct pt_regs *regs)
583{
584 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) != (MSR_IR|MSR_SF))
585 return 0;
586 xmon_core(regs, 0);
587 return 1;
588}
589
590int xmon_iabr_match(struct pt_regs *regs)
591{
592 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) != (MSR_IR|MSR_SF))
593 return 0;
594 if (iabr == 0)
595 return 0;
596 xmon_core(regs, 0);
597 return 1;
598}
599
600int xmon_ipi(struct pt_regs *regs)
601{
602#ifdef CONFIG_SMP
603 if (in_xmon && !cpu_isset(smp_processor_id(), cpus_in_xmon))
604 xmon_core(regs, 1);
605#endif
606 return 0;
607}
608
609int xmon_fault_handler(struct pt_regs *regs)
610{
611 struct bpt *bp;
612 unsigned long offset;
613
614 if (in_xmon && catch_memory_errors)
615 handle_fault(regs); /* doesn't return */
616
617 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) == (MSR_IR|MSR_SF)) {
618 bp = in_breakpoint_table(regs->nip, &offset);
619 if (bp != NULL) {
620 regs->nip = bp->address + offset;
621 atomic_dec(&bp->ref_count);
622 }
623 }
624
625 return 0;
626}
627
628/* On systems with a hypervisor, we can't set the DABR
629 (data address breakpoint register) directly. */
630static void set_controlled_dabr(unsigned long val)
631{
632#ifdef CONFIG_PPC_PSERIES
633 if (systemcfg->platform == PLATFORM_PSERIES_LPAR) {
634 int rc = plpar_hcall_norets(H_SET_DABR, val);
635 if (rc != H_Success)
636 xmon_printf("Warning: setting DABR failed (%d)\n", rc);
637 } else
638#endif
639 set_dabr(val);
640}
641
642static struct bpt *at_breakpoint(unsigned long pc)
643{
644 int i;
645 struct bpt *bp;
646
647 bp = bpts;
648 for (i = 0; i < NBPTS; ++i, ++bp)
649 if (bp->enabled && pc == bp->address)
650 return bp;
651 return NULL;
652}
653
654static struct bpt *in_breakpoint_table(unsigned long nip, unsigned long *offp)
655{
656 unsigned long off;
657
658 off = nip - (unsigned long) bpts;
659 if (off >= sizeof(bpts))
660 return NULL;
661 off %= sizeof(struct bpt);
662 if (off != offsetof(struct bpt, instr[0])
663 && off != offsetof(struct bpt, instr[1]))
664 return NULL;
665 *offp = off - offsetof(struct bpt, instr[0]);
666 return (struct bpt *) (nip - off);
667}
668
669static struct bpt *new_breakpoint(unsigned long a)
670{
671 struct bpt *bp;
672
673 a &= ~3UL;
674 bp = at_breakpoint(a);
675 if (bp)
676 return bp;
677
678 for (bp = bpts; bp < &bpts[NBPTS]; ++bp) {
679 if (!bp->enabled && atomic_read(&bp->ref_count) == 0) {
680 bp->address = a;
681 bp->instr[1] = bpinstr;
682 store_inst(&bp->instr[1]);
683 return bp;
684 }
685 }
686
687 printf("Sorry, no free breakpoints. Please clear one first.\n");
688 return NULL;
689}
690
691static void insert_bpts(void)
692{
693 int i;
694 struct bpt *bp;
695
696 bp = bpts;
697 for (i = 0; i < NBPTS; ++i, ++bp) {
698 if ((bp->enabled & (BP_TRAP|BP_IABR)) == 0)
699 continue;
700 if (mread(bp->address, &bp->instr[0], 4) != 4) {
701 printf("Couldn't read instruction at %lx, "
702 "disabling breakpoint there\n", bp->address);
703 bp->enabled = 0;
704 continue;
705 }
706 if (IS_MTMSRD(bp->instr[0]) || IS_RFID(bp->instr[0])) {
707 printf("Breakpoint at %lx is on an mtmsrd or rfid "
708 "instruction, disabling it\n", bp->address);
709 bp->enabled = 0;
710 continue;
711 }
712 store_inst(&bp->instr[0]);
713 if (bp->enabled & BP_IABR)
714 continue;
715 if (mwrite(bp->address, &bpinstr, 4) != 4) {
716 printf("Couldn't write instruction at %lx, "
717 "disabling breakpoint there\n", bp->address);
718 bp->enabled &= ~BP_TRAP;
719 continue;
720 }
721 store_inst((void *)bp->address);
722 }
723}
724
725static void insert_cpu_bpts(void)
726{
727 if (dabr.enabled)
728 set_controlled_dabr(dabr.address | (dabr.enabled & 7));
729 if (iabr && cpu_has_feature(CPU_FTR_IABR))
730 set_iabr(iabr->address
731 | (iabr->enabled & (BP_IABR|BP_IABR_TE)));
732}
733
734static void remove_bpts(void)
735{
736 int i;
737 struct bpt *bp;
738 unsigned instr;
739
740 bp = bpts;
741 for (i = 0; i < NBPTS; ++i, ++bp) {
742 if ((bp->enabled & (BP_TRAP|BP_IABR)) != BP_TRAP)
743 continue;
744 if (mread(bp->address, &instr, 4) == 4
745 && instr == bpinstr
746 && mwrite(bp->address, &bp->instr, 4) != 4)
747 printf("Couldn't remove breakpoint at %lx\n",
748 bp->address);
749 else
750 store_inst((void *)bp->address);
751 }
752}
753
754static void remove_cpu_bpts(void)
755{
756 set_controlled_dabr(0);
757 if (cpu_has_feature(CPU_FTR_IABR))
758 set_iabr(0);
759}
760
761/* Command interpreting routine */
762static char *last_cmd;
763
764static int
765cmds(struct pt_regs *excp)
766{
767 int cmd = 0;
768
769 last_cmd = NULL;
770 xmon_regs = excp;
771 for(;;) {
772#ifdef CONFIG_SMP
773 printf("%x:", smp_processor_id());
774#endif /* CONFIG_SMP */
775 printf("mon> ");
776 fflush(stdout);
777 flush_input();
778 termch = 0;
779 cmd = skipbl();
780 if( cmd == '\n' ) {
781 if (last_cmd == NULL)
782 continue;
783 take_input(last_cmd);
784 last_cmd = NULL;
785 cmd = inchar();
786 }
787 switch (cmd) {
788 case 'm':
789 cmd = inchar();
790 switch (cmd) {
791 case 'm':
792 case 's':
793 case 'd':
794 memops(cmd);
795 break;
796 case 'l':
797 memlocate();
798 break;
799 case 'z':
800 memzcan();
801 break;
802 case 'i':
803 show_mem();
804 break;
805 default:
806 termch = cmd;
807 memex();
808 }
809 break;
810 case 'd':
811 dump();
812 break;
813 case 'l':
814 symbol_lookup();
815 break;
816 case 'r':
817 prregs(excp); /* print regs */
818 break;
819 case 'e':
820 excprint(excp);
821 break;
822 case 'S':
823 super_regs();
824 break;
825 case 't':
826 backtrace(excp);
827 break;
828 case 'f':
829 cacheflush();
830 break;
831 case 's':
832 if (do_step(excp))
833 return cmd;
834 break;
835 case 'x':
836 case 'X':
837 case EOF:
838 return cmd;
839 case '?':
840 printf(help_string);
841 break;
842 case 'p':
843 show_state();
844 break;
845 case 'b':
846 bpt_cmds();
847 break;
848 case 'C':
849 csum();
850 break;
851 case 'c':
852 if (cpu_cmd())
853 return 0;
854 break;
855 case 'z':
856 bootcmds();
857 break;
858 case 'T':
859 debug_trace();
860 break;
861 case 'u':
862 dump_segments();
863 break;
864 default:
865 printf("Unrecognized command: ");
866 do {
867 if (' ' < cmd && cmd <= '~')
868 putchar(cmd);
869 else
870 printf("\\x%x", cmd);
871 cmd = inchar();
872 } while (cmd != '\n');
873 printf(" (type ? for help)\n");
874 break;
875 }
876 }
877}
878
879/*
880 * Step a single instruction.
881 * Some instructions we emulate, others we execute with MSR_SE set.
882 */
883static int do_step(struct pt_regs *regs)
884{
885 unsigned int instr;
886 int stepped;
887
888 /* check we are in 64-bit kernel mode, translation enabled */
889 if ((regs->msr & (MSR_SF|MSR_PR|MSR_IR)) == (MSR_SF|MSR_IR)) {
890 if (mread(regs->nip, &instr, 4) == 4) {
891 stepped = emulate_step(regs, instr);
892 if (stepped < 0) {
893 printf("Couldn't single-step %s instruction\n",
894 (IS_RFID(instr)? "rfid": "mtmsrd"));
895 return 0;
896 }
897 if (stepped > 0) {
898 regs->trap = 0xd00 | (regs->trap & 1);
899 printf("stepped to ");
900 xmon_print_symbol(regs->nip, " ", "\n");
901 ppc_inst_dump(regs->nip, 1, 0);
902 return 0;
903 }
904 }
905 }
906 regs->msr |= MSR_SE;
907 return 1;
908}
909
910static void bootcmds(void)
911{
912 int cmd;
913
914 cmd = inchar();
915 if (cmd == 'r')
916 ppc_md.restart(NULL);
917 else if (cmd == 'h')
918 ppc_md.halt();
919 else if (cmd == 'p')
920 ppc_md.power_off();
921}
922
923static int cpu_cmd(void)
924{
925#ifdef CONFIG_SMP
926 unsigned long cpu;
927 int timeout;
928 int count;
929
930 if (!scanhex(&cpu)) {
931 /* print cpus waiting or in xmon */
932 printf("cpus stopped:");
933 count = 0;
934 for (cpu = 0; cpu < NR_CPUS; ++cpu) {
935 if (cpu_isset(cpu, cpus_in_xmon)) {
936 if (count == 0)
937 printf(" %x", cpu);
938 ++count;
939 } else {
940 if (count > 1)
941 printf("-%x", cpu - 1);
942 count = 0;
943 }
944 }
945 if (count > 1)
946 printf("-%x", NR_CPUS - 1);
947 printf("\n");
948 return 0;
949 }
950 /* try to switch to cpu specified */
951 if (!cpu_isset(cpu, cpus_in_xmon)) {
952 printf("cpu 0x%x isn't in xmon\n", cpu);
953 return 0;
954 }
955 xmon_taken = 0;
956 mb();
957 xmon_owner = cpu;
958 timeout = 10000000;
959 while (!xmon_taken) {
960 if (--timeout == 0) {
961 if (test_and_set_bit(0, &xmon_taken))
962 break;
963 /* take control back */
964 mb();
965 xmon_owner = smp_processor_id();
966 printf("cpu %u didn't take control\n", cpu);
967 return 0;
968 }
969 barrier();
970 }
971 return 1;
972#else
973 return 0;
974#endif /* CONFIG_SMP */
975}
976
977static unsigned short fcstab[256] = {
978 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
979 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
980 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
981 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
982 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
983 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
984 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
985 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
986 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
987 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
988 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
989 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
990 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
991 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
992 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
993 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
994 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
995 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
996 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
997 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
998 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
999 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
1000 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
1001 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
1002 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
1003 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
1004 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
1005 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
1006 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
1007 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
1008 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
1009 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
1010};
1011
1012#define FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
1013
1014static void
1015csum(void)
1016{
1017 unsigned int i;
1018 unsigned short fcs;
1019 unsigned char v;
1020
1021 if (!scanhex(&adrs))
1022 return;
1023 if (!scanhex(&ncsum))
1024 return;
1025 fcs = 0xffff;
1026 for (i = 0; i < ncsum; ++i) {
1027 if (mread(adrs+i, &v, 1) == 0) {
1028 printf("csum stopped at %x\n", adrs+i);
1029 break;
1030 }
1031 fcs = FCS(fcs, v);
1032 }
1033 printf("%x\n", fcs);
1034}
1035
1036/*
1037 * Check if this is a suitable place to put a breakpoint.
1038 */
1039static long check_bp_loc(unsigned long addr)
1040{
1041 unsigned int instr;
1042
1043 addr &= ~3;
1044 if (addr < KERNELBASE) {
1045 printf("Breakpoints may only be placed at kernel addresses\n");
1046 return 0;
1047 }
1048 if (!mread(addr, &instr, sizeof(instr))) {
1049 printf("Can't read instruction at address %lx\n", addr);
1050 return 0;
1051 }
1052 if (IS_MTMSRD(instr) || IS_RFID(instr)) {
1053 printf("Breakpoints may not be placed on mtmsrd or rfid "
1054 "instructions\n");
1055 return 0;
1056 }
1057 return 1;
1058}
1059
1060static char *breakpoint_help_string =
1061 "Breakpoint command usage:\n"
1062 "b show breakpoints\n"
1063 "b <addr> [cnt] set breakpoint at given instr addr\n"
1064 "bc clear all breakpoints\n"
1065 "bc <n/addr> clear breakpoint number n or at addr\n"
1066 "bi <addr> [cnt] set hardware instr breakpoint (POWER3/RS64 only)\n"
1067 "bd <addr> [cnt] set hardware data breakpoint\n"
1068 "";
1069
1070static void
1071bpt_cmds(void)
1072{
1073 int cmd;
1074 unsigned long a;
1075 int mode, i;
1076 struct bpt *bp;
1077 const char badaddr[] = "Only kernel addresses are permitted "
1078 "for breakpoints\n";
1079
1080 cmd = inchar();
1081 switch (cmd) {
1082 case 'd': /* bd - hardware data breakpoint */
1083 mode = 7;
1084 cmd = inchar();
1085 if (cmd == 'r')
1086 mode = 5;
1087 else if (cmd == 'w')
1088 mode = 6;
1089 else
1090 termch = cmd;
1091 dabr.address = 0;
1092 dabr.enabled = 0;
1093 if (scanhex(&dabr.address)) {
1094 if (dabr.address < KERNELBASE) {
1095 printf(badaddr);
1096 break;
1097 }
1098 dabr.address &= ~7;
1099 dabr.enabled = mode | BP_DABR;
1100 }
1101 break;
1102
1103 case 'i': /* bi - hardware instr breakpoint */
1104 if (!cpu_has_feature(CPU_FTR_IABR)) {
1105 printf("Hardware instruction breakpoint "
1106 "not supported on this cpu\n");
1107 break;
1108 }
1109 if (iabr) {
1110 iabr->enabled &= ~(BP_IABR | BP_IABR_TE);
1111 iabr = NULL;
1112 }
1113 if (!scanhex(&a))
1114 break;
1115 if (!check_bp_loc(a))
1116 break;
1117 bp = new_breakpoint(a);
1118 if (bp != NULL) {
1119 bp->enabled |= BP_IABR | BP_IABR_TE;
1120 iabr = bp;
1121 }
1122 break;
1123
1124 case 'c':
1125 if (!scanhex(&a)) {
1126 /* clear all breakpoints */
1127 for (i = 0; i < NBPTS; ++i)
1128 bpts[i].enabled = 0;
1129 iabr = NULL;
1130 dabr.enabled = 0;
1131 printf("All breakpoints cleared\n");
1132 break;
1133 }
1134
1135 if (a <= NBPTS && a >= 1) {
1136 /* assume a breakpoint number */
1137 bp = &bpts[a-1]; /* bp nums are 1 based */
1138 } else {
1139 /* assume a breakpoint address */
1140 bp = at_breakpoint(a);
1141 if (bp == 0) {
1142 printf("No breakpoint at %x\n", a);
1143 break;
1144 }
1145 }
1146
1147 printf("Cleared breakpoint %x (", BP_NUM(bp));
1148 xmon_print_symbol(bp->address, " ", ")\n");
1149 bp->enabled = 0;
1150 break;
1151
1152 default:
1153 termch = cmd;
1154 cmd = skipbl();
1155 if (cmd == '?') {
1156 printf(breakpoint_help_string);
1157 break;
1158 }
1159 termch = cmd;
1160 if (!scanhex(&a)) {
1161 /* print all breakpoints */
1162 printf(" type address\n");
1163 if (dabr.enabled) {
1164 printf(" data %.16lx [", dabr.address);
1165 if (dabr.enabled & 1)
1166 printf("r");
1167 if (dabr.enabled & 2)
1168 printf("w");
1169 printf("]\n");
1170 }
1171 for (bp = bpts; bp < &bpts[NBPTS]; ++bp) {
1172 if (!bp->enabled)
1173 continue;
1174 printf("%2x %s ", BP_NUM(bp),
1175 (bp->enabled & BP_IABR)? "inst": "trap");
1176 xmon_print_symbol(bp->address, " ", "\n");
1177 }
1178 break;
1179 }
1180
1181 if (!check_bp_loc(a))
1182 break;
1183 bp = new_breakpoint(a);
1184 if (bp != NULL)
1185 bp->enabled |= BP_TRAP;
1186 break;
1187 }
1188}
1189
1190/* Very cheap human name for vector lookup. */
1191static
1192const char *getvecname(unsigned long vec)
1193{
1194 char *ret;
1195
1196 switch (vec) {
1197 case 0x100: ret = "(System Reset)"; break;
1198 case 0x200: ret = "(Machine Check)"; break;
1199 case 0x300: ret = "(Data Access)"; break;
1200 case 0x380: ret = "(Data SLB Access)"; break;
1201 case 0x400: ret = "(Instruction Access)"; break;
1202 case 0x480: ret = "(Instruction SLB Access)"; break;
1203 case 0x500: ret = "(Hardware Interrupt)"; break;
1204 case 0x600: ret = "(Alignment)"; break;
1205 case 0x700: ret = "(Program Check)"; break;
1206 case 0x800: ret = "(FPU Unavailable)"; break;
1207 case 0x900: ret = "(Decrementer)"; break;
1208 case 0xc00: ret = "(System Call)"; break;
1209 case 0xd00: ret = "(Single Step)"; break;
1210 case 0xf00: ret = "(Performance Monitor)"; break;
1211 case 0xf20: ret = "(Altivec Unavailable)"; break;
1212 case 0x1300: ret = "(Instruction Breakpoint)"; break;
1213 default: ret = "";
1214 }
1215 return ret;
1216}
1217
1218static void get_function_bounds(unsigned long pc, unsigned long *startp,
1219 unsigned long *endp)
1220{
1221 unsigned long size, offset;
1222 const char *name;
1223 char *modname;
1224
1225 *startp = *endp = 0;
1226 if (pc == 0)
1227 return;
1228 if (setjmp(bus_error_jmp) == 0) {
1229 catch_memory_errors = 1;
1230 sync();
1231 name = kallsyms_lookup(pc, &size, &offset, &modname, tmpstr);
1232 if (name != NULL) {
1233 *startp = pc - offset;
1234 *endp = pc - offset + size;
1235 }
1236 sync();
1237 }
1238 catch_memory_errors = 0;
1239}
1240
1241static int xmon_depth_to_print = 64;
1242
1243static void xmon_show_stack(unsigned long sp, unsigned long lr,
1244 unsigned long pc)
1245{
1246 unsigned long ip;
1247 unsigned long newsp;
1248 unsigned long marker;
1249 int count = 0;
1250 struct pt_regs regs;
1251
1252 do {
1253 if (sp < PAGE_OFFSET) {
1254 if (sp != 0)
1255 printf("SP (%lx) is in userspace\n", sp);
1256 break;
1257 }
1258
1259 if (!mread(sp + 16, &ip, sizeof(unsigned long))
1260 || !mread(sp, &newsp, sizeof(unsigned long))) {
1261 printf("Couldn't read stack frame at %lx\n", sp);
1262 break;
1263 }
1264
1265 /*
1266 * For the first stack frame, try to work out if
1267 * LR and/or the saved LR value in the bottommost
1268 * stack frame are valid.
1269 */
1270 if ((pc | lr) != 0) {
1271 unsigned long fnstart, fnend;
1272 unsigned long nextip;
1273 int printip = 1;
1274
1275 get_function_bounds(pc, &fnstart, &fnend);
1276 nextip = 0;
1277 if (newsp > sp)
1278 mread(newsp + 16, &nextip,
1279 sizeof(unsigned long));
1280 if (lr == ip) {
1281 if (lr < PAGE_OFFSET
1282 || (fnstart <= lr && lr < fnend))
1283 printip = 0;
1284 } else if (lr == nextip) {
1285 printip = 0;
1286 } else if (lr >= PAGE_OFFSET
1287 && !(fnstart <= lr && lr < fnend)) {
1288 printf("[link register ] ");
1289 xmon_print_symbol(lr, " ", "\n");
1290 }
1291 if (printip) {
1292 printf("[%.16lx] ", sp);
1293 xmon_print_symbol(ip, " ", " (unreliable)\n");
1294 }
1295 pc = lr = 0;
1296
1297 } else {
1298 printf("[%.16lx] ", sp);
1299 xmon_print_symbol(ip, " ", "\n");
1300 }
1301
1302 /* Look for "regshere" marker to see if this is
1303 an exception frame. */
1304 if (mread(sp + 0x60, &marker, sizeof(unsigned long))
1305 && marker == 0x7265677368657265ul) {
1306 if (mread(sp + 0x70, &regs, sizeof(regs))
1307 != sizeof(regs)) {
1308 printf("Couldn't read registers at %lx\n",
1309 sp + 0x70);
1310 break;
1311 }
1312 printf("--- Exception: %lx %s at ", regs.trap,
1313 getvecname(TRAP(&regs)));
1314 pc = regs.nip;
1315 lr = regs.link;
1316 xmon_print_symbol(pc, " ", "\n");
1317 }
1318
1319 if (newsp == 0)
1320 break;
1321
1322 sp = newsp;
1323 } while (count++ < xmon_depth_to_print);
1324}
1325
1326static void backtrace(struct pt_regs *excp)
1327{
1328 unsigned long sp;
1329
1330 if (scanhex(&sp))
1331 xmon_show_stack(sp, 0, 0);
1332 else
1333 xmon_show_stack(excp->gpr[1], excp->link, excp->nip);
1334 scannl();
1335}
1336
1337static void print_bug_trap(struct pt_regs *regs)
1338{
1339 struct bug_entry *bug;
1340 unsigned long addr;
1341
1342 if (regs->msr & MSR_PR)
1343 return; /* not in kernel */
1344 addr = regs->nip; /* address of trap instruction */
1345 if (addr < PAGE_OFFSET)
1346 return;
1347 bug = find_bug(regs->nip);
1348 if (bug == NULL)
1349 return;
1350 if (bug->line & BUG_WARNING_TRAP)
1351 return;
1352
1353 printf("kernel BUG in %s at %s:%d!\n",
1354 bug->function, bug->file, (unsigned int)bug->line);
1355}
1356
1357void excprint(struct pt_regs *fp)
1358{
1359 unsigned long trap;
1360
1361#ifdef CONFIG_SMP
1362 printf("cpu 0x%x: ", smp_processor_id());
1363#endif /* CONFIG_SMP */
1364
1365 trap = TRAP(fp);
1366 printf("Vector: %lx %s at [%lx]\n", fp->trap, getvecname(trap), fp);
1367 printf(" pc: ");
1368 xmon_print_symbol(fp->nip, ": ", "\n");
1369
1370 printf(" lr: ", fp->link);
1371 xmon_print_symbol(fp->link, ": ", "\n");
1372
1373 printf(" sp: %lx\n", fp->gpr[1]);
1374 printf(" msr: %lx\n", fp->msr);
1375
1376 if (trap == 0x300 || trap == 0x380 || trap == 0x600) {
1377 printf(" dar: %lx\n", fp->dar);
1378 if (trap != 0x380)
1379 printf(" dsisr: %lx\n", fp->dsisr);
1380 }
1381
1382 printf(" current = 0x%lx\n", current);
1383 printf(" paca = 0x%lx\n", get_paca());
1384 if (current) {
1385 printf(" pid = %ld, comm = %s\n",
1386 current->pid, current->comm);
1387 }
1388
1389 if (trap == 0x700)
1390 print_bug_trap(fp);
1391}
1392
1393void prregs(struct pt_regs *fp)
1394{
1395 int n;
1396 unsigned long base;
1397 struct pt_regs regs;
1398
1399 if (scanhex(&base)) {
1400 if (setjmp(bus_error_jmp) == 0) {
1401 catch_memory_errors = 1;
1402 sync();
1403 regs = *(struct pt_regs *)base;
1404 sync();
1405 __delay(200);
1406 } else {
1407 catch_memory_errors = 0;
1408 printf("*** Error reading registers from %.16lx\n",
1409 base);
1410 return;
1411 }
1412 catch_memory_errors = 0;
1413 fp = &regs;
1414 }
1415
1416 if (FULL_REGS(fp)) {
1417 for (n = 0; n < 16; ++n)
1418 printf("R%.2ld = %.16lx R%.2ld = %.16lx\n",
1419 n, fp->gpr[n], n+16, fp->gpr[n+16]);
1420 } else {
1421 for (n = 0; n < 7; ++n)
1422 printf("R%.2ld = %.16lx R%.2ld = %.16lx\n",
1423 n, fp->gpr[n], n+7, fp->gpr[n+7]);
1424 }
1425 printf("pc = ");
1426 xmon_print_symbol(fp->nip, " ", "\n");
1427 printf("lr = ");
1428 xmon_print_symbol(fp->link, " ", "\n");
1429 printf("msr = %.16lx cr = %.8lx\n", fp->msr, fp->ccr);
1430 printf("ctr = %.16lx xer = %.16lx trap = %8lx\n",
1431 fp->ctr, fp->xer, fp->trap);
1432}
1433
1434void cacheflush(void)
1435{
1436 int cmd;
1437 unsigned long nflush;
1438
1439 cmd = inchar();
1440 if (cmd != 'i')
1441 termch = cmd;
1442 scanhex((void *)&adrs);
1443 if (termch != '\n')
1444 termch = 0;
1445 nflush = 1;
1446 scanhex(&nflush);
1447 nflush = (nflush + L1_CACHE_BYTES - 1) / L1_CACHE_BYTES;
1448 if (setjmp(bus_error_jmp) == 0) {
1449 catch_memory_errors = 1;
1450 sync();
1451
1452 if (cmd != 'i') {
1453 for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
1454 cflush((void *) adrs);
1455 } else {
1456 for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
1457 cinval((void *) adrs);
1458 }
1459 sync();
1460 /* wait a little while to see if we get a machine check */
1461 __delay(200);
1462 }
1463 catch_memory_errors = 0;
1464}
1465
1466unsigned long
1467read_spr(int n)
1468{
1469 unsigned int instrs[2];
1470 unsigned long (*code)(void);
1471 unsigned long opd[3];
1472 unsigned long ret = -1UL;
1473
1474 instrs[0] = 0x7c6002a6 + ((n & 0x1F) << 16) + ((n & 0x3e0) << 6);
1475 instrs[1] = 0x4e800020;
1476 opd[0] = (unsigned long)instrs;
1477 opd[1] = 0;
1478 opd[2] = 0;
1479 store_inst(instrs);
1480 store_inst(instrs+1);
1481 code = (unsigned long (*)(void)) opd;
1482
1483 if (setjmp(bus_error_jmp) == 0) {
1484 catch_memory_errors = 1;
1485 sync();
1486
1487 ret = code();
1488
1489 sync();
1490 /* wait a little while to see if we get a machine check */
1491 __delay(200);
1492 n = size;
1493 }
1494
1495 return ret;
1496}
1497
1498void
1499write_spr(int n, unsigned long val)
1500{
1501 unsigned int instrs[2];
1502 unsigned long (*code)(unsigned long);
1503 unsigned long opd[3];
1504
1505 instrs[0] = 0x7c6003a6 + ((n & 0x1F) << 16) + ((n & 0x3e0) << 6);
1506 instrs[1] = 0x4e800020;
1507 opd[0] = (unsigned long)instrs;
1508 opd[1] = 0;
1509 opd[2] = 0;
1510 store_inst(instrs);
1511 store_inst(instrs+1);
1512 code = (unsigned long (*)(unsigned long)) opd;
1513
1514 if (setjmp(bus_error_jmp) == 0) {
1515 catch_memory_errors = 1;
1516 sync();
1517
1518 code(val);
1519
1520 sync();
1521 /* wait a little while to see if we get a machine check */
1522 __delay(200);
1523 n = size;
1524 }
1525}
1526
1527static unsigned long regno;
1528extern char exc_prolog;
1529extern char dec_exc;
1530
1531void
1532super_regs(void)
1533{
1534 int cmd;
1535 unsigned long val;
1536#ifdef CONFIG_PPC_ISERIES
1537 struct paca_struct *ptrPaca = NULL;
1538 struct lppaca *ptrLpPaca = NULL;
1539 struct ItLpRegSave *ptrLpRegSave = NULL;
1540#endif
1541
1542 cmd = skipbl();
1543 if (cmd == '\n') {
1544 unsigned long sp, toc;
1545 asm("mr %0,1" : "=r" (sp) :);
1546 asm("mr %0,2" : "=r" (toc) :);
1547
1548 printf("msr = %.16lx sprg0= %.16lx\n", get_msr(), get_sprg0());
1549 printf("pvr = %.16lx sprg1= %.16lx\n", get_pvr(), get_sprg1());
1550 printf("dec = %.16lx sprg2= %.16lx\n", get_dec(), get_sprg2());
1551 printf("sp = %.16lx sprg3= %.16lx\n", sp, get_sprg3());
1552 printf("toc = %.16lx dar = %.16lx\n", toc, get_dar());
1553 printf("srr0 = %.16lx srr1 = %.16lx\n", get_srr0(), get_srr1());
1554#ifdef CONFIG_PPC_ISERIES
1555 // Dump out relevant Paca data areas.
1556 printf("Paca: \n");
1557 ptrPaca = get_paca();
1558
1559 printf(" Local Processor Control Area (LpPaca): \n");
1560 ptrLpPaca = ptrPaca->lppaca_ptr;
1561 printf(" Saved Srr0=%.16lx Saved Srr1=%.16lx \n",
1562 ptrLpPaca->saved_srr0, ptrLpPaca->saved_srr1);
1563 printf(" Saved Gpr3=%.16lx Saved Gpr4=%.16lx \n",
1564 ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4);
1565 printf(" Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5);
1566
1567 printf(" Local Processor Register Save Area (LpRegSave): \n");
1568 ptrLpRegSave = ptrPaca->reg_save_ptr;
1569 printf(" Saved Sprg0=%.16lx Saved Sprg1=%.16lx \n",
1570 ptrLpRegSave->xSPRG0, ptrLpRegSave->xSPRG0);
1571 printf(" Saved Sprg2=%.16lx Saved Sprg3=%.16lx \n",
1572 ptrLpRegSave->xSPRG2, ptrLpRegSave->xSPRG3);
1573 printf(" Saved Msr =%.16lx Saved Nia =%.16lx \n",
1574 ptrLpRegSave->xMSR, ptrLpRegSave->xNIA);
1575#endif
1576
1577 return;
1578 }
1579
1580 scanhex(&regno);
1581 switch (cmd) {
1582 case 'w':
1583 val = read_spr(regno);
1584 scanhex(&val);
1585 write_spr(regno, val);
1586 /* fall through */
1587 case 'r':
1588 printf("spr %lx = %lx\n", regno, read_spr(regno));
1589 break;
1590 case 'm':
1591 val = get_msr();
1592 scanhex(&val);
1593 set_msrd(val);
1594 break;
1595 }
1596 scannl();
1597}
1598
1599/*
1600 * Stuff for reading and writing memory safely
1601 */
1602int
1603mread(unsigned long adrs, void *buf, int size)
1604{
1605 volatile int n;
1606 char *p, *q;
1607
1608 n = 0;
1609 if (setjmp(bus_error_jmp) == 0) {
1610 catch_memory_errors = 1;
1611 sync();
1612 p = (char *)adrs;
1613 q = (char *)buf;
1614 switch (size) {
1615 case 2:
1616 *(short *)q = *(short *)p;
1617 break;
1618 case 4:
1619 *(int *)q = *(int *)p;
1620 break;
1621 case 8:
1622 *(long *)q = *(long *)p;
1623 break;
1624 default:
1625 for( ; n < size; ++n) {
1626 *q++ = *p++;
1627 sync();
1628 }
1629 }
1630 sync();
1631 /* wait a little while to see if we get a machine check */
1632 __delay(200);
1633 n = size;
1634 }
1635 catch_memory_errors = 0;
1636 return n;
1637}
1638
1639int
1640mwrite(unsigned long adrs, void *buf, int size)
1641{
1642 volatile int n;
1643 char *p, *q;
1644
1645 n = 0;
1646 if (setjmp(bus_error_jmp) == 0) {
1647 catch_memory_errors = 1;
1648 sync();
1649 p = (char *) adrs;
1650 q = (char *) buf;
1651 switch (size) {
1652 case 2:
1653 *(short *)p = *(short *)q;
1654 break;
1655 case 4:
1656 *(int *)p = *(int *)q;
1657 break;
1658 case 8:
1659 *(long *)p = *(long *)q;
1660 break;
1661 default:
1662 for ( ; n < size; ++n) {
1663 *p++ = *q++;
1664 sync();
1665 }
1666 }
1667 sync();
1668 /* wait a little while to see if we get a machine check */
1669 __delay(200);
1670 n = size;
1671 } else {
1672 printf("*** Error writing address %x\n", adrs + n);
1673 }
1674 catch_memory_errors = 0;
1675 return n;
1676}
1677
1678static int fault_type;
1679static char *fault_chars[] = { "--", "**", "##" };
1680
1681static int
1682handle_fault(struct pt_regs *regs)
1683{
1684 switch (TRAP(regs)) {
1685 case 0x200:
1686 fault_type = 0;
1687 break;
1688 case 0x300:
1689 case 0x380:
1690 fault_type = 1;
1691 break;
1692 default:
1693 fault_type = 2;
1694 }
1695
1696 longjmp(bus_error_jmp, 1);
1697
1698 return 0;
1699}
1700
1701#define SWAP(a, b, t) ((t) = (a), (a) = (b), (b) = (t))
1702
1703void
1704byterev(unsigned char *val, int size)
1705{
1706 int t;
1707
1708 switch (size) {
1709 case 2:
1710 SWAP(val[0], val[1], t);
1711 break;
1712 case 4:
1713 SWAP(val[0], val[3], t);
1714 SWAP(val[1], val[2], t);
1715 break;
1716 case 8: /* is there really any use for this? */
1717 SWAP(val[0], val[7], t);
1718 SWAP(val[1], val[6], t);
1719 SWAP(val[2], val[5], t);
1720 SWAP(val[3], val[4], t);
1721 break;
1722 }
1723}
1724
1725static int brev;
1726static int mnoread;
1727
1728static char *memex_help_string =
1729 "Memory examine command usage:\n"
1730 "m [addr] [flags] examine/change memory\n"
1731 " addr is optional. will start where left off.\n"
1732 " flags may include chars from this set:\n"
1733 " b modify by bytes (default)\n"
1734 " w modify by words (2 byte)\n"
1735 " l modify by longs (4 byte)\n"
1736 " d modify by doubleword (8 byte)\n"
1737 " r toggle reverse byte order mode\n"
1738 " n do not read memory (for i/o spaces)\n"
1739 " . ok to read (default)\n"
1740 "NOTE: flags are saved as defaults\n"
1741 "";
1742
1743static char *memex_subcmd_help_string =
1744 "Memory examine subcommands:\n"
1745 " hexval write this val to current location\n"
1746 " 'string' write chars from string to this location\n"
1747 " ' increment address\n"
1748 " ^ decrement address\n"
1749 " / increment addr by 0x10. //=0x100, ///=0x1000, etc\n"
1750 " \\ decrement addr by 0x10. \\\\=0x100, \\\\\\=0x1000, etc\n"
1751 " ` clear no-read flag\n"
1752 " ; stay at this addr\n"
1753 " v change to byte mode\n"
1754 " w change to word (2 byte) mode\n"
1755 " l change to long (4 byte) mode\n"
1756 " u change to doubleword (8 byte) mode\n"
1757 " m addr change current addr\n"
1758 " n toggle no-read flag\n"
1759 " r toggle byte reverse flag\n"
1760 " < count back up count bytes\n"
1761 " > count skip forward count bytes\n"
1762 " x exit this mode\n"
1763 "";
1764
1765void
1766memex(void)
1767{
1768 int cmd, inc, i, nslash;
1769 unsigned long n;
1770 unsigned char val[16];
1771
1772 scanhex((void *)&adrs);
1773 cmd = skipbl();
1774 if (cmd == '?') {
1775 printf(memex_help_string);
1776 return;
1777 } else {
1778 termch = cmd;
1779 }
1780 last_cmd = "m\n";
1781 while ((cmd = skipbl()) != '\n') {
1782 switch( cmd ){
1783 case 'b': size = 1; break;
1784 case 'w': size = 2; break;
1785 case 'l': size = 4; break;
1786 case 'd': size = 8; break;
1787 case 'r': brev = !brev; break;
1788 case 'n': mnoread = 1; break;
1789 case '.': mnoread = 0; break;
1790 }
1791 }
1792 if( size <= 0 )
1793 size = 1;
1794 else if( size > 8 )
1795 size = 8;
1796 for(;;){
1797 if (!mnoread)
1798 n = mread(adrs, val, size);
1799 printf("%.16x%c", adrs, brev? 'r': ' ');
1800 if (!mnoread) {
1801 if (brev)
1802 byterev(val, size);
1803 putchar(' ');
1804 for (i = 0; i < n; ++i)
1805 printf("%.2x", val[i]);
1806 for (; i < size; ++i)
1807 printf("%s", fault_chars[fault_type]);
1808 }
1809 putchar(' ');
1810 inc = size;
1811 nslash = 0;
1812 for(;;){
1813 if( scanhex(&n) ){
1814 for (i = 0; i < size; ++i)
1815 val[i] = n >> (i * 8);
1816 if (!brev)
1817 byterev(val, size);
1818 mwrite(adrs, val, size);
1819 inc = size;
1820 }
1821 cmd = skipbl();
1822 if (cmd == '\n')
1823 break;
1824 inc = 0;
1825 switch (cmd) {
1826 case '\'':
1827 for(;;){
1828 n = inchar();
1829 if( n == '\\' )
1830 n = bsesc();
1831 else if( n == '\'' )
1832 break;
1833 for (i = 0; i < size; ++i)
1834 val[i] = n >> (i * 8);
1835 if (!brev)
1836 byterev(val, size);
1837 mwrite(adrs, val, size);
1838 adrs += size;
1839 }
1840 adrs -= size;
1841 inc = size;
1842 break;
1843 case ',':
1844 adrs += size;
1845 break;
1846 case '.':
1847 mnoread = 0;
1848 break;
1849 case ';':
1850 break;
1851 case 'x':
1852 case EOF:
1853 scannl();
1854 return;
1855 case 'b':
1856 case 'v':
1857 size = 1;
1858 break;
1859 case 'w':
1860 size = 2;
1861 break;
1862 case 'l':
1863 size = 4;
1864 break;
1865 case 'u':
1866 size = 8;
1867 break;
1868 case '^':
1869 adrs -= size;
1870 break;
1871 break;
1872 case '/':
1873 if (nslash > 0)
1874 adrs -= 1 << nslash;
1875 else
1876 nslash = 0;
1877 nslash += 4;
1878 adrs += 1 << nslash;
1879 break;
1880 case '\\':
1881 if (nslash < 0)
1882 adrs += 1 << -nslash;
1883 else
1884 nslash = 0;
1885 nslash -= 4;
1886 adrs -= 1 << -nslash;
1887 break;
1888 case 'm':
1889 scanhex((void *)&adrs);
1890 break;
1891 case 'n':
1892 mnoread = 1;
1893 break;
1894 case 'r':
1895 brev = !brev;
1896 break;
1897 case '<':
1898 n = size;
1899 scanhex(&n);
1900 adrs -= n;
1901 break;
1902 case '>':
1903 n = size;
1904 scanhex(&n);
1905 adrs += n;
1906 break;
1907 case '?':
1908 printf(memex_subcmd_help_string);
1909 break;
1910 }
1911 }
1912 adrs += inc;
1913 }
1914}
1915
1916int
1917bsesc(void)
1918{
1919 int c;
1920
1921 c = inchar();
1922 switch( c ){
1923 case 'n': c = '\n'; break;
1924 case 'r': c = '\r'; break;
1925 case 'b': c = '\b'; break;
1926 case 't': c = '\t'; break;
1927 }
1928 return c;
1929}
1930
1931#define isxdigit(c) (('0' <= (c) && (c) <= '9') \
1932 || ('a' <= (c) && (c) <= 'f') \
1933 || ('A' <= (c) && (c) <= 'F'))
1934void
1935dump(void)
1936{
1937 int c;
1938
1939 c = inchar();
1940 if ((isxdigit(c) && c != 'f' && c != 'd') || c == '\n')
1941 termch = c;
1942 scanhex((void *)&adrs);
1943 if (termch != '\n')
1944 termch = 0;
1945 if (c == 'i') {
1946 scanhex(&nidump);
1947 if (nidump == 0)
1948 nidump = 16;
1949 else if (nidump > MAX_DUMP)
1950 nidump = MAX_DUMP;
1951 adrs += ppc_inst_dump(adrs, nidump, 1);
1952 last_cmd = "di\n";
1953 } else {
1954 scanhex(&ndump);
1955 if (ndump == 0)
1956 ndump = 64;
1957 else if (ndump > MAX_DUMP)
1958 ndump = MAX_DUMP;
1959 prdump(adrs, ndump);
1960 adrs += ndump;
1961 last_cmd = "d\n";
1962 }
1963}
1964
1965void
1966prdump(unsigned long adrs, long ndump)
1967{
1968 long n, m, c, r, nr;
1969 unsigned char temp[16];
1970
1971 for (n = ndump; n > 0;) {
1972 printf("%.16lx", adrs);
1973 putchar(' ');
1974 r = n < 16? n: 16;
1975 nr = mread(adrs, temp, r);
1976 adrs += nr;
1977 for (m = 0; m < r; ++m) {
1978 if ((m & 7) == 0 && m > 0)
1979 putchar(' ');
1980 if (m < nr)
1981 printf("%.2x", temp[m]);
1982 else
1983 printf("%s", fault_chars[fault_type]);
1984 }
1985 if (m <= 8)
1986 printf(" ");
1987 for (; m < 16; ++m)
1988 printf(" ");
1989 printf(" |");
1990 for (m = 0; m < r; ++m) {
1991 if (m < nr) {
1992 c = temp[m];
1993 putchar(' ' <= c && c <= '~'? c: '.');
1994 } else
1995 putchar(' ');
1996 }
1997 n -= r;
1998 for (; m < 16; ++m)
1999 putchar(' ');
2000 printf("|\n");
2001 if (nr < r)
2002 break;
2003 }
2004}
2005
2006int
2007ppc_inst_dump(unsigned long adr, long count, int praddr)
2008{
2009 int nr, dotted;
2010 unsigned long first_adr;
2011 unsigned long inst, last_inst = 0;
2012 unsigned char val[4];
2013
2014 dotted = 0;
2015 for (first_adr = adr; count > 0; --count, adr += 4) {
2016 nr = mread(adr, val, 4);
2017 if (nr == 0) {
2018 if (praddr) {
2019 const char *x = fault_chars[fault_type];
2020 printf("%.16lx %s%s%s%s\n", adr, x, x, x, x);
2021 }
2022 break;
2023 }
2024 inst = GETWORD(val);
2025 if (adr > first_adr && inst == last_inst) {
2026 if (!dotted) {
2027 printf(" ...\n");
2028 dotted = 1;
2029 }
2030 continue;
2031 }
2032 dotted = 0;
2033 last_inst = inst;
2034 if (praddr)
2035 printf("%.16lx %.8x", adr, inst);
2036 printf("\t");
2037 print_insn_powerpc(inst, adr, 0); /* always returns 4 */
2038 printf("\n");
2039 }
2040 return adr - first_adr;
2041}
2042
2043void
2044print_address(unsigned long addr)
2045{
2046 xmon_print_symbol(addr, "\t# ", "");
2047}
2048
2049
2050/*
2051 * Memory operations - move, set, print differences
2052 */
2053static unsigned long mdest; /* destination address */
2054static unsigned long msrc; /* source address */
2055static unsigned long mval; /* byte value to set memory to */
2056static unsigned long mcount; /* # bytes to affect */
2057static unsigned long mdiffs; /* max # differences to print */
2058
2059void
2060memops(int cmd)
2061{
2062 scanhex((void *)&mdest);
2063 if( termch != '\n' )
2064 termch = 0;
2065 scanhex((void *)(cmd == 's'? &mval: &msrc));
2066 if( termch != '\n' )
2067 termch = 0;
2068 scanhex((void *)&mcount);
2069 switch( cmd ){
2070 case 'm':
2071 memmove((void *)mdest, (void *)msrc, mcount);
2072 break;
2073 case 's':
2074 memset((void *)mdest, mval, mcount);
2075 break;
2076 case 'd':
2077 if( termch != '\n' )
2078 termch = 0;
2079 scanhex((void *)&mdiffs);
2080 memdiffs((unsigned char *)mdest, (unsigned char *)msrc, mcount, mdiffs);
2081 break;
2082 }
2083}
2084
2085void
2086memdiffs(unsigned char *p1, unsigned char *p2, unsigned nb, unsigned maxpr)
2087{
2088 unsigned n, prt;
2089
2090 prt = 0;
2091 for( n = nb; n > 0; --n )
2092 if( *p1++ != *p2++ )
2093 if( ++prt <= maxpr )
2094 printf("%.16x %.2x # %.16x %.2x\n", p1 - 1,
2095 p1[-1], p2 - 1, p2[-1]);
2096 if( prt > maxpr )
2097 printf("Total of %d differences\n", prt);
2098}
2099
2100static unsigned mend;
2101static unsigned mask;
2102
2103void
2104memlocate(void)
2105{
2106 unsigned a, n;
2107 unsigned char val[4];
2108
2109 last_cmd = "ml";
2110 scanhex((void *)&mdest);
2111 if (termch != '\n') {
2112 termch = 0;
2113 scanhex((void *)&mend);
2114 if (termch != '\n') {
2115 termch = 0;
2116 scanhex((void *)&mval);
2117 mask = ~0;
2118 if (termch != '\n') termch = 0;
2119 scanhex((void *)&mask);
2120 }
2121 }
2122 n = 0;
2123 for (a = mdest; a < mend; a += 4) {
2124 if (mread(a, val, 4) == 4
2125 && ((GETWORD(val) ^ mval) & mask) == 0) {
2126 printf("%.16x: %.16x\n", a, GETWORD(val));
2127 if (++n >= 10)
2128 break;
2129 }
2130 }
2131}
2132
2133static unsigned long mskip = 0x1000;
2134static unsigned long mlim = 0xffffffff;
2135
2136void
2137memzcan(void)
2138{
2139 unsigned char v;
2140 unsigned a;
2141 int ok, ook;
2142
2143 scanhex(&mdest);
2144 if (termch != '\n') termch = 0;
2145 scanhex(&mskip);
2146 if (termch != '\n') termch = 0;
2147 scanhex(&mlim);
2148 ook = 0;
2149 for (a = mdest; a < mlim; a += mskip) {
2150 ok = mread(a, &v, 1);
2151 if (ok && !ook) {
2152 printf("%.8x .. ", a);
2153 fflush(stdout);
2154 } else if (!ok && ook)
2155 printf("%.8x\n", a - mskip);
2156 ook = ok;
2157 if (a + mskip < a)
2158 break;
2159 }
2160 if (ook)
2161 printf("%.8x\n", a - mskip);
2162}
2163
2164/* Input scanning routines */
2165int
2166skipbl(void)
2167{
2168 int c;
2169
2170 if( termch != 0 ){
2171 c = termch;
2172 termch = 0;
2173 } else
2174 c = inchar();
2175 while( c == ' ' || c == '\t' )
2176 c = inchar();
2177 return c;
2178}
2179
2180#define N_PTREGS 44
2181static char *regnames[N_PTREGS] = {
2182 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2183 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2184 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
2185 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
2186 "pc", "msr", "or3", "ctr", "lr", "xer", "ccr", "softe",
2187 "trap", "dar", "dsisr", "res"
2188};
2189
2190int
2191scanhex(unsigned long *vp)
2192{
2193 int c, d;
2194 unsigned long v;
2195
2196 c = skipbl();
2197 if (c == '%') {
2198 /* parse register name */
2199 char regname[8];
2200 int i;
2201
2202 for (i = 0; i < sizeof(regname) - 1; ++i) {
2203 c = inchar();
2204 if (!isalnum(c)) {
2205 termch = c;
2206 break;
2207 }
2208 regname[i] = c;
2209 }
2210 regname[i] = 0;
2211 for (i = 0; i < N_PTREGS; ++i) {
2212 if (strcmp(regnames[i], regname) == 0) {
2213 if (xmon_regs == NULL) {
2214 printf("regs not available\n");
2215 return 0;
2216 }
2217 *vp = ((unsigned long *)xmon_regs)[i];
2218 return 1;
2219 }
2220 }
2221 printf("invalid register name '%%%s'\n", regname);
2222 return 0;
2223 }
2224
2225 /* skip leading "0x" if any */
2226
2227 if (c == '0') {
2228 c = inchar();
2229 if (c == 'x') {
2230 c = inchar();
2231 } else {
2232 d = hexdigit(c);
2233 if (d == EOF) {
2234 termch = c;
2235 *vp = 0;
2236 return 1;
2237 }
2238 }
2239 } else if (c == '$') {
2240 int i;
2241 for (i=0; i<63; i++) {
2242 c = inchar();
2243 if (isspace(c)) {
2244 termch = c;
2245 break;
2246 }
2247 tmpstr[i] = c;
2248 }
2249 tmpstr[i++] = 0;
2250 *vp = kallsyms_lookup_name(tmpstr);
2251 if (!(*vp)) {
2252 printf("unknown symbol '%s'\n", tmpstr);
2253 return 0;
2254 }
2255 return 1;
2256 }
2257
2258 d = hexdigit(c);
2259 if (d == EOF) {
2260 termch = c;
2261 return 0;
2262 }
2263 v = 0;
2264 do {
2265 v = (v << 4) + d;
2266 c = inchar();
2267 d = hexdigit(c);
2268 } while (d != EOF);
2269 termch = c;
2270 *vp = v;
2271 return 1;
2272}
2273
2274void
2275scannl(void)
2276{
2277 int c;
2278
2279 c = termch;
2280 termch = 0;
2281 while( c != '\n' )
2282 c = inchar();
2283}
2284
2285int
2286hexdigit(int c)
2287{
2288 if( '0' <= c && c <= '9' )
2289 return c - '0';
2290 if( 'A' <= c && c <= 'F' )
2291 return c - ('A' - 10);
2292 if( 'a' <= c && c <= 'f' )
2293 return c - ('a' - 10);
2294 return EOF;
2295}
2296
2297void
2298getstring(char *s, int size)
2299{
2300 int c;
2301
2302 c = skipbl();
2303 do {
2304 if( size > 1 ){
2305 *s++ = c;
2306 --size;
2307 }
2308 c = inchar();
2309 } while( c != ' ' && c != '\t' && c != '\n' );
2310 termch = c;
2311 *s = 0;
2312}
2313
2314static char line[256];
2315static char *lineptr;
2316
2317void
2318flush_input(void)
2319{
2320 lineptr = NULL;
2321}
2322
2323int
2324inchar(void)
2325{
2326 if (lineptr == NULL || *lineptr == 0) {
2327 if (fgets(line, sizeof(line), stdin) == NULL) {
2328 lineptr = NULL;
2329 return EOF;
2330 }
2331 lineptr = line;
2332 }
2333 return *lineptr++;
2334}
2335
2336void
2337take_input(char *str)
2338{
2339 lineptr = str;
2340}
2341
2342
2343static void
2344symbol_lookup(void)
2345{
2346 int type = inchar();
2347 unsigned long addr;
2348 static char tmp[64];
2349
2350 switch (type) {
2351 case 'a':
2352 if (scanhex(&addr))
2353 xmon_print_symbol(addr, ": ", "\n");
2354 termch = 0;
2355 break;
2356 case 's':
2357 getstring(tmp, 64);
2358 if (setjmp(bus_error_jmp) == 0) {
2359 catch_memory_errors = 1;
2360 sync();
2361 addr = kallsyms_lookup_name(tmp);
2362 if (addr)
2363 printf("%s: %lx\n", tmp, addr);
2364 else
2365 printf("Symbol '%s' not found.\n", tmp);
2366 sync();
2367 }
2368 catch_memory_errors = 0;
2369 termch = 0;
2370 break;
2371 }
2372}
2373
2374
2375/* Print an address in numeric and symbolic form (if possible) */
2376static void xmon_print_symbol(unsigned long address, const char *mid,
2377 const char *after)
2378{
2379 char *modname;
2380 const char *name = NULL;
2381 unsigned long offset, size;
2382
2383 printf("%.16lx", address);
2384 if (setjmp(bus_error_jmp) == 0) {
2385 catch_memory_errors = 1;
2386 sync();
2387 name = kallsyms_lookup(address, &size, &offset, &modname,
2388 tmpstr);
2389 sync();
2390 /* wait a little while to see if we get a machine check */
2391 __delay(200);
2392 }
2393
2394 catch_memory_errors = 0;
2395
2396 if (name) {
2397 printf("%s%s+%#lx/%#lx", mid, name, offset, size);
2398 if (modname)
2399 printf(" [%s]", modname);
2400 }
2401 printf("%s", after);
2402}
2403
2404static void debug_trace(void)
2405{
2406 unsigned long val, cmd, on;
2407
2408 cmd = skipbl();
2409 if (cmd == '\n') {
2410 /* show current state */
2411 unsigned long i;
2412 printf("ppc64_debug_switch = 0x%lx\n", ppc64_debug_switch);
2413 for (i = 0; i < PPCDBG_NUM_FLAGS ;i++) {
2414 on = PPCDBG_BITVAL(i) & ppc64_debug_switch;
2415 printf("%02x %s %12s ", i, on ? "on " : "off", trace_names[i] ? trace_names[i] : "");
2416 if (((i+1) % 3) == 0)
2417 printf("\n");
2418 }
2419 printf("\n");
2420 return;
2421 }
2422 while (cmd != '\n') {
2423 on = 1; /* default if no sign given */
2424 while (cmd == '+' || cmd == '-') {
2425 on = (cmd == '+');
2426 cmd = inchar();
2427 if (cmd == ' ' || cmd == '\n') { /* Turn on or off based on + or - */
2428 ppc64_debug_switch = on ? PPCDBG_ALL:PPCDBG_NONE;
2429 printf("Setting all values to %s...\n", on ? "on" : "off");
2430 if (cmd == '\n') return;
2431 else cmd = skipbl();
2432 }
2433 else
2434 termch = cmd;
2435 }
2436 termch = cmd; /* not +/- ... let scanhex see it */
2437 scanhex((void *)&val);
2438 if (val >= 64) {
2439 printf("Value %x out of range:\n", val);
2440 return;
2441 }
2442 if (on) {
2443 ppc64_debug_switch |= PPCDBG_BITVAL(val);
2444 printf("enable debug %x %s\n", val, trace_names[val] ? trace_names[val] : "");
2445 } else {
2446 ppc64_debug_switch &= ~PPCDBG_BITVAL(val);
2447 printf("disable debug %x %s\n", val, trace_names[val] ? trace_names[val] : "");
2448 }
2449 cmd = skipbl();
2450 }
2451}
2452
2453static void dump_slb(void)
2454{
2455 int i;
2456 unsigned long tmp;
2457
2458 printf("SLB contents of cpu %x\n", smp_processor_id());
2459
2460 for (i = 0; i < SLB_NUM_ENTRIES; i++) {
2461 asm volatile("slbmfee %0,%1" : "=r" (tmp) : "r" (i));
2462 printf("%02d %016lx ", i, tmp);
2463
2464 asm volatile("slbmfev %0,%1" : "=r" (tmp) : "r" (i));
2465 printf("%016lx\n", tmp);
2466 }
2467}
2468
2469static void dump_stab(void)
2470{
2471 int i;
2472 unsigned long *tmp = (unsigned long *)get_paca()->stab_addr;
2473
2474 printf("Segment table contents of cpu %x\n", smp_processor_id());
2475
2476 for (i = 0; i < PAGE_SIZE/16; i++) {
2477 unsigned long a, b;
2478
2479 a = *tmp++;
2480 b = *tmp++;
2481
2482 if (a || b) {
2483 printf("%03d %016lx ", i, a);
2484 printf("%016lx\n", b);
2485 }
2486 }
2487}
2488
2489void xmon_init(void)
2490{
2491 __debugger = xmon;
2492 __debugger_ipi = xmon_ipi;
2493 __debugger_bpt = xmon_bpt;
2494 __debugger_sstep = xmon_sstep;
2495 __debugger_iabr_match = xmon_iabr_match;
2496 __debugger_dabr_match = xmon_dabr_match;
2497 __debugger_fault_handler = xmon_fault_handler;
2498}
2499
2500void dump_segments(void)
2501{
2502 if (cpu_has_feature(CPU_FTR_SLB))
2503 dump_slb();
2504 else
2505 dump_stab();
2506}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 03:32:17 -0500