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authorPaul Mackerras <paulus@samba.org>2005-10-28 08:53:37 -0400
committerPaul Mackerras <paulus@samba.org>2005-10-28 08:53:37 -0400
commitf78541dcec327b0c46b150ee7d727f3db80275c4 (patch)
tree9336801742d93ffa0c84c76e2b3cdc5b50c7125b /arch/ppc64/xmon
parentc032524f0ddea5fcc3a2cece0d4a61f37e5ca9cd (diff)
powerpc: Merge xmon
The merged version follows the ppc64 version pretty closely mostly, and in fact ARCH=ppc64 now uses the arch/powerpc/xmon version. The main difference for ppc64 is that the 'p' command to call show_state (which was always pretty dodgy) has been replaced by the ppc32 'p' command, which calls a given procedure (so in fact the old 'p' command behaviour can be achieved with 'p $show_state'). Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc64/xmon')
-rw-r--r--arch/ppc64/xmon/Makefile5
-rw-r--r--arch/ppc64/xmon/ansidecl.h141
-rw-r--r--arch/ppc64/xmon/nonstdio.h22
-rw-r--r--arch/ppc64/xmon/ppc-dis.c184
-rw-r--r--arch/ppc64/xmon/ppc-opc.c4621
-rw-r--r--arch/ppc64/xmon/ppc.h307
-rw-r--r--arch/ppc64/xmon/setjmp.S73
-rw-r--r--arch/ppc64/xmon/start.c187
-rw-r--r--arch/ppc64/xmon/subr_prf.c55
-rw-r--r--arch/ppc64/xmon/xmon.c2514
10 files changed, 0 insertions, 8109 deletions
diff --git a/arch/ppc64/xmon/Makefile b/arch/ppc64/xmon/Makefile
deleted file mode 100644
index fb21a7088d3e..000000000000
--- a/arch/ppc64/xmon/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1# Makefile for xmon
2
3EXTRA_CFLAGS += -mno-minimal-toc
4
5obj-y := start.o xmon.o ppc-dis.o ppc-opc.o subr_prf.o setjmp.o
diff --git a/arch/ppc64/xmon/ansidecl.h b/arch/ppc64/xmon/ansidecl.h
deleted file mode 100644
index c9b9f0929e9e..000000000000
--- a/arch/ppc64/xmon/ansidecl.h
+++ /dev/null
@@ -1,141 +0,0 @@
1/* ANSI and traditional C compatibility macros
2 Copyright 1991, 1992 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4
5This program is free software; you can redistribute it and/or modify
6it under the terms of the GNU General Public License as published by
7the Free Software Foundation; either version 2 of the License, or
8(at your option) any later version.
9
10This program is distributed in the hope that it will be useful,
11but WITHOUT ANY WARRANTY; without even the implied warranty of
12MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13GNU General Public License for more details.
14
15You should have received a copy of the GNU General Public License
16along with this program; if not, write to the Free Software
17Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
18
19/* ANSI and traditional C compatibility macros
20
21 ANSI C is assumed if __STDC__ is #defined.
22
23 Macro ANSI C definition Traditional C definition
24 ----- ---- - ---------- ----------- - ----------
25 PTR `void *' `char *'
26 LONG_DOUBLE `long double' `double'
27 VOLATILE `volatile' `'
28 SIGNED `signed' `'
29 PTRCONST `void *const' `char *'
30 ANSI_PROTOTYPES 1 not defined
31
32 CONST is also defined, but is obsolete. Just use const.
33
34 DEFUN (name, arglist, args)
35
36 Defines function NAME.
37
38 ARGLIST lists the arguments, separated by commas and enclosed in
39 parentheses. ARGLIST becomes the argument list in traditional C.
40
41 ARGS list the arguments with their types. It becomes a prototype in
42 ANSI C, and the type declarations in traditional C. Arguments should
43 be separated with `AND'. For functions with a variable number of
44 arguments, the last thing listed should be `DOTS'.
45
46 DEFUN_VOID (name)
47
48 Defines a function NAME, which takes no arguments.
49
50 obsolete -- EXFUN (name, (prototype)) -- obsolete.
51
52 Replaced by PARAMS. Do not use; will disappear someday soon.
53 Was used in external function declarations.
54 In ANSI C it is `NAME PROTOTYPE' (so PROTOTYPE should be enclosed in
55 parentheses). In traditional C it is `NAME()'.
56 For a function that takes no arguments, PROTOTYPE should be `(void)'.
57
58 PARAMS ((args))
59
60 We could use the EXFUN macro to handle prototype declarations, but
61 the name is misleading and the result is ugly. So we just define a
62 simple macro to handle the parameter lists, as in:
63
64 static int foo PARAMS ((int, char));
65
66 This produces: `static int foo();' or `static int foo (int, char);'
67
68 EXFUN would have done it like this:
69
70 static int EXFUN (foo, (int, char));
71
72 but the function is not external...and it's hard to visually parse
73 the function name out of the mess. EXFUN should be considered
74 obsolete; new code should be written to use PARAMS.
75
76 For example:
77 extern int printf PARAMS ((CONST char *format DOTS));
78 int DEFUN(fprintf, (stream, format),
79 FILE *stream AND CONST char *format DOTS) { ... }
80 void DEFUN_VOID(abort) { ... }
81*/
82
83#ifndef _ANSIDECL_H
84
85#define _ANSIDECL_H 1
86
87
88/* Every source file includes this file,
89 so they will all get the switch for lint. */
90/* LINTLIBRARY */
91
92
93#if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(WIN32)
94/* All known AIX compilers implement these things (but don't always
95 define __STDC__). The RISC/OS MIPS compiler defines these things
96 in SVR4 mode, but does not define __STDC__. */
97
98#define PTR void *
99#define PTRCONST void *CONST
100#define LONG_DOUBLE long double
101
102#define AND ,
103#define NOARGS void
104#define CONST const
105#define VOLATILE volatile
106#define SIGNED signed
107#define DOTS , ...
108
109#define EXFUN(name, proto) name proto
110#define DEFUN(name, arglist, args) name(args)
111#define DEFUN_VOID(name) name(void)
112
113#define PROTO(type, name, arglist) type name arglist
114#define PARAMS(paramlist) paramlist
115#define ANSI_PROTOTYPES 1
116
117#else /* Not ANSI C. */
118
119#define PTR char *
120#define PTRCONST PTR
121#define LONG_DOUBLE double
122
123#define AND ;
124#define NOARGS
125#define CONST
126#ifndef const /* some systems define it in header files for non-ansi mode */
127#define const
128#endif
129#define VOLATILE
130#define SIGNED
131#define DOTS
132
133#define EXFUN(name, proto) name()
134#define DEFUN(name, arglist, args) name arglist args;
135#define DEFUN_VOID(name) name()
136#define PROTO(type, name, arglist) type name ()
137#define PARAMS(paramlist) ()
138
139#endif /* ANSI C. */
140
141#endif /* ansidecl.h */
diff --git a/arch/ppc64/xmon/nonstdio.h b/arch/ppc64/xmon/nonstdio.h
deleted file mode 100644
index 84211a21c6f4..000000000000
--- a/arch/ppc64/xmon/nonstdio.h
+++ /dev/null
@@ -1,22 +0,0 @@
1typedef int FILE;
2extern FILE *xmon_stdin, *xmon_stdout;
3#define EOF (-1)
4#define stdin xmon_stdin
5#define stdout xmon_stdout
6#define printf xmon_printf
7#define fprintf xmon_fprintf
8#define fputs xmon_fputs
9#define fgets xmon_fgets
10#define putchar xmon_putchar
11#define getchar xmon_getchar
12#define putc xmon_putc
13#define getc xmon_getc
14#define fopen(n, m) NULL
15#define fflush(f) do {} while (0)
16#define fclose(f) do {} while (0)
17extern char *fgets(char *, int, void *);
18extern void xmon_printf(const char *, ...);
19extern void xmon_fprintf(void *, const char *, ...);
20extern void xmon_sprintf(char *, const char *, ...);
21
22#define perror(s) printf("%s: no files!\n", (s))
diff --git a/arch/ppc64/xmon/ppc-dis.c b/arch/ppc64/xmon/ppc-dis.c
deleted file mode 100644
index ac0a9d2427e0..000000000000
--- a/arch/ppc64/xmon/ppc-dis.c
+++ /dev/null
@@ -1,184 +0,0 @@
1/* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
102, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#include "nonstdio.h"
22#include "ansidecl.h"
23#include "ppc.h"
24
25extern void print_address (unsigned long memaddr);
26
27/* Print a PowerPC or POWER instruction. */
28
29int
30print_insn_powerpc (unsigned long insn, unsigned long memaddr, int dialect)
31{
32 const struct powerpc_opcode *opcode;
33 const struct powerpc_opcode *opcode_end;
34 unsigned long op;
35
36 if (dialect == 0)
37 dialect = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON
38 | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_ALTIVEC;
39
40 /* Get the major opcode of the instruction. */
41 op = PPC_OP (insn);
42
43 /* Find the first match in the opcode table. We could speed this up
44 a bit by doing a binary search on the major opcode. */
45 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
46 again:
47 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
48 {
49 unsigned long table_op;
50 const unsigned char *opindex;
51 const struct powerpc_operand *operand;
52 int invalid;
53 int need_comma;
54 int need_paren;
55
56 table_op = PPC_OP (opcode->opcode);
57 if (op < table_op)
58 break;
59 if (op > table_op)
60 continue;
61
62 if ((insn & opcode->mask) != opcode->opcode
63 || (opcode->flags & dialect) == 0)
64 continue;
65
66 /* Make two passes over the operands. First see if any of them
67 have extraction functions, and, if they do, make sure the
68 instruction is valid. */
69 invalid = 0;
70 for (opindex = opcode->operands; *opindex != 0; opindex++)
71 {
72 operand = powerpc_operands + *opindex;
73 if (operand->extract)
74 (*operand->extract) (insn, dialect, &invalid);
75 }
76 if (invalid)
77 continue;
78
79 /* The instruction is valid. */
80 printf("%s", opcode->name);
81 if (opcode->operands[0] != 0)
82 printf("\t");
83
84 /* Now extract and print the operands. */
85 need_comma = 0;
86 need_paren = 0;
87 for (opindex = opcode->operands; *opindex != 0; opindex++)
88 {
89 long value;
90
91 operand = powerpc_operands + *opindex;
92
93 /* Operands that are marked FAKE are simply ignored. We
94 already made sure that the extract function considered
95 the instruction to be valid. */
96 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
97 continue;
98
99 /* Extract the value from the instruction. */
100 if (operand->extract)
101 value = (*operand->extract) (insn, dialect, &invalid);
102 else
103 {
104 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
105 if ((operand->flags & PPC_OPERAND_SIGNED) != 0
106 && (value & (1 << (operand->bits - 1))) != 0)
107 value -= 1 << operand->bits;
108 }
109
110 /* If the operand is optional, and the value is zero, don't
111 print anything. */
112 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
113 && (operand->flags & PPC_OPERAND_NEXT) == 0
114 && value == 0)
115 continue;
116
117 if (need_comma)
118 {
119 printf(",");
120 need_comma = 0;
121 }
122
123 /* Print the operand as directed by the flags. */
124 if ((operand->flags & PPC_OPERAND_GPR) != 0)
125 printf("r%ld", value);
126 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
127 printf("f%ld", value);
128 else if ((operand->flags & PPC_OPERAND_VR) != 0)
129 printf("v%ld", value);
130 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
131 print_address (memaddr + value);
132 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
133 print_address (value & 0xffffffff);
134 else if ((operand->flags & PPC_OPERAND_CR) == 0
135 || (dialect & PPC_OPCODE_PPC) == 0)
136 printf("%ld", value);
137 else
138 {
139 if (operand->bits == 3)
140 printf("cr%d", value);
141 else
142 {
143 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
144 int cr;
145 int cc;
146
147 cr = value >> 2;
148 if (cr != 0)
149 printf("4*cr%d+", cr);
150 cc = value & 3;
151 printf("%s", cbnames[cc]);
152 }
153 }
154
155 if (need_paren)
156 {
157 printf(")");
158 need_paren = 0;
159 }
160
161 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
162 need_comma = 1;
163 else
164 {
165 printf("(");
166 need_paren = 1;
167 }
168 }
169
170 /* We have found and printed an instruction; return. */
171 return 4;
172 }
173
174 if ((dialect & PPC_OPCODE_ANY) != 0)
175 {
176 dialect = ~PPC_OPCODE_ANY;
177 goto again;
178 }
179
180 /* We could not find a match. */
181 printf(".long 0x%lx", insn);
182
183 return 4;
184}
diff --git a/arch/ppc64/xmon/ppc-opc.c b/arch/ppc64/xmon/ppc-opc.c
deleted file mode 100644
index 5ee8fc32f824..000000000000
--- a/arch/ppc64/xmon/ppc-opc.c
+++ /dev/null
@@ -1,4621 +0,0 @@
1/* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23#include <linux/stddef.h>
24#include "nonstdio.h"
25#include "ppc.h"
26
27#define ATTRIBUTE_UNUSED
28#define _(x) x
29
30/* This file holds the PowerPC opcode table. The opcode table
31 includes almost all of the extended instruction mnemonics. This
32 permits the disassembler to use them, and simplifies the assembler
33 logic, at the cost of increasing the table size. The table is
34 strictly constant data, so the compiler should be able to put it in
35 the .text section.
36
37 This file also holds the operand table. All knowledge about
38 inserting operands into instructions and vice-versa is kept in this
39 file. */
40
41/* Local insertion and extraction functions. */
42
43static unsigned long insert_bat (unsigned long, long, int, const char **);
44static long extract_bat (unsigned long, int, int *);
45static unsigned long insert_bba (unsigned long, long, int, const char **);
46static long extract_bba (unsigned long, int, int *);
47static unsigned long insert_bd (unsigned long, long, int, const char **);
48static long extract_bd (unsigned long, int, int *);
49static unsigned long insert_bdm (unsigned long, long, int, const char **);
50static long extract_bdm (unsigned long, int, int *);
51static unsigned long insert_bdp (unsigned long, long, int, const char **);
52static long extract_bdp (unsigned long, int, int *);
53static unsigned long insert_bo (unsigned long, long, int, const char **);
54static long extract_bo (unsigned long, int, int *);
55static unsigned long insert_boe (unsigned long, long, int, const char **);
56static long extract_boe (unsigned long, int, int *);
57static unsigned long insert_dq (unsigned long, long, int, const char **);
58static long extract_dq (unsigned long, int, int *);
59static unsigned long insert_ds (unsigned long, long, int, const char **);
60static long extract_ds (unsigned long, int, int *);
61static unsigned long insert_de (unsigned long, long, int, const char **);
62static long extract_de (unsigned long, int, int *);
63static unsigned long insert_des (unsigned long, long, int, const char **);
64static long extract_des (unsigned long, int, int *);
65static unsigned long insert_fxm (unsigned long, long, int, const char **);
66static long extract_fxm (unsigned long, int, int *);
67static unsigned long insert_li (unsigned long, long, int, const char **);
68static long extract_li (unsigned long, int, int *);
69static unsigned long insert_mbe (unsigned long, long, int, const char **);
70static long extract_mbe (unsigned long, int, int *);
71static unsigned long insert_mb6 (unsigned long, long, int, const char **);
72static long extract_mb6 (unsigned long, int, int *);
73static unsigned long insert_nb (unsigned long, long, int, const char **);
74static long extract_nb (unsigned long, int, int *);
75static unsigned long insert_nsi (unsigned long, long, int, const char **);
76static long extract_nsi (unsigned long, int, int *);
77static unsigned long insert_ral (unsigned long, long, int, const char **);
78static unsigned long insert_ram (unsigned long, long, int, const char **);
79static unsigned long insert_raq (unsigned long, long, int, const char **);
80static unsigned long insert_ras (unsigned long, long, int, const char **);
81static unsigned long insert_rbs (unsigned long, long, int, const char **);
82static long extract_rbs (unsigned long, int, int *);
83static unsigned long insert_rsq (unsigned long, long, int, const char **);
84static unsigned long insert_rtq (unsigned long, long, int, const char **);
85static unsigned long insert_sh6 (unsigned long, long, int, const char **);
86static long extract_sh6 (unsigned long, int, int *);
87static unsigned long insert_spr (unsigned long, long, int, const char **);
88static long extract_spr (unsigned long, int, int *);
89static unsigned long insert_tbr (unsigned long, long, int, const char **);
90static long extract_tbr (unsigned long, int, int *);
91static unsigned long insert_ev2 (unsigned long, long, int, const char **);
92static long extract_ev2 (unsigned long, int, int *);
93static unsigned long insert_ev4 (unsigned long, long, int, const char **);
94static long extract_ev4 (unsigned long, int, int *);
95static unsigned long insert_ev8 (unsigned long, long, int, const char **);
96static long extract_ev8 (unsigned long, int, int *);
97
98/* The operands table.
99
100 The fields are bits, shift, insert, extract, flags.
101
102 We used to put parens around the various additions, like the one
103 for BA just below. However, that caused trouble with feeble
104 compilers with a limit on depth of a parenthesized expression, like
105 (reportedly) the compiler in Microsoft Developer Studio 5. So we
106 omit the parens, since the macros are never used in a context where
107 the addition will be ambiguous. */
108
109const struct powerpc_operand powerpc_operands[] =
110{
111 /* The zero index is used to indicate the end of the list of
112 operands. */
113#define UNUSED 0
114 { 0, 0, NULL, NULL, 0 },
115
116 /* The BA field in an XL form instruction. */
117#define BA UNUSED + 1
118#define BA_MASK (0x1f << 16)
119 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
120
121 /* The BA field in an XL form instruction when it must be the same
122 as the BT field in the same instruction. */
123#define BAT BA + 1
124 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
125
126 /* The BB field in an XL form instruction. */
127#define BB BAT + 1
128#define BB_MASK (0x1f << 11)
129 { 5, 11, NULL, NULL, PPC_OPERAND_CR },
130
131 /* The BB field in an XL form instruction when it must be the same
132 as the BA field in the same instruction. */
133#define BBA BB + 1
134 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
135
136 /* The BD field in a B form instruction. The lower two bits are
137 forced to zero. */
138#define BD BBA + 1
139 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
140
141 /* The BD field in a B form instruction when absolute addressing is
142 used. */
143#define BDA BD + 1
144 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
145
146 /* The BD field in a B form instruction when the - modifier is used.
147 This sets the y bit of the BO field appropriately. */
148#define BDM BDA + 1
149 { 16, 0, insert_bdm, extract_bdm,
150 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
151
152 /* The BD field in a B form instruction when the - modifier is used
153 and absolute address is used. */
154#define BDMA BDM + 1
155 { 16, 0, insert_bdm, extract_bdm,
156 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
157
158 /* The BD field in a B form instruction when the + modifier is used.
159 This sets the y bit of the BO field appropriately. */
160#define BDP BDMA + 1
161 { 16, 0, insert_bdp, extract_bdp,
162 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
163
164 /* The BD field in a B form instruction when the + modifier is used
165 and absolute addressing is used. */
166#define BDPA BDP + 1
167 { 16, 0, insert_bdp, extract_bdp,
168 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
169
170 /* The BF field in an X or XL form instruction. */
171#define BF BDPA + 1
172 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
173
174 /* An optional BF field. This is used for comparison instructions,
175 in which an omitted BF field is taken as zero. */
176#define OBF BF + 1
177 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
178
179 /* The BFA field in an X or XL form instruction. */
180#define BFA OBF + 1
181 { 3, 18, NULL, NULL, PPC_OPERAND_CR },
182
183 /* The BI field in a B form or XL form instruction. */
184#define BI BFA + 1
185#define BI_MASK (0x1f << 16)
186 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
187
188 /* The BO field in a B form instruction. Certain values are
189 illegal. */
190#define BO BI + 1
191#define BO_MASK (0x1f << 21)
192 { 5, 21, insert_bo, extract_bo, 0 },
193
194 /* The BO field in a B form instruction when the + or - modifier is
195 used. This is like the BO field, but it must be even. */
196#define BOE BO + 1
197 { 5, 21, insert_boe, extract_boe, 0 },
198
199 /* The BT field in an X or XL form instruction. */
200#define BT BOE + 1
201 { 5, 21, NULL, NULL, PPC_OPERAND_CR },
202
203 /* The condition register number portion of the BI field in a B form
204 or XL form instruction. This is used for the extended
205 conditional branch mnemonics, which set the lower two bits of the
206 BI field. This field is optional. */
207#define CR BT + 1
208 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
209
210 /* The CRB field in an X form instruction. */
211#define CRB CR + 1
212 { 5, 6, NULL, NULL, 0 },
213
214 /* The CRFD field in an X form instruction. */
215#define CRFD CRB + 1
216 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
217
218 /* The CRFS field in an X form instruction. */
219#define CRFS CRFD + 1
220 { 3, 0, NULL, NULL, PPC_OPERAND_CR },
221
222 /* The CT field in an X form instruction. */
223#define CT CRFS + 1
224 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
225
226 /* The D field in a D form instruction. This is a displacement off
227 a register, and implies that the next operand is a register in
228 parentheses. */
229#define D CT + 1
230 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
231
232 /* The DE field in a DE form instruction. This is like D, but is 12
233 bits only. */
234#define DE D + 1
235 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
236
237 /* The DES field in a DES form instruction. This is like DS, but is 14
238 bits only (12 stored.) */
239#define DES DE + 1
240 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
241
242 /* The DQ field in a DQ form instruction. This is like D, but the
243 lower four bits are forced to zero. */
244#define DQ DES + 1
245 { 16, 0, insert_dq, extract_dq,
246 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
247
248 /* The DS field in a DS form instruction. This is like D, but the
249 lower two bits are forced to zero. */
250#define DS DQ + 1
251 { 16, 0, insert_ds, extract_ds,
252 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
253
254 /* The E field in a wrteei instruction. */
255#define E DS + 1
256 { 1, 15, NULL, NULL, 0 },
257
258 /* The FL1 field in a POWER SC form instruction. */
259#define FL1 E + 1
260 { 4, 12, NULL, NULL, 0 },
261
262 /* The FL2 field in a POWER SC form instruction. */
263#define FL2 FL1 + 1
264 { 3, 2, NULL, NULL, 0 },
265
266 /* The FLM field in an XFL form instruction. */
267#define FLM FL2 + 1
268 { 8, 17, NULL, NULL, 0 },
269
270 /* The FRA field in an X or A form instruction. */
271#define FRA FLM + 1
272#define FRA_MASK (0x1f << 16)
273 { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
274
275 /* The FRB field in an X or A form instruction. */
276#define FRB FRA + 1
277#define FRB_MASK (0x1f << 11)
278 { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
279
280 /* The FRC field in an A form instruction. */
281#define FRC FRB + 1
282#define FRC_MASK (0x1f << 6)
283 { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
284
285 /* The FRS field in an X form instruction or the FRT field in a D, X
286 or A form instruction. */
287#define FRS FRC + 1
288#define FRT FRS
289 { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
290
291 /* The FXM field in an XFX instruction. */
292#define FXM FRS + 1
293#define FXM_MASK (0xff << 12)
294 { 8, 12, insert_fxm, extract_fxm, 0 },
295
296 /* Power4 version for mfcr. */
297#define FXM4 FXM + 1
298 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
299
300 /* The L field in a D or X form instruction. */
301#define L FXM4 + 1
302 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
303
304 /* The LEV field in a POWER SC form instruction. */
305#define LEV L + 1
306 { 7, 5, NULL, NULL, 0 },
307
308 /* The LI field in an I form instruction. The lower two bits are
309 forced to zero. */
310#define LI LEV + 1
311 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
312
313 /* The LI field in an I form instruction when used as an absolute
314 address. */
315#define LIA LI + 1
316 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
317
318 /* The LS field in an X (sync) form instruction. */
319#define LS LIA + 1
320 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
321
322 /* The MB field in an M form instruction. */
323#define MB LS + 1
324#define MB_MASK (0x1f << 6)
325 { 5, 6, NULL, NULL, 0 },
326
327 /* The ME field in an M form instruction. */
328#define ME MB + 1
329#define ME_MASK (0x1f << 1)
330 { 5, 1, NULL, NULL, 0 },
331
332 /* The MB and ME fields in an M form instruction expressed a single
333 operand which is a bitmask indicating which bits to select. This
334 is a two operand form using PPC_OPERAND_NEXT. See the
335 description in opcode/ppc.h for what this means. */
336#define MBE ME + 1
337 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
338 { 32, 0, insert_mbe, extract_mbe, 0 },
339
340 /* The MB or ME field in an MD or MDS form instruction. The high
341 bit is wrapped to the low end. */
342#define MB6 MBE + 2
343#define ME6 MB6
344#define MB6_MASK (0x3f << 5)
345 { 6, 5, insert_mb6, extract_mb6, 0 },
346
347 /* The MO field in an mbar instruction. */
348#define MO MB6 + 1
349 { 5, 21, NULL, NULL, 0 },
350
351 /* The NB field in an X form instruction. The value 32 is stored as
352 0. */
353#define NB MO + 1
354 { 6, 11, insert_nb, extract_nb, 0 },
355
356 /* The NSI field in a D form instruction. This is the same as the
357 SI field, only negated. */
358#define NSI NB + 1
359 { 16, 0, insert_nsi, extract_nsi,
360 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
361
362 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
363#define RA NSI + 1
364#define RA_MASK (0x1f << 16)
365 { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
366
367 /* The RA field in the DQ form lq instruction, which has special
368 value restrictions. */
369#define RAQ RA + 1
370 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR },
371
372 /* The RA field in a D or X form instruction which is an updating
373 load, which means that the RA field may not be zero and may not
374 equal the RT field. */
375#define RAL RAQ + 1
376 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR },
377
378 /* The RA field in an lmw instruction, which has special value
379 restrictions. */
380#define RAM RAL + 1
381 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR },
382
383 /* The RA field in a D or X form instruction which is an updating
384 store or an updating floating point load, which means that the RA
385 field may not be zero. */
386#define RAS RAM + 1
387 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR },
388
389 /* The RB field in an X, XO, M, or MDS form instruction. */
390#define RB RAS + 1
391#define RB_MASK (0x1f << 11)
392 { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
393
394 /* The RB field in an X form instruction when it must be the same as
395 the RS field in the instruction. This is used for extended
396 mnemonics like mr. */
397#define RBS RB + 1
398 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
399
400 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
401 instruction or the RT field in a D, DS, X, XFX or XO form
402 instruction. */
403#define RS RBS + 1
404#define RT RS
405#define RT_MASK (0x1f << 21)
406 { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
407
408 /* The RS field of the DS form stq instruction, which has special
409 value restrictions. */
410#define RSQ RS + 1
411 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR },
412
413 /* The RT field of the DQ form lq instruction, which has special
414 value restrictions. */
415#define RTQ RSQ + 1
416 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR },
417
418 /* The SH field in an X or M form instruction. */
419#define SH RTQ + 1
420#define SH_MASK (0x1f << 11)
421 { 5, 11, NULL, NULL, 0 },
422
423 /* The SH field in an MD form instruction. This is split. */
424#define SH6 SH + 1
425#define SH6_MASK ((0x1f << 11) | (1 << 1))
426 { 6, 1, insert_sh6, extract_sh6, 0 },
427
428 /* The SI field in a D form instruction. */
429#define SI SH6 + 1
430 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
431
432 /* The SI field in a D form instruction when we accept a wide range
433 of positive values. */
434#define SISIGNOPT SI + 1
435 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
436
437 /* The SPR field in an XFX form instruction. This is flipped--the
438 lower 5 bits are stored in the upper 5 and vice- versa. */
439#define SPR SISIGNOPT + 1
440#define PMR SPR
441#define SPR_MASK (0x3ff << 11)
442 { 10, 11, insert_spr, extract_spr, 0 },
443
444 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
445#define SPRBAT SPR + 1
446#define SPRBAT_MASK (0x3 << 17)
447 { 2, 17, NULL, NULL, 0 },
448
449 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
450#define SPRG SPRBAT + 1
451#define SPRG_MASK (0x3 << 16)
452 { 2, 16, NULL, NULL, 0 },
453
454 /* The SR field in an X form instruction. */
455#define SR SPRG + 1
456 { 4, 16, NULL, NULL, 0 },
457
458 /* The STRM field in an X AltiVec form instruction. */
459#define STRM SR + 1
460#define STRM_MASK (0x3 << 21)
461 { 2, 21, NULL, NULL, 0 },
462
463 /* The SV field in a POWER SC form instruction. */
464#define SV STRM + 1
465 { 14, 2, NULL, NULL, 0 },
466
467 /* The TBR field in an XFX form instruction. This is like the SPR
468 field, but it is optional. */
469#define TBR SV + 1
470 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
471
472 /* The TO field in a D or X form instruction. */
473#define TO TBR + 1
474#define TO_MASK (0x1f << 21)
475 { 5, 21, NULL, NULL, 0 },
476
477 /* The U field in an X form instruction. */
478#define U TO + 1
479 { 4, 12, NULL, NULL, 0 },
480
481 /* The UI field in a D form instruction. */
482#define UI U + 1
483 { 16, 0, NULL, NULL, 0 },
484
485 /* The VA field in a VA, VX or VXR form instruction. */
486#define VA UI + 1
487#define VA_MASK (0x1f << 16)
488 { 5, 16, NULL, NULL, PPC_OPERAND_VR },
489
490 /* The VB field in a VA, VX or VXR form instruction. */
491#define VB VA + 1
492#define VB_MASK (0x1f << 11)
493 { 5, 11, NULL, NULL, PPC_OPERAND_VR },
494
495 /* The VC field in a VA form instruction. */
496#define VC VB + 1
497#define VC_MASK (0x1f << 6)
498 { 5, 6, NULL, NULL, PPC_OPERAND_VR },
499
500 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
501#define VD VC + 1
502#define VS VD
503#define VD_MASK (0x1f << 21)
504 { 5, 21, NULL, NULL, PPC_OPERAND_VR },
505
506 /* The SIMM field in a VX form instruction. */
507#define SIMM VD + 1
508 { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
509
510 /* The UIMM field in a VX form instruction. */
511#define UIMM SIMM + 1
512 { 5, 16, NULL, NULL, 0 },
513
514 /* The SHB field in a VA form instruction. */
515#define SHB UIMM + 1
516 { 4, 6, NULL, NULL, 0 },
517
518 /* The other UIMM field in a EVX form instruction. */
519#define EVUIMM SHB + 1
520 { 5, 11, NULL, NULL, 0 },
521
522 /* The other UIMM field in a half word EVX form instruction. */
523#define EVUIMM_2 EVUIMM + 1
524 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
525
526 /* The other UIMM field in a word EVX form instruction. */
527#define EVUIMM_4 EVUIMM_2 + 1
528 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
529
530 /* The other UIMM field in a double EVX form instruction. */
531#define EVUIMM_8 EVUIMM_4 + 1
532 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
533
534 /* The WS field. */
535#define WS EVUIMM_8 + 1
536#define WS_MASK (0x7 << 11)
537 { 3, 11, NULL, NULL, 0 },
538
539 /* The L field in an mtmsrd instruction */
540#define MTMSRD_L WS + 1
541 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
542
543};
544
545/* The functions used to insert and extract complicated operands. */
546
547/* The BA field in an XL form instruction when it must be the same as
548 the BT field in the same instruction. This operand is marked FAKE.
549 The insertion function just copies the BT field into the BA field,
550 and the extraction function just checks that the fields are the
551 same. */
552
553/*ARGSUSED*/
554static unsigned long
555insert_bat (unsigned long insn,
556 long value ATTRIBUTE_UNUSED,
557 int dialect ATTRIBUTE_UNUSED,
558 const char **errmsg ATTRIBUTE_UNUSED)
559{
560 return insn | (((insn >> 21) & 0x1f) << 16);
561}
562
563static long
564extract_bat (unsigned long insn,
565 int dialect ATTRIBUTE_UNUSED,
566 int *invalid)
567{
568 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
569 *invalid = 1;
570 return 0;
571}
572
573/* The BB field in an XL form instruction when it must be the same as
574 the BA field in the same instruction. This operand is marked FAKE.
575 The insertion function just copies the BA field into the BB field,
576 and the extraction function just checks that the fields are the
577 same. */
578
579/*ARGSUSED*/
580static unsigned long
581insert_bba (unsigned long insn,
582 long value ATTRIBUTE_UNUSED,
583 int dialect ATTRIBUTE_UNUSED,
584 const char **errmsg ATTRIBUTE_UNUSED)
585{
586 return insn | (((insn >> 16) & 0x1f) << 11);
587}
588
589static long
590extract_bba (unsigned long insn,
591 int dialect ATTRIBUTE_UNUSED,
592 int *invalid)
593{
594 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
595 *invalid = 1;
596 return 0;
597}
598
599/* The BD field in a B form instruction. The lower two bits are
600 forced to zero. */
601
602/*ARGSUSED*/
603static unsigned long
604insert_bd (unsigned long insn,
605 long value,
606 int dialect ATTRIBUTE_UNUSED,
607 const char **errmsg ATTRIBUTE_UNUSED)
608{
609 return insn | (value & 0xfffc);
610}
611
612/*ARGSUSED*/
613static long
614extract_bd (unsigned long insn,
615 int dialect ATTRIBUTE_UNUSED,
616 int *invalid ATTRIBUTE_UNUSED)
617{
618 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
619}
620
621/* The BD field in a B form instruction when the - modifier is used.
622 This modifier means that the branch is not expected to be taken.
623 For chips built to versions of the architecture prior to version 2
624 (ie. not Power4 compatible), we set the y bit of the BO field to 1
625 if the offset is negative. When extracting, we require that the y
626 bit be 1 and that the offset be positive, since if the y bit is 0
627 we just want to print the normal form of the instruction.
628 Power4 compatible targets use two bits, "a", and "t", instead of
629 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
630 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
631 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
632 for branch on CTR. We only handle the taken/not-taken hint here. */
633
634/*ARGSUSED*/
635static unsigned long
636insert_bdm (unsigned long insn,
637 long value,
638 int dialect,
639 const char **errmsg ATTRIBUTE_UNUSED)
640{
641 if ((dialect & PPC_OPCODE_POWER4) == 0)
642 {
643 if ((value & 0x8000) != 0)
644 insn |= 1 << 21;
645 }
646 else
647 {
648 if ((insn & (0x14 << 21)) == (0x04 << 21))
649 insn |= 0x02 << 21;
650 else if ((insn & (0x14 << 21)) == (0x10 << 21))
651 insn |= 0x08 << 21;
652 }
653 return insn | (value & 0xfffc);
654}
655
656static long
657extract_bdm (unsigned long insn,
658 int dialect,
659 int *invalid)
660{
661 if ((dialect & PPC_OPCODE_POWER4) == 0)
662 {
663 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
664 *invalid = 1;
665 }
666 else
667 {
668 if ((insn & (0x17 << 21)) != (0x06 << 21)
669 && (insn & (0x1d << 21)) != (0x18 << 21))
670 *invalid = 1;
671 }
672
673 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
674}
675
676/* The BD field in a B form instruction when the + modifier is used.
677 This is like BDM, above, except that the branch is expected to be
678 taken. */
679
680/*ARGSUSED*/
681static unsigned long
682insert_bdp (unsigned long insn,
683 long value,
684 int dialect,
685 const char **errmsg ATTRIBUTE_UNUSED)
686{
687 if ((dialect & PPC_OPCODE_POWER4) == 0)
688 {
689 if ((value & 0x8000) == 0)
690 insn |= 1 << 21;
691 }
692 else
693 {
694 if ((insn & (0x14 << 21)) == (0x04 << 21))
695 insn |= 0x03 << 21;
696 else if ((insn & (0x14 << 21)) == (0x10 << 21))
697 insn |= 0x09 << 21;
698 }
699 return insn | (value & 0xfffc);
700}
701
702static long
703extract_bdp (unsigned long insn,
704 int dialect,
705 int *invalid)
706{
707 if ((dialect & PPC_OPCODE_POWER4) == 0)
708 {
709 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
710 *invalid = 1;
711 }
712 else
713 {
714 if ((insn & (0x17 << 21)) != (0x07 << 21)
715 && (insn & (0x1d << 21)) != (0x19 << 21))
716 *invalid = 1;
717 }
718
719 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
720}
721
722/* Check for legal values of a BO field. */
723
724static int
725valid_bo (long value, int dialect)
726{
727 if ((dialect & PPC_OPCODE_POWER4) == 0)
728 {
729 /* Certain encodings have bits that are required to be zero.
730 These are (z must be zero, y may be anything):
731 001zy
732 011zy
733 1z00y
734 1z01y
735 1z1zz
736 */
737 switch (value & 0x14)
738 {
739 default:
740 case 0:
741 return 1;
742 case 0x4:
743 return (value & 0x2) == 0;
744 case 0x10:
745 return (value & 0x8) == 0;
746 case 0x14:
747 return value == 0x14;
748 }
749 }
750 else
751 {
752 /* Certain encodings have bits that are required to be zero.
753 These are (z must be zero, a & t may be anything):
754 0000z
755 0001z
756 0100z
757 0101z
758 001at
759 011at
760 1a00t
761 1a01t
762 1z1zz
763 */
764 if ((value & 0x14) == 0)
765 return (value & 0x1) == 0;
766 else if ((value & 0x14) == 0x14)
767 return value == 0x14;
768 else
769 return 1;
770 }
771}
772
773/* The BO field in a B form instruction. Warn about attempts to set
774 the field to an illegal value. */
775
776static unsigned long
777insert_bo (unsigned long insn,
778 long value,
779 int dialect,
780 const char **errmsg)
781{
782 if (!valid_bo (value, dialect))
783 *errmsg = _("invalid conditional option");
784 return insn | ((value & 0x1f) << 21);
785}
786
787static long
788extract_bo (unsigned long insn,
789 int dialect,
790 int *invalid)
791{
792 long value;
793
794 value = (insn >> 21) & 0x1f;
795 if (!valid_bo (value, dialect))
796 *invalid = 1;
797 return value;
798}
799
800/* The BO field in a B form instruction when the + or - modifier is
801 used. This is like the BO field, but it must be even. When
802 extracting it, we force it to be even. */
803
804static unsigned long
805insert_boe (unsigned long insn,
806 long value,
807 int dialect,
808 const char **errmsg)
809{
810 if (!valid_bo (value, dialect))
811 *errmsg = _("invalid conditional option");
812 else if ((value & 1) != 0)
813 *errmsg = _("attempt to set y bit when using + or - modifier");
814
815 return insn | ((value & 0x1f) << 21);
816}
817
818static long
819extract_boe (unsigned long insn,
820 int dialect,
821 int *invalid)
822{
823 long value;
824
825 value = (insn >> 21) & 0x1f;
826 if (!valid_bo (value, dialect))
827 *invalid = 1;
828 return value & 0x1e;
829}
830
831/* The DQ field in a DQ form instruction. This is like D, but the
832 lower four bits are forced to zero. */
833
834/*ARGSUSED*/
835static unsigned long
836insert_dq (unsigned long insn,
837 long value,
838 int dialect ATTRIBUTE_UNUSED,
839 const char **errmsg)
840{
841 if ((value & 0xf) != 0)
842 *errmsg = _("offset not a multiple of 16");
843 return insn | (value & 0xfff0);
844}
845
846/*ARGSUSED*/
847static long
848extract_dq (unsigned long insn,
849 int dialect ATTRIBUTE_UNUSED,
850 int *invalid ATTRIBUTE_UNUSED)
851{
852 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
853}
854
855static unsigned long
856insert_ev2 (unsigned long insn,
857 long value,
858 int dialect ATTRIBUTE_UNUSED,
859 const char **errmsg)
860{
861 if ((value & 1) != 0)
862 *errmsg = _("offset not a multiple of 2");
863 if ((value > 62) != 0)
864 *errmsg = _("offset greater than 62");
865 return insn | ((value & 0x3e) << 10);
866}
867
868static long
869extract_ev2 (unsigned long insn,
870 int dialect ATTRIBUTE_UNUSED,
871 int *invalid ATTRIBUTE_UNUSED)
872{
873 return (insn >> 10) & 0x3e;
874}
875
876static unsigned long
877insert_ev4 (unsigned long insn,
878 long value,
879 int dialect ATTRIBUTE_UNUSED,
880 const char **errmsg)
881{
882 if ((value & 3) != 0)
883 *errmsg = _("offset not a multiple of 4");
884 if ((value > 124) != 0)
885 *errmsg = _("offset greater than 124");
886 return insn | ((value & 0x7c) << 9);
887}
888
889static long
890extract_ev4 (unsigned long insn,
891 int dialect ATTRIBUTE_UNUSED,
892 int *invalid ATTRIBUTE_UNUSED)
893{
894 return (insn >> 9) & 0x7c;
895}
896
897static unsigned long
898insert_ev8 (unsigned long insn,
899 long value,
900 int dialect ATTRIBUTE_UNUSED,
901 const char **errmsg)
902{
903 if ((value & 7) != 0)
904 *errmsg = _("offset not a multiple of 8");
905 if ((value > 248) != 0)
906 *errmsg = _("offset greater than 248");
907 return insn | ((value & 0xf8) << 8);
908}
909
910static long
911extract_ev8 (unsigned long insn,
912 int dialect ATTRIBUTE_UNUSED,
913 int *invalid ATTRIBUTE_UNUSED)
914{
915 return (insn >> 8) & 0xf8;
916}
917
918/* The DS field in a DS form instruction. This is like D, but the
919 lower two bits are forced to zero. */
920
921/*ARGSUSED*/
922static unsigned long
923insert_ds (unsigned long insn,
924 long value,
925 int dialect ATTRIBUTE_UNUSED,
926 const char **errmsg)
927{
928 if ((value & 3) != 0)
929 *errmsg = _("offset not a multiple of 4");
930 return insn | (value & 0xfffc);
931}
932
933/*ARGSUSED*/
934static long
935extract_ds (unsigned long insn,
936 int dialect ATTRIBUTE_UNUSED,
937 int *invalid ATTRIBUTE_UNUSED)
938{
939 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
940}
941
942/* The DE field in a DE form instruction. */
943
944/*ARGSUSED*/
945static unsigned long
946insert_de (unsigned long insn,
947 long value,
948 int dialect ATTRIBUTE_UNUSED,
949 const char **errmsg)
950{
951 if (value > 2047 || value < -2048)
952 *errmsg = _("offset not between -2048 and 2047");
953 return insn | ((value << 4) & 0xfff0);
954}
955
956/*ARGSUSED*/
957static long
958extract_de (unsigned long insn,
959 int dialect ATTRIBUTE_UNUSED,
960 int *invalid ATTRIBUTE_UNUSED)
961{
962 return (insn & 0xfff0) >> 4;
963}
964
965/* The DES field in a DES form instruction. */
966
967/*ARGSUSED*/
968static unsigned long
969insert_des (unsigned long insn,
970 long value,
971 int dialect ATTRIBUTE_UNUSED,
972 const char **errmsg)
973{
974 if (value > 8191 || value < -8192)
975 *errmsg = _("offset not between -8192 and 8191");
976 else if ((value & 3) != 0)
977 *errmsg = _("offset not a multiple of 4");
978 return insn | ((value << 2) & 0xfff0);
979}
980
981/*ARGSUSED*/
982static long
983extract_des (unsigned long insn,
984 int dialect ATTRIBUTE_UNUSED,
985 int *invalid ATTRIBUTE_UNUSED)
986{
987 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
988}
989
990/* FXM mask in mfcr and mtcrf instructions. */
991
992static unsigned long
993insert_fxm (unsigned long insn,
994 long value,
995 int dialect,
996 const char **errmsg)
997{
998 /* If the optional field on mfcr is missing that means we want to use
999 the old form of the instruction that moves the whole cr. In that
1000 case we'll have VALUE zero. There doesn't seem to be a way to
1001 distinguish this from the case where someone writes mfcr %r3,0. */
1002 if (value == 0)
1003 ;
1004
1005 /* If only one bit of the FXM field is set, we can use the new form
1006 of the instruction, which is faster. Unlike the Power4 branch hint
1007 encoding, this is not backward compatible. */
1008 else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
1009 insn |= 1 << 20;
1010
1011 /* Any other value on mfcr is an error. */
1012 else if ((insn & (0x3ff << 1)) == 19 << 1)
1013 {
1014 *errmsg = _("ignoring invalid mfcr mask");
1015 value = 0;
1016 }
1017
1018 return insn | ((value & 0xff) << 12);
1019}
1020
1021static long
1022extract_fxm (unsigned long insn,
1023 int dialect,
1024 int *invalid)
1025{
1026 long mask = (insn >> 12) & 0xff;
1027
1028 /* Is this a Power4 insn? */
1029 if ((insn & (1 << 20)) != 0)
1030 {
1031 if ((dialect & PPC_OPCODE_POWER4) == 0)
1032 *invalid = 1;
1033 else
1034 {
1035 /* Exactly one bit of MASK should be set. */
1036 if (mask == 0 || (mask & -mask) != mask)
1037 *invalid = 1;
1038 }
1039 }
1040
1041 /* Check that non-power4 form of mfcr has a zero MASK. */
1042 else if ((insn & (0x3ff << 1)) == 19 << 1)
1043 {
1044 if (mask != 0)
1045 *invalid = 1;
1046 }
1047
1048 return mask;
1049}
1050
1051/* The LI field in an I form instruction. The lower two bits are
1052 forced to zero. */
1053
1054/*ARGSUSED*/
1055static unsigned long
1056insert_li (unsigned long insn,
1057 long value,
1058 int dialect ATTRIBUTE_UNUSED,
1059 const char **errmsg)
1060{
1061 if ((value & 3) != 0)
1062 *errmsg = _("ignoring least significant bits in branch offset");
1063 return insn | (value & 0x3fffffc);
1064}
1065
1066/*ARGSUSED*/
1067static long
1068extract_li (unsigned long insn,
1069 int dialect ATTRIBUTE_UNUSED,
1070 int *invalid ATTRIBUTE_UNUSED)
1071{
1072 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1073}
1074
1075/* The MB and ME fields in an M form instruction expressed as a single
1076 operand which is itself a bitmask. The extraction function always
1077 marks it as invalid, since we never want to recognize an
1078 instruction which uses a field of this type. */
1079
1080static unsigned long
1081insert_mbe (unsigned long insn,
1082 long value,
1083 int dialect ATTRIBUTE_UNUSED,
1084 const char **errmsg)
1085{
1086 unsigned long uval, mask;
1087 int mb, me, mx, count, last;
1088
1089 uval = value;
1090
1091 if (uval == 0)
1092 {
1093 *errmsg = _("illegal bitmask");
1094 return insn;
1095 }
1096
1097 mb = 0;
1098 me = 32;
1099 if ((uval & 1) != 0)
1100 last = 1;
1101 else
1102 last = 0;
1103 count = 0;
1104
1105 /* mb: location of last 0->1 transition */
1106 /* me: location of last 1->0 transition */
1107 /* count: # transitions */
1108
1109 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1110 {
1111 if ((uval & mask) && !last)
1112 {
1113 ++count;
1114 mb = mx;
1115 last = 1;
1116 }
1117 else if (!(uval & mask) && last)
1118 {
1119 ++count;
1120 me = mx;
1121 last = 0;
1122 }
1123 }
1124 if (me == 0)
1125 me = 32;
1126
1127 if (count != 2 && (count != 0 || ! last))
1128 *errmsg = _("illegal bitmask");
1129
1130 return insn | (mb << 6) | ((me - 1) << 1);
1131}
1132
1133static long
1134extract_mbe (unsigned long insn,
1135 int dialect ATTRIBUTE_UNUSED,
1136 int *invalid)
1137{
1138 long ret;
1139 int mb, me;
1140 int i;
1141
1142 *invalid = 1;
1143
1144 mb = (insn >> 6) & 0x1f;
1145 me = (insn >> 1) & 0x1f;
1146 if (mb < me + 1)
1147 {
1148 ret = 0;
1149 for (i = mb; i <= me; i++)
1150 ret |= 1L << (31 - i);
1151 }
1152 else if (mb == me + 1)
1153 ret = ~0;
1154 else /* (mb > me + 1) */
1155 {
1156 ret = ~0;
1157 for (i = me + 1; i < mb; i++)
1158 ret &= ~(1L << (31 - i));
1159 }
1160 return ret;
1161}
1162
1163/* The MB or ME field in an MD or MDS form instruction. The high bit
1164 is wrapped to the low end. */
1165
1166/*ARGSUSED*/
1167static unsigned long
1168insert_mb6 (unsigned long insn,
1169 long value,
1170 int dialect ATTRIBUTE_UNUSED,
1171 const char **errmsg ATTRIBUTE_UNUSED)
1172{
1173 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1174}
1175
1176/*ARGSUSED*/
1177static long
1178extract_mb6 (unsigned long insn,
1179 int dialect ATTRIBUTE_UNUSED,
1180 int *invalid ATTRIBUTE_UNUSED)
1181{
1182 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1183}
1184
1185/* The NB field in an X form instruction. The value 32 is stored as
1186 0. */
1187
1188static unsigned long
1189insert_nb (unsigned long insn,
1190 long value,
1191 int dialect ATTRIBUTE_UNUSED,
1192 const char **errmsg)
1193{
1194 if (value < 0 || value > 32)
1195 *errmsg = _("value out of range");
1196 if (value == 32)
1197 value = 0;
1198 return insn | ((value & 0x1f) << 11);
1199}
1200
1201/*ARGSUSED*/
1202static long
1203extract_nb (unsigned long insn,
1204 int dialect ATTRIBUTE_UNUSED,
1205 int *invalid ATTRIBUTE_UNUSED)
1206{
1207 long ret;
1208
1209 ret = (insn >> 11) & 0x1f;
1210 if (ret == 0)
1211 ret = 32;
1212 return ret;
1213}
1214
1215/* The NSI field in a D form instruction. This is the same as the SI
1216 field, only negated. The extraction function always marks it as
1217 invalid, since we never want to recognize an instruction which uses
1218 a field of this type. */
1219
1220/*ARGSUSED*/
1221static unsigned long
1222insert_nsi (unsigned long insn,
1223 long value,
1224 int dialect ATTRIBUTE_UNUSED,
1225 const char **errmsg ATTRIBUTE_UNUSED)
1226{
1227 return insn | (-value & 0xffff);
1228}
1229
1230static long
1231extract_nsi (unsigned long insn,
1232 int dialect ATTRIBUTE_UNUSED,
1233 int *invalid)
1234{
1235 *invalid = 1;
1236 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1237}
1238
1239/* The RA field in a D or X form instruction which is an updating
1240 load, which means that the RA field may not be zero and may not
1241 equal the RT field. */
1242
1243static unsigned long
1244insert_ral (unsigned long insn,
1245 long value,
1246 int dialect ATTRIBUTE_UNUSED,
1247 const char **errmsg)
1248{
1249 if (value == 0
1250 || (unsigned long) value == ((insn >> 21) & 0x1f))
1251 *errmsg = "invalid register operand when updating";
1252 return insn | ((value & 0x1f) << 16);
1253}
1254
1255/* The RA field in an lmw instruction, which has special value
1256 restrictions. */
1257
1258static unsigned long
1259insert_ram (unsigned long insn,
1260 long value,
1261 int dialect ATTRIBUTE_UNUSED,
1262 const char **errmsg)
1263{
1264 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1265 *errmsg = _("index register in load range");
1266 return insn | ((value & 0x1f) << 16);
1267}
1268
1269/* The RA field in the DQ form lq instruction, which has special
1270 value restrictions. */
1271
1272/*ARGSUSED*/
1273static unsigned long
1274insert_raq (unsigned long insn,
1275 long value,
1276 int dialect ATTRIBUTE_UNUSED,
1277 const char **errmsg)
1278{
1279 long rtvalue = (insn & RT_MASK) >> 21;
1280
1281 if (value == rtvalue)
1282 *errmsg = _("source and target register operands must be different");
1283 return insn | ((value & 0x1f) << 16);
1284}
1285
1286/* The RA field in a D or X form instruction which is an updating
1287 store or an updating floating point load, which means that the RA
1288 field may not be zero. */
1289
1290static unsigned long
1291insert_ras (unsigned long insn,
1292 long value,
1293 int dialect ATTRIBUTE_UNUSED,
1294 const char **errmsg)
1295{
1296 if (value == 0)
1297 *errmsg = _("invalid register operand when updating");
1298 return insn | ((value & 0x1f) << 16);
1299}
1300
1301/* The RB field in an X form instruction when it must be the same as
1302 the RS field in the instruction. This is used for extended
1303 mnemonics like mr. This operand is marked FAKE. The insertion
1304 function just copies the BT field into the BA field, and the
1305 extraction function just checks that the fields are the same. */
1306
1307/*ARGSUSED*/
1308static unsigned long
1309insert_rbs (unsigned long insn,
1310 long value ATTRIBUTE_UNUSED,
1311 int dialect ATTRIBUTE_UNUSED,
1312 const char **errmsg ATTRIBUTE_UNUSED)
1313{
1314 return insn | (((insn >> 21) & 0x1f) << 11);
1315}
1316
1317static long
1318extract_rbs (unsigned long insn,
1319 int dialect ATTRIBUTE_UNUSED,
1320 int *invalid)
1321{
1322 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1323 *invalid = 1;
1324 return 0;
1325}
1326
1327/* The RT field of the DQ form lq instruction, which has special
1328 value restrictions. */
1329
1330/*ARGSUSED*/
1331static unsigned long
1332insert_rtq (unsigned long insn,
1333 long value,
1334 int dialect ATTRIBUTE_UNUSED,
1335 const char **errmsg)
1336{
1337 if ((value & 1) != 0)
1338 *errmsg = _("target register operand must be even");
1339 return insn | ((value & 0x1f) << 21);
1340}
1341
1342/* The RS field of the DS form stq instruction, which has special
1343 value restrictions. */
1344
1345/*ARGSUSED*/
1346static unsigned long
1347insert_rsq (unsigned long insn,
1348 long value ATTRIBUTE_UNUSED,
1349 int dialect ATTRIBUTE_UNUSED,
1350 const char **errmsg)
1351{
1352 if ((value & 1) != 0)
1353 *errmsg = _("source register operand must be even");
1354 return insn | ((value & 0x1f) << 21);
1355}
1356
1357/* The SH field in an MD form instruction. This is split. */
1358
1359/*ARGSUSED*/
1360static unsigned long
1361insert_sh6 (unsigned long insn,
1362 long value,
1363 int dialect ATTRIBUTE_UNUSED,
1364 const char **errmsg ATTRIBUTE_UNUSED)
1365{
1366 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1367}
1368
1369/*ARGSUSED*/
1370static long
1371extract_sh6 (unsigned long insn,
1372 int dialect ATTRIBUTE_UNUSED,
1373 int *invalid ATTRIBUTE_UNUSED)
1374{
1375 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1376}
1377
1378/* The SPR field in an XFX form instruction. This is flipped--the
1379 lower 5 bits are stored in the upper 5 and vice- versa. */
1380
1381static unsigned long
1382insert_spr (unsigned long insn,
1383 long value,
1384 int dialect ATTRIBUTE_UNUSED,
1385 const char **errmsg ATTRIBUTE_UNUSED)
1386{
1387 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1388}
1389
1390static long
1391extract_spr (unsigned long insn,
1392 int dialect ATTRIBUTE_UNUSED,
1393 int *invalid ATTRIBUTE_UNUSED)
1394{
1395 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1396}
1397
1398/* The TBR field in an XFX instruction. This is just like SPR, but it
1399 is optional. When TBR is omitted, it must be inserted as 268 (the
1400 magic number of the TB register). These functions treat 0
1401 (indicating an omitted optional operand) as 268. This means that
1402 ``mftb 4,0'' is not handled correctly. This does not matter very
1403 much, since the architecture manual does not define mftb as
1404 accepting any values other than 268 or 269. */
1405
1406#define TB (268)
1407
1408static unsigned long
1409insert_tbr (unsigned long insn,
1410 long value,
1411 int dialect ATTRIBUTE_UNUSED,
1412 const char **errmsg ATTRIBUTE_UNUSED)
1413{
1414 if (value == 0)
1415 value = TB;
1416 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1417}
1418
1419static long
1420extract_tbr (unsigned long insn,
1421 int dialect ATTRIBUTE_UNUSED,
1422 int *invalid ATTRIBUTE_UNUSED)
1423{
1424 long ret;
1425
1426 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1427 if (ret == TB)
1428 ret = 0;
1429 return ret;
1430}
1431
1432/* Macros used to form opcodes. */
1433
1434/* The main opcode. */
1435#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1436#define OP_MASK OP (0x3f)
1437
1438/* The main opcode combined with a trap code in the TO field of a D
1439 form instruction. Used for extended mnemonics for the trap
1440 instructions. */
1441#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1442#define OPTO_MASK (OP_MASK | TO_MASK)
1443
1444/* The main opcode combined with a comparison size bit in the L field
1445 of a D form or X form instruction. Used for extended mnemonics for
1446 the comparison instructions. */
1447#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1448#define OPL_MASK OPL (0x3f,1)
1449
1450/* An A form instruction. */
1451#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1452#define A_MASK A (0x3f, 0x1f, 1)
1453
1454/* An A_MASK with the FRB field fixed. */
1455#define AFRB_MASK (A_MASK | FRB_MASK)
1456
1457/* An A_MASK with the FRC field fixed. */
1458#define AFRC_MASK (A_MASK | FRC_MASK)
1459
1460/* An A_MASK with the FRA and FRC fields fixed. */
1461#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1462
1463/* A B form instruction. */
1464#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1465#define B_MASK B (0x3f, 1, 1)
1466
1467/* A B form instruction setting the BO field. */
1468#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1469#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1470
1471/* A BBO_MASK with the y bit of the BO field removed. This permits
1472 matching a conditional branch regardless of the setting of the y
1473 bit. Similarly for the 'at' bits used for power4 branch hints. */
1474#define Y_MASK (((unsigned long) 1) << 21)
1475#define AT1_MASK (((unsigned long) 3) << 21)
1476#define AT2_MASK (((unsigned long) 9) << 21)
1477#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1478#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1479
1480/* A B form instruction setting the BO field and the condition bits of
1481 the BI field. */
1482#define BBOCB(op, bo, cb, aa, lk) \
1483 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1484#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1485
1486/* A BBOCB_MASK with the y bit of the BO field removed. */
1487#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1488#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1489#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1490
1491/* A BBOYCB_MASK in which the BI field is fixed. */
1492#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1493#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1494
1495/* An Context form instruction. */
1496#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1497#define CTX_MASK CTX(0x3f, 0x7)
1498
1499/* An User Context form instruction. */
1500#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1501#define UCTX_MASK UCTX(0x3f, 0x1f)
1502
1503/* The main opcode mask with the RA field clear. */
1504#define DRA_MASK (OP_MASK | RA_MASK)
1505
1506/* A DS form instruction. */
1507#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1508#define DS_MASK DSO (0x3f, 3)
1509
1510/* A DE form instruction. */
1511#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1512#define DE_MASK DEO (0x3e, 0xf)
1513
1514/* An EVSEL form instruction. */
1515#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1516#define EVSEL_MASK EVSEL(0x3f, 0xff)
1517
1518/* An M form instruction. */
1519#define M(op, rc) (OP (op) | ((rc) & 1))
1520#define M_MASK M (0x3f, 1)
1521
1522/* An M form instruction with the ME field specified. */
1523#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1524
1525/* An M_MASK with the MB and ME fields fixed. */
1526#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1527
1528/* An M_MASK with the SH and ME fields fixed. */
1529#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1530
1531/* An MD form instruction. */
1532#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1533#define MD_MASK MD (0x3f, 0x7, 1)
1534
1535/* An MD_MASK with the MB field fixed. */
1536#define MDMB_MASK (MD_MASK | MB6_MASK)
1537
1538/* An MD_MASK with the SH field fixed. */
1539#define MDSH_MASK (MD_MASK | SH6_MASK)
1540
1541/* An MDS form instruction. */
1542#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1543#define MDS_MASK MDS (0x3f, 0xf, 1)
1544
1545/* An MDS_MASK with the MB field fixed. */
1546#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1547
1548/* An SC form instruction. */
1549#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1550#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1551
1552/* An VX form instruction. */
1553#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1554
1555/* The mask for an VX form instruction. */
1556#define VX_MASK VX(0x3f, 0x7ff)
1557
1558/* An VA form instruction. */
1559#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1560
1561/* The mask for an VA form instruction. */
1562#define VXA_MASK VXA(0x3f, 0x3f)
1563
1564/* An VXR form instruction. */
1565#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1566
1567/* The mask for a VXR form instruction. */
1568#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1569
1570/* An X form instruction. */
1571#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1572
1573/* An X form instruction with the RC bit specified. */
1574#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1575
1576/* The mask for an X form instruction. */
1577#define X_MASK XRC (0x3f, 0x3ff, 1)
1578
1579/* An X_MASK with the RA field fixed. */
1580#define XRA_MASK (X_MASK | RA_MASK)
1581
1582/* An X_MASK with the RB field fixed. */
1583#define XRB_MASK (X_MASK | RB_MASK)
1584
1585/* An X_MASK with the RT field fixed. */
1586#define XRT_MASK (X_MASK | RT_MASK)
1587
1588/* An X_MASK with the RA and RB fields fixed. */
1589#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1590
1591/* An XRARB_MASK, but with the L bit clear. */
1592#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1593
1594/* An X_MASK with the RT and RA fields fixed. */
1595#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1596
1597/* An XRTRA_MASK, but with L bit clear. */
1598#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1599
1600/* An X form comparison instruction. */
1601#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1602
1603/* The mask for an X form comparison instruction. */
1604#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1605
1606/* The mask for an X form comparison instruction with the L field
1607 fixed. */
1608#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1609
1610/* An X form trap instruction with the TO field specified. */
1611#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1612#define XTO_MASK (X_MASK | TO_MASK)
1613
1614/* An X form tlb instruction with the SH field specified. */
1615#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1616#define XTLB_MASK (X_MASK | SH_MASK)
1617
1618/* An X form sync instruction. */
1619#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1620
1621/* An X form sync instruction with everything filled in except the LS field. */
1622#define XSYNC_MASK (0xff9fffff)
1623
1624/* An X form AltiVec dss instruction. */
1625#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1626#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1627
1628/* An XFL form instruction. */
1629#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1630#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1631
1632/* An X form isel instruction. */
1633#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1634#define XISEL_MASK XISEL(0x3f, 0x1f)
1635
1636/* An XL form instruction with the LK field set to 0. */
1637#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1638
1639/* An XL form instruction which uses the LK field. */
1640#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1641
1642/* The mask for an XL form instruction. */
1643#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1644
1645/* An XL form instruction which explicitly sets the BO field. */
1646#define XLO(op, bo, xop, lk) \
1647 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1648#define XLO_MASK (XL_MASK | BO_MASK)
1649
1650/* An XL form instruction which explicitly sets the y bit of the BO
1651 field. */
1652#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1653#define XLYLK_MASK (XL_MASK | Y_MASK)
1654
1655/* An XL form instruction which sets the BO field and the condition
1656 bits of the BI field. */
1657#define XLOCB(op, bo, cb, xop, lk) \
1658 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1659#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1660
1661/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1662#define XLBB_MASK (XL_MASK | BB_MASK)
1663#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1664#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1665
1666/* An XL_MASK with the BO and BB fields fixed. */
1667#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1668
1669/* An XL_MASK with the BO, BI and BB fields fixed. */
1670#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1671
1672/* An XO form instruction. */
1673#define XO(op, xop, oe, rc) \
1674 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1675#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1676
1677/* An XO_MASK with the RB field fixed. */
1678#define XORB_MASK (XO_MASK | RB_MASK)
1679
1680/* An XS form instruction. */
1681#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1682#define XS_MASK XS (0x3f, 0x1ff, 1)
1683
1684/* A mask for the FXM version of an XFX form instruction. */
1685#define XFXFXM_MASK (X_MASK | (1 << 11))
1686
1687/* An XFX form instruction with the FXM field filled in. */
1688#define XFXM(op, xop, fxm) \
1689 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1690
1691/* An XFX form instruction with the SPR field filled in. */
1692#define XSPR(op, xop, spr) \
1693 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1694#define XSPR_MASK (X_MASK | SPR_MASK)
1695
1696/* An XFX form instruction with the SPR field filled in except for the
1697 SPRBAT field. */
1698#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1699
1700/* An XFX form instruction with the SPR field filled in except for the
1701 SPRG field. */
1702#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1703
1704/* An X form instruction with everything filled in except the E field. */
1705#define XE_MASK (0xffff7fff)
1706
1707/* An X form user context instruction. */
1708#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1709#define XUC_MASK XUC(0x3f, 0x1f)
1710
1711/* The BO encodings used in extended conditional branch mnemonics. */
1712#define BODNZF (0x0)
1713#define BODNZFP (0x1)
1714#define BODZF (0x2)
1715#define BODZFP (0x3)
1716#define BODNZT (0x8)
1717#define BODNZTP (0x9)
1718#define BODZT (0xa)
1719#define BODZTP (0xb)
1720
1721#define BOF (0x4)
1722#define BOFP (0x5)
1723#define BOFM4 (0x6)
1724#define BOFP4 (0x7)
1725#define BOT (0xc)
1726#define BOTP (0xd)
1727#define BOTM4 (0xe)
1728#define BOTP4 (0xf)
1729
1730#define BODNZ (0x10)
1731#define BODNZP (0x11)
1732#define BODZ (0x12)
1733#define BODZP (0x13)
1734#define BODNZM4 (0x18)
1735#define BODNZP4 (0x19)
1736#define BODZM4 (0x1a)
1737#define BODZP4 (0x1b)
1738
1739#define BOU (0x14)
1740
1741/* The BI condition bit encodings used in extended conditional branch
1742 mnemonics. */
1743#define CBLT (0)
1744#define CBGT (1)
1745#define CBEQ (2)
1746#define CBSO (3)
1747
1748/* The TO encodings used in extended trap mnemonics. */
1749#define TOLGT (0x1)
1750#define TOLLT (0x2)
1751#define TOEQ (0x4)
1752#define TOLGE (0x5)
1753#define TOLNL (0x5)
1754#define TOLLE (0x6)
1755#define TOLNG (0x6)
1756#define TOGT (0x8)
1757#define TOGE (0xc)
1758#define TONL (0xc)
1759#define TOLT (0x10)
1760#define TOLE (0x14)
1761#define TONG (0x14)
1762#define TONE (0x18)
1763#define TOU (0x1f)
1764
1765/* Smaller names for the flags so each entry in the opcodes table will
1766 fit on a single line. */
1767#undef PPC
1768#define PPC PPC_OPCODE_PPC
1769#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1770#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1771#define POWER4 PPC_OPCODE_POWER4
1772#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1773#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1774#define PPC403 PPC_OPCODE_403
1775#define PPC405 PPC403
1776#define PPC440 PPC_OPCODE_440
1777#define PPC750 PPC
1778#define PPC860 PPC
1779#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
1780#define POWER PPC_OPCODE_POWER
1781#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1782#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1783#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1784#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1785#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1786#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1787#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1788#define MFDEC1 PPC_OPCODE_POWER
1789#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1790#define BOOKE PPC_OPCODE_BOOKE
1791#define BOOKE64 PPC_OPCODE_BOOKE64
1792#define CLASSIC PPC_OPCODE_CLASSIC
1793#define PPCSPE PPC_OPCODE_SPE
1794#define PPCISEL PPC_OPCODE_ISEL
1795#define PPCEFS PPC_OPCODE_EFS
1796#define PPCBRLK PPC_OPCODE_BRLOCK
1797#define PPCPMR PPC_OPCODE_PMR
1798#define PPCCHLK PPC_OPCODE_CACHELCK
1799#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1800#define PPCRFMCI PPC_OPCODE_RFMCI
1801
1802/* The opcode table.
1803
1804 The format of the opcode table is:
1805
1806 NAME OPCODE MASK FLAGS { OPERANDS }
1807
1808 NAME is the name of the instruction.
1809 OPCODE is the instruction opcode.
1810 MASK is the opcode mask; this is used to tell the disassembler
1811 which bits in the actual opcode must match OPCODE.
1812 FLAGS are flags indicated what processors support the instruction.
1813 OPERANDS is the list of operands.
1814
1815 The disassembler reads the table in order and prints the first
1816 instruction which matches, so this table is sorted to put more
1817 specific instructions before more general instructions. It is also
1818 sorted by major opcode. */
1819
1820const struct powerpc_opcode powerpc_opcodes[] = {
1821{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
1822{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1823{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1824{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1825{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1826{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1827{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1828{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1829{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1830{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1831{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1832{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1833{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1834{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1835{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1836{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1837
1838{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1839{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1840{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1841{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1842{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1843{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1844{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1845{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1846{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1847{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1848{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1849{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1850{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1851{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1852{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1853{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1854{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1855{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1856{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1857{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1858{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1859{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1860{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1861{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1862{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1863{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1864{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1865{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1866{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1867{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1868
1869{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1870{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1871{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1872{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1873{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1874{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1875{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1876{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1877{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1878{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1879{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1880{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1881{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1882{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1883{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1884{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1885{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1886{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1887{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1888{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1889{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1890{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1891{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1892{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1893{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1894{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1895{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1896{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1897{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1898{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1899{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1900{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1901{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1902{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1903{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1904{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1905{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1906{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1907{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1908{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1909{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1910{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1911{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1912{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1913{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1914{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1915{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1916{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1917{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1918{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1919{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1920{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1921{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1922{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1923{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1924{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1925{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1926{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1927{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1928{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1929{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1930{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1931{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1932{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1933{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1934{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1935{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1936{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1937{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1938{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1939{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1940{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1941{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1942{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1943{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1944{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1945{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1946{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1947{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1948{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1949{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1950{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1951{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1952{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1953{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1954{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1955{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1956{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1957{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1958{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1959{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1960{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1961{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1962{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1963{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1964{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1965{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1966{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1967{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1968{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1969{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1970{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1971{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1972{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1973{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1974{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1975{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1976{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1977{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1978{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1979{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1980{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1981{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1982{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1983{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1984{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1985{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1986{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1987{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1988{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1989{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1990{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1991{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1992{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1993{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1994{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1995{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1996{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1997{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1998{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1999{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2000{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2001{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2002{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2003{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2004{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2005{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2006{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2007{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2008{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2009{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2010{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2011{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2012{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2013{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2014{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2015{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2016{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2017{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2018{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2019{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2020{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2021{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2022{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2023{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2024{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2025{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2026{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2027{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2028{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2029{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2030{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2031{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2032{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2033{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2034{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2035{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2036{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2037{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2038{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2039{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2040{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2041{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2042{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2043{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2044{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2045{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2046{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2047{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2048{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2049{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2050{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2051{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2052{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2053{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2054{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2055{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2056{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2057{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2058{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2059{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2060{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2061{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2062{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2063{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2064{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2065{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2066{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2067{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2068{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2069{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2070{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2071{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2072{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2073{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2074{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2075{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2076{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2077{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2078{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2079{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2080{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2081{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2082{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2083{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2084{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2085{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2086{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2087{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2088{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2089{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2090{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2091{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2092{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2093{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2094{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2095{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2096{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2097{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2098{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2099{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2100{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2101{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2102{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2103{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2104{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2105{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2106{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2107{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2108{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2109{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2110
2111{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2112{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2113{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2114{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2115{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2116{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2117{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2118{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2119{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2120{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2121{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2122{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2123{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2124
2125{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2126
2127{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2128{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2129{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2130{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2131{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2132{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2133{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2134{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2135{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2136{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2137
2138{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2139{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2140{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2141{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2142{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2143{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2144{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2145{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2146{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2147{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2148{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2149{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2150{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2151{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2152
2153{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2154{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2155{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2156{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2157{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2158{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2159
2160{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2161{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2162{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2163{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2164{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2165{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2166{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2167{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2168{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2169{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2170{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2171{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2172{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2173{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2174{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2175{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2176{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2177{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2178{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2179{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2180{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2181{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2182
2183{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2184{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2185{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2186{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2187{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2188{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2189{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2190{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2191{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2192{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2193{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2194{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2195{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2196{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2197
2198{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2199{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2200{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2201{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2202{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2203{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2204{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2205{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2206{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2207{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2208{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2209{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2210{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2211{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2212{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2213{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2214{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2215{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2216{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2217{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2218{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2219{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2220{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2221
2222{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2223{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2224{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2225{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2226{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2227{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2228{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2229{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2230{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2231{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2232{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2233{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2234{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2235{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2236{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2237{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2238{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2239{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2240{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2241{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2242{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2243{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2244{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2245
2246{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2247{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2248{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2249{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2250{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2251{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2252{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2253{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2254{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2255{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2256{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2257{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2258{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2259{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2260{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2261{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2262
2263{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2264{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2265{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2266{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2267{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2268{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2269{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2270{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2271{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2272{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2273{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2274{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2275
2276{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2277{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2278{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2279{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2280{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2281{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2282{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2283{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2284{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2285{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2286{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2287{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2288
2289{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2290{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2291{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2292{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2293{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2294{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2295
2296{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2297{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2298{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2299{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2300{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2301{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2302
2303{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2304{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2305{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2306{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2307{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2308{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2309{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2310{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2311
2312{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2313{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2314
2315{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2316{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2317{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2318{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2319
2320{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2321{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2322{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2323{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2324
2325{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2326{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2327{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2328{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2329{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2330{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2331{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2332{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2333
2334{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2335{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2336{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2337{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2338
2339{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2340{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2341{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2342{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2343
2344{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2345{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2346{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2347{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2348
2349{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2350{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2351{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2352{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2353
2354{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2355
2356{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2357{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2358
2359{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2360{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2361
2362{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2363{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2364
2365{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2366
2367{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2368{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2369{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2370{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2371
2372{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2373{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2374{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2375{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2376
2377{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2378{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2379{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2380{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2381
2382{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2383{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2384{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2385
2386{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2387{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2388{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2389
2390{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2391{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2392{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
2393{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
2394{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
2395{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
2396
2397{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2398{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2399{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
2400{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
2401{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
2402
2403{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2404{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2405{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2406{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2407{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2408{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2409{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2410{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2411{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2412{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2413{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2414{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2415{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2416{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2417{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2418{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2419{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2420{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2421{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2422{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2423{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2424{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2425{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2426{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2427{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2428{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2429{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2430{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2431{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2432{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2433{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2434{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2435{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2436{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2437{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2438{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2439{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2440{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2441{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2442{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2443{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2444{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2445{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2446{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2447{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2448{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2449{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2450{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2451{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2452{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2453{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2454{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2455{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2456{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2457{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2458{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2459{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2460{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2461{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2462{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2463{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2464{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2465{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2466{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2467{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2468{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2469{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2470{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2471{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2472{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2473{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2474{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2475{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2476{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2477{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2478{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2479{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2480{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2481{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2482{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2483{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2484{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2485{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2486{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2487{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2488{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2489{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2490{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2491{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2492{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2493{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2494{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2495{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2496{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2497{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2498{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2499{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2500{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2501{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2502{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2503{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2504{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2505{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2506{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2507{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2508{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2509{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2510{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2511{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2512{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2513{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2514{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2515{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2516{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2517{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2518{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2519{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2520{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2521{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2522{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2523{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2524{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2525{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2526{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2527{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2528{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2529{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2530{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2531{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2532{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2533{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2534{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2535{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2536{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2537{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2538{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2539{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2540{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2541{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2542{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2543{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2544{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2545{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2546{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2547{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2548{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2549{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2550{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2551{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2552{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2553{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2554{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2555{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2556{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2557{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2558{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2559{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2560{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2561{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2562{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2563{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2564{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2565{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2566{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2567{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2568{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2569{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2570{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2571{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2572{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2573{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2574{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2575{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2576{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2577{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2578{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2579{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2580{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2581{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2582{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2583{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2584{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2585{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2586{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2587{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2588{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2589{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2590{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2591{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2592{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2593{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2594{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2595{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2596{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2597{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2598{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2599{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2600{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2601{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2602{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2603{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2604{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2605{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2606{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2607{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2608{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2609{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2610{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2611{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2612{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2613{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2614{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2615{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2616{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2617{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2618{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2619{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2620{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2621{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2622{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2623{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2624{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2625{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2626{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2627{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2628{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2629{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2630{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2631{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2632{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2633{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2634{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2635{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2636{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2637{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2638{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2639{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2640{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2641{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2642{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2643{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2644{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2645{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2646{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2647{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2648{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2649{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2650{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2651{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2652{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2653{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2654{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2655{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2656{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2657{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2658{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2659{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2660{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2661{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2662{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2663{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2664{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2665{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2666{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2667
2668{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2669{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2670{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2671{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2672{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2673
2674{ "b", B(18,0,0), B_MASK, COM, { LI } },
2675{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2676{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2677{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
2678
2679{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2680
2681{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2682{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2683{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2684{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2685{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2686{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2687{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2688{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2689{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2690{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2691{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2692{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2693{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2694{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2695{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2696{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2697{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2698{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2699{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2700{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2701{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2702{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2703{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2704{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2705{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2706{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2707{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2708{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2709{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2710{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2711{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2712{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2713{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2714{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2715{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2716{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2717{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2718{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2719{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2720{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2721{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2722{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2723{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2724{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2725{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2726{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2727{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2728{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2729{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2730{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2731{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2732{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2733{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2734{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2735{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2736{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2737{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2738{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2739{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2740{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2741{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2742{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2743{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2744{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2745{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2746{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2747{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2748{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2749{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2750{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2751{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2752{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2753{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2754{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2755{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2756{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2757{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2758{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2759{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2760{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2761{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2762{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2763{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2764{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2765{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2766{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2767{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2768{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2769{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2770{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2771{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2772{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2773{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2774{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2775{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2776{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2777{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2778{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2779{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2780{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2781{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2782{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2783{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2784{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2785{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2786{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2787{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2788{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2789{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2790{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2792{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2793{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2794{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2795{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2796{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2797{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2798{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2799{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2800{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2801{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2802{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2803{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2804{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2805{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2806{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2807{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2808{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2809{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2810{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2811{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2812{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2813{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2814{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2815{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2816{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2817{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2818{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2819{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2820{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2821{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2822{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2823{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2824{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2825{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2826{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2827{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2828{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2829{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2830{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2831{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2832{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2833{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2834{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2835{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2836{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2837{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2838{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2839{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2840{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2841{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2842{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2843{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2844{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2845{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2846{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2847{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2848{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2849{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2850{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2851{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2852{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2853{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2854{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2855{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2856{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2857{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2858{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2859{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2860{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2861{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2862{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2863{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2864{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2865{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2866{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2867{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2868{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2869{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2870{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2871{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2872{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2873{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2874{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2875{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2876{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2877{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2878{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2879{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2880{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2881{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2882{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2883{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2884{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2885{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2886{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2887{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2888{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2889{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2890{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2891{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2892{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2893{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2894{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2895{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2896{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2897{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2898{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2899{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2900{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2901{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2902{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2903
2904{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2905
2906{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2907{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2908{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2909
2910{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2911{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
2912
2913{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2914
2915{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2916
2917{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2918{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2919
2920{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2921{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2922
2923{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2924
2925{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2926
2927{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2928{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2929
2930{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2931
2932{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2933{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2934
2935{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2936{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2937{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2938{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2939{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2940{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2941{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2942{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2943{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2944{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2945{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2946{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2947{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2948{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2949{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2950{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2951{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2952{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2953{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2954{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2955{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2956{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2957{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2958{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2959{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2960{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2961{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2962{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2963{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2964{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2965{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2966{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2967{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2968{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2969{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2970{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2971{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2972{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2973{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2974{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2975{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2976{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2977{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2978{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2979{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2980{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2981{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2982{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2983{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2984{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2985{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2986{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2987{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2988{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2989{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2990{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2991{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2992{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2993{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2994{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2995{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2996{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2997{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2998{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2999{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3000{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3001{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3002{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3003{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3004{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3005{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3006{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3007{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3008{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3009{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3010{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3011{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3012{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3013{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3014{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3015{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3016{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3017{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3018{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3019{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3020{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3021{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3022{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3023{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3024{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3025{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3026{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3027{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3028{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3029{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3030{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3031{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3032{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3033{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3034{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3035{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3036{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3037{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3038{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3039{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3040{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3041{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3042{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3043{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3044{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3045{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3046{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3047{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3048{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3049{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3050{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3051{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3052{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3053{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3054{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3055{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3056{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3057{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3058{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3059{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3060{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3061{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3062{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3063{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3064{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3065{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3066{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3067{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3068{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3069{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3070{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3071{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3072{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3073{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3074{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3075{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3076{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3077{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
3078{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3079{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3080{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
3081{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3082{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3083{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3084{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3085{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3086{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3087
3088{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3089{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3090
3091{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3092{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3093
3094{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3095{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3096{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3097{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3098{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3099{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3100{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3101{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3102
3103{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3104{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3105
3106{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3107{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3108{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3109{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3110
3111{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3112{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3113{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3114{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3115{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3116{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3117
3118{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3119{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3120{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3121
3122{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3123{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3124
3125{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3126{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3127
3128{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3129{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3130
3131{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3132{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3133
3134{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3135{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3136
3137{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3138{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3139{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3140{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3141{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3142{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3143
3144{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3145{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3146
3147{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3148{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3149
3150{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3151{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3152
3153{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3154{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3155{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3156{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3157
3158{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3159{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3160
3161{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3162{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3163{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3164{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3165
3166{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3167{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3168{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3169{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3170{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3171{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3172{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3173{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3174{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3175{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3176{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3177{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3178{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3179{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3180{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3181{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3182{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3183{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3184{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3185{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3186{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3187{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3188{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3189{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3190{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3191{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3192{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3193{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3194{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3195{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3196{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3197
3198{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3199{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3200{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3201{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3202{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3203{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3204{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3205{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3206{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3207{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3208{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3209{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3210
3211{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3212{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3213
3214{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3215{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3216{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3217{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3218{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3219{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3220{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3221{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3222
3223{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3224{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3225
3226{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3227{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3228{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3229{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3230
3231{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3232{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3233
3234{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
3235
3236{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
3237
3238{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3239{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3240
3241{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
3242{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3243
3244{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3245{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3246{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3247{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3248
3249{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3250{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3251{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3252{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3253
3254{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3255{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3256
3257{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3258{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3259
3260{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3261{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3262
3263{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3264
3265{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
3266
3267{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3268{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3269{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3270{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3271
3272{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3273{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3274{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3275{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3276{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3277{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3278{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3279{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3280
3281{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3282
3283{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3284
3285{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3286{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3287
3288{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3289
3290{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3291
3292{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3293{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3294
3295{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3296{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3297
3298{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3299{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3300{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3301{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3302{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3303{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3304{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3305{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3306{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3307{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3308{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3309{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3310{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3311{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3312{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3313
3314{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3315{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3316
3317{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3318{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3319
3320{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3321{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3322
3323{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3324
3325{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3326
3327{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
3328
3329{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3330
3331{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
3332
3333{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3334
3335{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
3336
3337{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3338{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3339{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3340{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3341
3342{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3343{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3344{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3345{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3346
3347{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3348
3349{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3350
3351{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3352
3353{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3354{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3355{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3356{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3357
3358{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
3359
3360{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3361
3362{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3363
3364{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3365
3366{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3367{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3368{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3369{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3370{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3371{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3372{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3373{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3374
3375{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3376{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3377{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3378{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3379{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3380{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3381{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3382{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3383
3384{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3385
3386{ "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }},
3387{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3388
3389{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3390
3391{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
3392
3393{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
3394
3395{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
3396{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3397
3398{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
3399
3400{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
3401
3402{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3403{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3404
3405{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3406{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3407
3408{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3409
3410{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3411{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3412
3413{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3414
3415{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3416
3417{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3418{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
3419
3420{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3421{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3422
3423{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3424
3425{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3426{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3427{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3428{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3429{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3430{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3431{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3432{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3433
3434{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3435{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3436{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3437{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3438{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3439{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3440{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3441{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3442
3443{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3444
3445{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
3446
3447{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
3448
3449{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3450{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3451
3452{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3453{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3454
3455{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
3456
3457{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3458
3459{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3460{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3461{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3462{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3463{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3464{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3465{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3466{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3467
3468{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3469{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3470{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3471{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3472
3473{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3474{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3475{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3476{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3477{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3478{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3479{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3480{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3481
3482{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3483{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3484{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3485{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3486{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3487{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3488{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3489{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3490
3491{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3492{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3493{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3494
3495{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
3496
3497{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3498
3499{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3500{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3501
3502{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3503
3504{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3505
3506{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3507
3508{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3509{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3510{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3511{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3512
3513{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3514{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3515{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3516{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3517{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3518{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3519{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3520{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3521
3522{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3523
3524{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3525
3526{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3527{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3528
3529{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
3530
3531{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3532
3533{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3534{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3535
3536{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3537
3538{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3539
3540{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3541{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3542
3543{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3544
3545{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3546
3547{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3548{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3549
3550{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3551
3552{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3553{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3554{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3555{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3556{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3557{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3558{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3559{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3560{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3561{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3562{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3563{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3564{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3565{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3566{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3567{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3568{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3569{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3570{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3571{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3572{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3573{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3574{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3575{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3576{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3577{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3578{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3579{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3580{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3581{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3582{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3583{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3584{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3585{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3586{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3587
3588{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3589{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3590{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3591{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3592
3593{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3594
3595{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3596{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3597{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3598{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3599{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3600{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3601{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3602{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3603{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3604{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3605{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3606{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3607{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3608{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3609{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3610{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3611{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3612{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3613{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3614{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3615{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3616{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3617{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3618{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3619{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3620{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3621{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3622{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3623{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3624{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3625{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3626{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3627{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3628{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3629{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3630{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3631{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3632{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3633{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3634{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3635{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3636{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3637{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3638{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3639{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3640{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3641{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3642{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3643{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3644{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3645{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3646{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3647{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3648{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3649{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3650{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3651{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3652{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3653{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3654{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3655{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3656{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3657{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3658{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3659{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3660{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3661{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3662{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3663{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3664{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3665{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3666{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3667{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3668{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3669{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3670{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3671{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3672{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3673{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3674{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3675{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3676{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3677{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3678{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3679{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3680{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3681{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3682{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3683{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3684{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3685{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3686{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3687{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3688{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3689{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3690{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3691{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3692{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3693{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3694{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3695{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3696{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3697{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3698{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3699{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3700{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3701{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3702{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3703{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3704{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3705{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3706{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3707{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3708{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3709{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3710{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3711{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3712{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3713{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3714{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3715{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3716{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3717{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3718{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3719{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3720{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3721{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3722{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3723{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3724{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3725{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3726{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3727{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3728{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3729{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3730{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3731{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3732{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3733{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3734{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3735{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3736{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3737{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3738{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3739{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3740{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3741{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3742{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3743{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3744{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3745{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3746{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3747{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3748{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3749{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3750{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3751{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3752{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3753{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3754{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3755{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3756{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3757{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3758{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3759{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3760{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3761{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3762{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3763{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3764{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3765{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3766{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3767{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3768{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3769{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3770{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3771{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3772{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3773{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3774{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3775{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3776{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3777
3778{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3779
3780{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3781{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3782
3783{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3784
3785{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3786
3787{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3788{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3789
3790{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3791
3792{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3793{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3794{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3795{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3796
3797{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3798{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3799{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3800{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3801
3802{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3803
3804{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3805
3806{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3807
3808{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3809
3810{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3811
3812{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3813
3814{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3815{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3816
3817{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3818{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3819
3820{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3821
3822{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3823
3824{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3825
3826{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3827
3828{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3829
3830{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3831
3832{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3833
3834{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3835{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3836
3837{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3838{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3839
3840{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3841
3842{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3843
3844{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3845
3846{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3847
3848{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3849
3850{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3851{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3852{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3853{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3854
3855{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3856{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3857{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3858{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3859{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3860{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3861{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3862{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3863{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3864{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3865{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3866{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3867{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3868{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3869{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3870{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3871{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3872{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3873{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3874{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3875{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3876{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3877{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3878{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3879{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3880{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3881{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3882{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3883{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3884{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3885{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3886{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3887{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3888{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3889{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3890
3891{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3892{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3893
3894{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3895{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3896{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3897{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3898
3899{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3900{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3901
3902{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3903{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3904{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3905{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3906
3907{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3908{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3909{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3910{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3911{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3912{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3913{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3914{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3915{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3916{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3917{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3918{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3919{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3920{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3921{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3922{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3923{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3924{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3925{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3926{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3927{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
3928{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3929{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
3930{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3931{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3932{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3933{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3934{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3935{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3936{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3937{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3938{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3939{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3940{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3941{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3942{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3943{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3944{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3945{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3946{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3947{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
3948{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3949{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
3950{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3951{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3952{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
3953{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
3954{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
3955{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
3956{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
3957{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
3958{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3959{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3960{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3961{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3962{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3963{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
3964{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3965{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
3966{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3967{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
3968{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3969{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3970{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
3971{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3972{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
3973{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3974{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
3975{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3976{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
3977{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3978{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
3979{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3980{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
3981{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3982{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
3983{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3984{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
3985{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3986{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
3987{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3988{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
3989{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3990{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3991{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3992{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3993{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3994{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3995{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3996{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3997{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3998{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3999{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4000{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4001{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4002{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4003{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4004{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4005{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4006{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4007{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4008{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4009{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4010{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4011{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4012{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4013{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4014{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4015{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4016{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4017{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4018{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4019{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4020{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4021{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4022{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4023{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4024{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4025{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4026{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4027{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4028{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4029{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4030{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4031{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4032{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4033{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4034{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4035{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4036{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4037{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4038{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4039{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4040{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4041{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4042{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4043{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4044{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4045{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4046{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4047{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4048{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4049{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4050{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4051{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4052{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4053{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4054{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4055
4056{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4057
4058{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4059{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4060
4061{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4062
4063{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4064
4065{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4066
4067{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4068
4069{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4070{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4071{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4072{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4073{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4074{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4075
4076{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4077{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4078{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4079{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4080
4081{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4082{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4083
4084{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4085{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4086{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4087{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4088
4089{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4090
4091{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4092
4093{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4094
4095{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4096
4097{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4098
4099{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4100{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4101
4102{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4103
4104{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
4105{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4106
4107{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
4108{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4109
4110{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
4111
4112{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4113{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4114{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4115{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4116
4117{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4118{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4119
4120{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4121{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4122
4123{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4124{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4125
4126{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
4127
4128{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
4129
4130{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4131{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4132
4133{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4134
4135{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4136
4137{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4138
4139{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
4140{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
4141
4142{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4143{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4144{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4145{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4146{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4147
4148{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
4149
4150{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
4151
4152{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4153
4154{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4155
4156{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4157
4158{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4159
4160{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4161
4162{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
4163{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
4164
4165{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
4166{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
4167
4168{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
4169
4170{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4171{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4172
4173{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4174{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4175
4176{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
4177
4178{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
4179
4180{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4181
4182{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4183{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4184
4185{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4186
4187{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
4188{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
4189
4190{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
4191
4192{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4193{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4194
4195{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4196{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4197
4198{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
4199
4200{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4201
4202{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4203
4204{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4205{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4206
4207{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4208
4209{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4210
4211{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4212{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4213
4214{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
4215
4216{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4217{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4218{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4219{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4220
4221{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4222{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4223
4224{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
4225
4226{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
4227{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
4228
4229{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4230
4231{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4232{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4233
4234{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4235{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4236{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4237{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4238
4239{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4240
4241{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4242{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4243
4244{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
4245{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4246{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
4247{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
4248{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4249{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4250
4251{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4252
4253{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
4254
4255{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4256{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4257
4258{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4259{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4260
4261{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4262{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4263{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4264{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4265
4266{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
4267
4268{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
4269
4270{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4271{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4272{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
4273{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
4274
4275{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4276{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4277
4278{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4279{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4280
4281{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4282
4283{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4284
4285{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4286{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4287{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
4288{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4289{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4290
4291{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4292
4293{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
4294
4295{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4296{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4297
4298{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4299
4300{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4301{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
4302
4303{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4304
4305{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4306{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4307
4308{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4309
4310{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4311{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4312{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4313{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4314{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4315{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4316{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4317{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4318{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4319{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4320{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4321{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4322
4323{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
4324{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
4325
4326{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4327{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
4328
4329{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
4330
4331{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4332
4333{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
4334{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
4335
4336{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4337{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
4338
4339{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
4340
4341{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4342
4343{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
4344
4345{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4346
4347{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
4348
4349{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4350
4351{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
4352
4353{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4354
4355{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4356{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
4357
4358{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
4359{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
4360
4361{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
4362
4363{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4364
4365{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
4366
4367{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4368
4369{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
4370
4371{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4372
4373{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
4374
4375{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4376
4377{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4378
4379{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
4380
4381{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
4382
4383{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
4384{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4385{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
4386{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4387{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
4388{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4389{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
4390{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4391{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
4392{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4393{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
4394{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4395{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
4396{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4397
4398{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
4399
4400{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4401
4402{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
4403
4404{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4405{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4406
4407{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4408{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4409
4410{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4411{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4412
4413{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4414{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4415
4416{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4417{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4418
4419{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4420{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4421
4422{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4423{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4424
4425{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4426{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4427
4428{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4429{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4430
4431{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4432{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4433
4434{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4435
4436{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4437
4438{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
4439{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
4440{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
4441{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4442{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
4443{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4444{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
4445{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4446{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
4447{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4448{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
4449{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4450
4451{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
4452
4453{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4454
4455{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
4456
4457{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4458
4459{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4460{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4461
4462{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4463{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4464{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4465{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4466
4467{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4468{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4469{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4470{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4471
4472{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4473{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4474{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4475{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4476
4477{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4478{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4479{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4480{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4481
4482{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4483{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4484{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4485{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4486
4487{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4488{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4489
4490{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4491{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4492
4493{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4494{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4495{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4496{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4497
4498{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4499{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4500
4501{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4502{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4503{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4504{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4505
4506{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4507{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4508{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4509{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4510
4511{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4512{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4513{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4514{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4515
4516{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4517{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4518{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4519{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4520
4521{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4522
4523{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4524{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4525
4526{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4527{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4528
4529{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4530
4531{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4532{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4533
4534{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4535{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4536
4537{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4538{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4539
4540{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4541{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4542
4543{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4544{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4545
4546{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4547{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4548
4549{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4550{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4551
4552{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4553{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4554
4555{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4556{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4557
4558{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4559{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4560
4561};
4562
4563const int powerpc_num_opcodes =
4564 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4565
4566/* The macro table. This is only used by the assembler. */
4567
4568/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4569 when x=0; 32-x when x is between 1 and 31; are negative if x is
4570 negative; and are 32 or more otherwise. This is what you want
4571 when, for instance, you are emulating a right shift by a
4572 rotate-left-and-mask, because the underlying instructions support
4573 shifts of size 0 but not shifts of size 32. By comparison, when
4574 extracting x bits from some word you want to use just 32-x, because
4575 the underlying instructions don't support extracting 0 bits but do
4576 support extracting the whole word (32 bits in this case). */
4577
4578const struct powerpc_macro powerpc_macros[] = {
4579{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4580{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4581{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4582{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4583{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4584{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4585{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4586{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4587{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4588{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4589{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4590{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4591{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4592{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4593{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4594{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4595
4596{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4597{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4598{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4599{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4600{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4601{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4602{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4603{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4604{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4605{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4606{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4607{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4608{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4609{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4610{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4611{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4612{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4613{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4614{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4615{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4616{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4617{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4618};
4619
4620const int powerpc_num_macros =
4621 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
diff --git a/arch/ppc64/xmon/ppc.h b/arch/ppc64/xmon/ppc.h
deleted file mode 100644
index 342237e8dd69..000000000000
--- a/arch/ppc64/xmon/ppc.h
+++ /dev/null
@@ -1,307 +0,0 @@
1/* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
111, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free
20Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22#ifndef PPC_H
23#define PPC_H
24
25/* The opcode table is an array of struct powerpc_opcode. */
26
27struct powerpc_opcode
28{
29 /* The opcode name. */
30 const char *name;
31
32 /* The opcode itself. Those bits which will be filled in with
33 operands are zeroes. */
34 unsigned long opcode;
35
36 /* The opcode mask. This is used by the disassembler. This is a
37 mask containing ones indicating those bits which must match the
38 opcode field, and zeroes indicating those bits which need not
39 match (and are presumably filled in by operands). */
40 unsigned long mask;
41
42 /* One bit flags for the opcode. These are used to indicate which
43 specific processors support the instructions. The defined values
44 are listed below. */
45 unsigned long flags;
46
47 /* An array of operand codes. Each code is an index into the
48 operand table. They appear in the order which the operands must
49 appear in assembly code, and are terminated by a zero. */
50 unsigned char operands[8];
51};
52
53/* The table itself is sorted by major opcode number, and is otherwise
54 in the order in which the disassembler should consider
55 instructions. */
56extern const struct powerpc_opcode powerpc_opcodes[];
57extern const int powerpc_num_opcodes;
58
59/* Values defined for the flags field of a struct powerpc_opcode. */
60
61/* Opcode is defined for the PowerPC architecture. */
62#define PPC_OPCODE_PPC 1
63
64/* Opcode is defined for the POWER (RS/6000) architecture. */
65#define PPC_OPCODE_POWER 2
66
67/* Opcode is defined for the POWER2 (Rios 2) architecture. */
68#define PPC_OPCODE_POWER2 4
69
70/* Opcode is only defined on 32 bit architectures. */
71#define PPC_OPCODE_32 8
72
73/* Opcode is only defined on 64 bit architectures. */
74#define PPC_OPCODE_64 0x10
75
76/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
77 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
78 but it also supports many additional POWER instructions. */
79#define PPC_OPCODE_601 0x20
80
81/* Opcode is supported in both the Power and PowerPC architectures
82 (ie, compiler's -mcpu=common or assembler's -mcom). */
83#define PPC_OPCODE_COMMON 0x40
84
85/* Opcode is supported for any Power or PowerPC platform (this is
86 for the assembler's -many option, and it eliminates duplicates). */
87#define PPC_OPCODE_ANY 0x80
88
89/* Opcode is supported as part of the 64-bit bridge. */
90#define PPC_OPCODE_64_BRIDGE 0x100
91
92/* Opcode is supported by Altivec Vector Unit */
93#define PPC_OPCODE_ALTIVEC 0x200
94
95/* Opcode is supported by PowerPC 403 processor. */
96#define PPC_OPCODE_403 0x400
97
98/* Opcode is supported by PowerPC BookE processor. */
99#define PPC_OPCODE_BOOKE 0x800
100
101/* Opcode is only supported by 64-bit PowerPC BookE processor. */
102#define PPC_OPCODE_BOOKE64 0x1000
103
104/* Opcode is supported by PowerPC 440 processor. */
105#define PPC_OPCODE_440 0x2000
106
107/* Opcode is only supported by Power4 architecture. */
108#define PPC_OPCODE_POWER4 0x4000
109
110/* Opcode isn't supported by Power4 architecture. */
111#define PPC_OPCODE_NOPOWER4 0x8000
112
113/* Opcode is only supported by POWERPC Classic architecture. */
114#define PPC_OPCODE_CLASSIC 0x10000
115
116/* Opcode is only supported by e500x2 Core. */
117#define PPC_OPCODE_SPE 0x20000
118
119/* Opcode is supported by e500x2 Integer select APU. */
120#define PPC_OPCODE_ISEL 0x40000
121
122/* Opcode is an e500 SPE floating point instruction. */
123#define PPC_OPCODE_EFS 0x80000
124
125/* Opcode is supported by branch locking APU. */
126#define PPC_OPCODE_BRLOCK 0x100000
127
128/* Opcode is supported by performance monitor APU. */
129#define PPC_OPCODE_PMR 0x200000
130
131/* Opcode is supported by cache locking APU. */
132#define PPC_OPCODE_CACHELCK 0x400000
133
134/* Opcode is supported by machine check APU. */
135#define PPC_OPCODE_RFMCI 0x800000
136
137/* A macro to extract the major opcode from an instruction. */
138#define PPC_OP(i) (((i) >> 26) & 0x3f)
139
140/* The operands table is an array of struct powerpc_operand. */
141
142struct powerpc_operand
143{
144 /* The number of bits in the operand. */
145 int bits;
146
147 /* How far the operand is left shifted in the instruction. */
148 int shift;
149
150 /* Insertion function. This is used by the assembler. To insert an
151 operand value into an instruction, check this field.
152
153 If it is NULL, execute
154 i |= (op & ((1 << o->bits) - 1)) << o->shift;
155 (i is the instruction which we are filling in, o is a pointer to
156 this structure, and op is the opcode value; this assumes twos
157 complement arithmetic).
158
159 If this field is not NULL, then simply call it with the
160 instruction and the operand value. It will return the new value
161 of the instruction. If the ERRMSG argument is not NULL, then if
162 the operand value is illegal, *ERRMSG will be set to a warning
163 string (the operand will be inserted in any case). If the
164 operand value is legal, *ERRMSG will be unchanged (most operands
165 can accept any value). */
166 unsigned long (*insert)
167 (unsigned long instruction, long op, int dialect, const char **errmsg);
168
169 /* Extraction function. This is used by the disassembler. To
170 extract this operand type from an instruction, check this field.
171
172 If it is NULL, compute
173 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
174 if ((o->flags & PPC_OPERAND_SIGNED) != 0
175 && (op & (1 << (o->bits - 1))) != 0)
176 op -= 1 << o->bits;
177 (i is the instruction, o is a pointer to this structure, and op
178 is the result; this assumes twos complement arithmetic).
179
180 If this field is not NULL, then simply call it with the
181 instruction value. It will return the value of the operand. If
182 the INVALID argument is not NULL, *INVALID will be set to
183 non-zero if this operand type can not actually be extracted from
184 this operand (i.e., the instruction does not match). If the
185 operand is valid, *INVALID will not be changed. */
186 long (*extract) (unsigned long instruction, int dialect, int *invalid);
187
188 /* One bit syntax flags. */
189 unsigned long flags;
190};
191
192/* Elements in the table are retrieved by indexing with values from
193 the operands field of the powerpc_opcodes table. */
194
195extern const struct powerpc_operand powerpc_operands[];
196
197/* Values defined for the flags field of a struct powerpc_operand. */
198
199/* This operand takes signed values. */
200#define PPC_OPERAND_SIGNED (01)
201
202/* This operand takes signed values, but also accepts a full positive
203 range of values when running in 32 bit mode. That is, if bits is
204 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
205 this flag is ignored. */
206#define PPC_OPERAND_SIGNOPT (02)
207
208/* This operand does not actually exist in the assembler input. This
209 is used to support extended mnemonics such as mr, for which two
210 operands fields are identical. The assembler should call the
211 insert function with any op value. The disassembler should call
212 the extract function, ignore the return value, and check the value
213 placed in the valid argument. */
214#define PPC_OPERAND_FAKE (04)
215
216/* The next operand should be wrapped in parentheses rather than
217 separated from this one by a comma. This is used for the load and
218 store instructions which want their operands to look like
219 reg,displacement(reg)
220 */
221#define PPC_OPERAND_PARENS (010)
222
223/* This operand may use the symbolic names for the CR fields, which
224 are
225 lt 0 gt 1 eq 2 so 3 un 3
226 cr0 0 cr1 1 cr2 2 cr3 3
227 cr4 4 cr5 5 cr6 6 cr7 7
228 These may be combined arithmetically, as in cr2*4+gt. These are
229 only supported on the PowerPC, not the POWER. */
230#define PPC_OPERAND_CR (020)
231
232/* This operand names a register. The disassembler uses this to print
233 register names with a leading 'r'. */
234#define PPC_OPERAND_GPR (040)
235
236/* This operand names a floating point register. The disassembler
237 prints these with a leading 'f'. */
238#define PPC_OPERAND_FPR (0100)
239
240/* This operand is a relative branch displacement. The disassembler
241 prints these symbolically if possible. */
242#define PPC_OPERAND_RELATIVE (0200)
243
244/* This operand is an absolute branch address. The disassembler
245 prints these symbolically if possible. */
246#define PPC_OPERAND_ABSOLUTE (0400)
247
248/* This operand is optional, and is zero if omitted. This is used for
249 the optional BF and L fields in the comparison instructions. The
250 assembler must count the number of operands remaining on the line,
251 and the number of operands remaining for the opcode, and decide
252 whether this operand is present or not. The disassembler should
253 print this operand out only if it is not zero. */
254#define PPC_OPERAND_OPTIONAL (01000)
255
256/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
257 is omitted, then for the next operand use this operand value plus
258 1, ignoring the next operand field for the opcode. This wretched
259 hack is needed because the Power rotate instructions can take
260 either 4 or 5 operands. The disassembler should print this operand
261 out regardless of the PPC_OPERAND_OPTIONAL field. */
262#define PPC_OPERAND_NEXT (02000)
263
264/* This operand should be regarded as a negative number for the
265 purposes of overflow checking (i.e., the normal most negative
266 number is disallowed and one more than the normal most positive
267 number is allowed). This flag will only be set for a signed
268 operand. */
269#define PPC_OPERAND_NEGATIVE (04000)
270
271/* This operand names a vector unit register. The disassembler
272 prints these with a leading 'v'. */
273#define PPC_OPERAND_VR (010000)
274
275/* This operand is for the DS field in a DS form instruction. */
276#define PPC_OPERAND_DS (020000)
277
278/* This operand is for the DQ field in a DQ form instruction. */
279#define PPC_OPERAND_DQ (040000)
280
281/* The POWER and PowerPC assemblers use a few macros. We keep them
282 with the operands table for simplicity. The macro table is an
283 array of struct powerpc_macro. */
284
285struct powerpc_macro
286{
287 /* The macro name. */
288 const char *name;
289
290 /* The number of operands the macro takes. */
291 unsigned int operands;
292
293 /* One bit flags for the opcode. These are used to indicate which
294 specific processors support the instructions. The values are the
295 same as those for the struct powerpc_opcode flags field. */
296 unsigned long flags;
297
298 /* A format string to turn the macro into a normal instruction.
299 Each %N in the string is replaced with operand number N (zero
300 based). */
301 const char *format;
302};
303
304extern const struct powerpc_macro powerpc_macros[];
305extern const int powerpc_num_macros;
306
307#endif /* PPC_H */
diff --git a/arch/ppc64/xmon/setjmp.S b/arch/ppc64/xmon/setjmp.S
deleted file mode 100644
index 30ee643d557c..000000000000
--- a/arch/ppc64/xmon/setjmp.S
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * Copyright (C) 1996 Paul Mackerras.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * NOTE: assert(sizeof(buf) > 184)
10 */
11#include <asm/processor.h>
12#include <asm/ppc_asm.h>
13
14_GLOBAL(xmon_setjmp)
15 mflr r0
16 std r0,0(r3)
17 std r1,8(r3)
18 std r2,16(r3)
19 mfcr r0
20 std r0,24(r3)
21 std r13,32(r3)
22 std r14,40(r3)
23 std r15,48(r3)
24 std r16,56(r3)
25 std r17,64(r3)
26 std r18,72(r3)
27 std r19,80(r3)
28 std r20,88(r3)
29 std r21,96(r3)
30 std r22,104(r3)
31 std r23,112(r3)
32 std r24,120(r3)
33 std r25,128(r3)
34 std r26,136(r3)
35 std r27,144(r3)
36 std r28,152(r3)
37 std r29,160(r3)
38 std r30,168(r3)
39 std r31,176(r3)
40 li r3,0
41 blr
42
43_GLOBAL(xmon_longjmp)
44 cmpdi r4,0
45 bne 1f
46 li r4,1
471: ld r13,32(r3)
48 ld r14,40(r3)
49 ld r15,48(r3)
50 ld r16,56(r3)
51 ld r17,64(r3)
52 ld r18,72(r3)
53 ld r19,80(r3)
54 ld r20,88(r3)
55 ld r21,96(r3)
56 ld r22,104(r3)
57 ld r23,112(r3)
58 ld r24,120(r3)
59 ld r25,128(r3)
60 ld r26,136(r3)
61 ld r27,144(r3)
62 ld r28,152(r3)
63 ld r29,160(r3)
64 ld r30,168(r3)
65 ld r31,176(r3)
66 ld r0,24(r3)
67 mtcrf 56,r0
68 ld r0,0(r3)
69 ld r1,8(r3)
70 ld r2,16(r3)
71 mtlr r0
72 mr r3,r4
73 blr
diff --git a/arch/ppc64/xmon/start.c b/arch/ppc64/xmon/start.c
deleted file mode 100644
index e50c158191e1..000000000000
--- a/arch/ppc64/xmon/start.c
+++ /dev/null
@@ -1,187 +0,0 @@
1/*
2 * Copyright (C) 1996 Paul Mackerras.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#include <linux/config.h>
10#include <linux/string.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/sysrq.h>
14#include <linux/init.h>
15#include <asm/machdep.h>
16#include <asm/io.h>
17#include <asm/page.h>
18#include <asm/prom.h>
19#include <asm/processor.h>
20#include <asm/udbg.h>
21#include <asm/system.h>
22#include "nonstdio.h"
23
24#ifdef CONFIG_MAGIC_SYSRQ
25
26static void sysrq_handle_xmon(int key, struct pt_regs *pt_regs,
27 struct tty_struct *tty)
28{
29 /* ensure xmon is enabled */
30 xmon_init(1);
31 debugger(pt_regs);
32}
33
34static struct sysrq_key_op sysrq_xmon_op =
35{
36 .handler = sysrq_handle_xmon,
37 .help_msg = "Xmon",
38 .action_msg = "Entering xmon",
39};
40
41static int __init setup_xmon_sysrq(void)
42{
43 register_sysrq_key('x', &sysrq_xmon_op);
44 return 0;
45}
46__initcall(setup_xmon_sysrq);
47#endif /* CONFIG_MAGIC_SYSRQ */
48
49int
50xmon_write(void *handle, void *ptr, int nb)
51{
52 return udbg_write(ptr, nb);
53}
54
55int
56xmon_read(void *handle, void *ptr, int nb)
57{
58 return udbg_read(ptr, nb);
59}
60
61int
62xmon_read_poll(void)
63{
64 if (udbg_getc_poll)
65 return udbg_getc_poll();
66 return -1;
67}
68
69FILE *xmon_stdin;
70FILE *xmon_stdout;
71
72int
73xmon_putc(int c, void *f)
74{
75 char ch = c;
76
77 if (c == '\n')
78 xmon_putc('\r', f);
79 return xmon_write(f, &ch, 1) == 1? c: -1;
80}
81
82int
83xmon_putchar(int c)
84{
85 return xmon_putc(c, xmon_stdout);
86}
87
88int
89xmon_fputs(char *str, void *f)
90{
91 int n = strlen(str);
92
93 return xmon_write(f, str, n) == n? 0: -1;
94}
95
96int
97xmon_readchar(void)
98{
99 char ch;
100
101 for (;;) {
102 switch (xmon_read(xmon_stdin, &ch, 1)) {
103 case 1:
104 return ch;
105 case -1:
106 xmon_printf("read(stdin) returned -1\r\n", 0, 0);
107 return -1;
108 }
109 }
110}
111
112static char line[256];
113static char *lineptr;
114static int lineleft;
115
116int
117xmon_getchar(void)
118{
119 int c;
120
121 if (lineleft == 0) {
122 lineptr = line;
123 for (;;) {
124 c = xmon_readchar();
125 if (c == -1 || c == 4)
126 break;
127 if (c == '\r' || c == '\n') {
128 *lineptr++ = '\n';
129 xmon_putchar('\n');
130 break;
131 }
132 switch (c) {
133 case 0177:
134 case '\b':
135 if (lineptr > line) {
136 xmon_putchar('\b');
137 xmon_putchar(' ');
138 xmon_putchar('\b');
139 --lineptr;
140 }
141 break;
142 case 'U' & 0x1F:
143 while (lineptr > line) {
144 xmon_putchar('\b');
145 xmon_putchar(' ');
146 xmon_putchar('\b');
147 --lineptr;
148 }
149 break;
150 default:
151 if (lineptr >= &line[sizeof(line) - 1])
152 xmon_putchar('\a');
153 else {
154 xmon_putchar(c);
155 *lineptr++ = c;
156 }
157 }
158 }
159 lineleft = lineptr - line;
160 lineptr = line;
161 }
162 if (lineleft == 0)
163 return -1;
164 --lineleft;
165 return *lineptr++;
166}
167
168char *
169xmon_fgets(char *str, int nb, void *f)
170{
171 char *p;
172 int c;
173
174 for (p = str; p < str + nb - 1; ) {
175 c = xmon_getchar();
176 if (c == -1) {
177 if (p == str)
178 return NULL;
179 break;
180 }
181 *p++ = c;
182 if (c == '\n')
183 break;
184 }
185 *p = 0;
186 return str;
187}
diff --git a/arch/ppc64/xmon/subr_prf.c b/arch/ppc64/xmon/subr_prf.c
deleted file mode 100644
index 5242bd7d0959..000000000000
--- a/arch/ppc64/xmon/subr_prf.c
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Written by Cort Dougan to replace the version originally used
3 * by Paul Mackerras, which came from NetBSD and thus had copyright
4 * conflicts with Linux.
5 *
6 * This file makes liberal use of the standard linux utility
7 * routines to reduce the size of the binary. We assume we can
8 * trust some parts of Linux inside the debugger.
9 * -- Cort (cort@cs.nmt.edu)
10 *
11 * Copyright (C) 1999 Cort Dougan.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/string.h>
21#include <stdarg.h>
22#include "nonstdio.h"
23
24extern int xmon_write(void *, void *, int);
25
26void
27xmon_vfprintf(void *f, const char *fmt, va_list ap)
28{
29 static char xmon_buf[2048];
30 int n;
31
32 n = vsprintf(xmon_buf, fmt, ap);
33 xmon_write(f, xmon_buf, n);
34}
35
36void
37xmon_printf(const char *fmt, ...)
38{
39 va_list ap;
40
41 va_start(ap, fmt);
42 xmon_vfprintf(stdout, fmt, ap);
43 va_end(ap);
44}
45
46void
47xmon_fprintf(void *f, const char *fmt, ...)
48{
49 va_list ap;
50
51 va_start(ap, fmt);
52 xmon_vfprintf(f, fmt, ap);
53 va_end(ap);
54}
55
diff --git a/arch/ppc64/xmon/xmon.c b/arch/ppc64/xmon/xmon.c
deleted file mode 100644
index 74e63a886a69..000000000000
--- a/arch/ppc64/xmon/xmon.c
+++ /dev/null
@@ -1,2514 +0,0 @@
1/*
2 * Routines providing a simple monitor for use on the PowerMac.
3 *
4 * Copyright (C) 1996 Paul Mackerras.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/config.h>
12#include <linux/errno.h>
13#include <linux/sched.h>
14#include <linux/smp.h>
15#include <linux/mm.h>
16#include <linux/reboot.h>
17#include <linux/delay.h>
18#include <linux/kallsyms.h>
19#include <linux/cpumask.h>
20
21#include <asm/ptrace.h>
22#include <asm/string.h>
23#include <asm/prom.h>
24#include <asm/machdep.h>
25#include <asm/processor.h>
26#include <asm/pgtable.h>
27#include <asm/mmu.h>
28#include <asm/mmu_context.h>
29#include <asm/paca.h>
30#include <asm/ppcdebug.h>
31#include <asm/cputable.h>
32#include <asm/rtas.h>
33#include <asm/sstep.h>
34#include <asm/bug.h>
35#include <asm/hvcall.h>
36
37#include "nonstdio.h"
38#include "privinst.h"
39
40#define scanhex xmon_scanhex
41#define skipbl xmon_skipbl
42
43#ifdef CONFIG_SMP
44cpumask_t cpus_in_xmon = CPU_MASK_NONE;
45static unsigned long xmon_taken = 1;
46static int xmon_owner;
47static int xmon_gate;
48#endif /* CONFIG_SMP */
49
50static unsigned long in_xmon = 0;
51
52static unsigned long adrs;
53static int size = 1;
54#define MAX_DUMP (128 * 1024)
55static unsigned long ndump = 64;
56static unsigned long nidump = 16;
57static unsigned long ncsum = 4096;
58static int termch;
59static char tmpstr[128];
60
61#define JMP_BUF_LEN (184/sizeof(long))
62static long bus_error_jmp[JMP_BUF_LEN];
63static int catch_memory_errors;
64static long *xmon_fault_jmp[NR_CPUS];
65#define setjmp xmon_setjmp
66#define longjmp xmon_longjmp
67
68/* Breakpoint stuff */
69struct bpt {
70 unsigned long address;
71 unsigned int instr[2];
72 atomic_t ref_count;
73 int enabled;
74 unsigned long pad;
75};
76
77/* Bits in bpt.enabled */
78#define BP_IABR_TE 1 /* IABR translation enabled */
79#define BP_IABR 2
80#define BP_TRAP 8
81#define BP_DABR 0x10
82
83#define NBPTS 256
84static struct bpt bpts[NBPTS];
85static struct bpt dabr;
86static struct bpt *iabr;
87static unsigned bpinstr = 0x7fe00008; /* trap */
88
89#define BP_NUM(bp) ((bp) - bpts + 1)
90
91/* Prototypes */
92static int cmds(struct pt_regs *);
93static int mread(unsigned long, void *, int);
94static int mwrite(unsigned long, void *, int);
95static int handle_fault(struct pt_regs *);
96static void byterev(unsigned char *, int);
97static void memex(void);
98static int bsesc(void);
99static void dump(void);
100static void prdump(unsigned long, long);
101static int ppc_inst_dump(unsigned long, long, int);
102void print_address(unsigned long);
103static void backtrace(struct pt_regs *);
104static void excprint(struct pt_regs *);
105static void prregs(struct pt_regs *);
106static void memops(int);
107static void memlocate(void);
108static void memzcan(void);
109static void memdiffs(unsigned char *, unsigned char *, unsigned, unsigned);
110int skipbl(void);
111int scanhex(unsigned long *valp);
112static void scannl(void);
113static int hexdigit(int);
114void getstring(char *, int);
115static void flush_input(void);
116static int inchar(void);
117static void take_input(char *);
118static unsigned long read_spr(int);
119static void write_spr(int, unsigned long);
120static void super_regs(void);
121static void remove_bpts(void);
122static void insert_bpts(void);
123static void remove_cpu_bpts(void);
124static void insert_cpu_bpts(void);
125static struct bpt *at_breakpoint(unsigned long pc);
126static struct bpt *in_breakpoint_table(unsigned long pc, unsigned long *offp);
127static int do_step(struct pt_regs *);
128static void bpt_cmds(void);
129static void cacheflush(void);
130static int cpu_cmd(void);
131static void csum(void);
132static void bootcmds(void);
133void dump_segments(void);
134static void symbol_lookup(void);
135static void xmon_print_symbol(unsigned long address, const char *mid,
136 const char *after);
137static const char *getvecname(unsigned long vec);
138
139static void debug_trace(void);
140
141extern int print_insn_powerpc(unsigned long, unsigned long, int);
142extern void printf(const char *fmt, ...);
143extern void xmon_vfprintf(void *f, const char *fmt, va_list ap);
144extern int xmon_putc(int c, void *f);
145extern int putchar(int ch);
146extern int xmon_read_poll(void);
147extern int setjmp(long *);
148extern void longjmp(long *, int);
149extern unsigned long _ASR;
150
151#define GETWORD(v) (((v)[0] << 24) + ((v)[1] << 16) + ((v)[2] << 8) + (v)[3])
152
153#define isxdigit(c) (('0' <= (c) && (c) <= '9') \
154 || ('a' <= (c) && (c) <= 'f') \
155 || ('A' <= (c) && (c) <= 'F'))
156#define isalnum(c) (('0' <= (c) && (c) <= '9') \
157 || ('a' <= (c) && (c) <= 'z') \
158 || ('A' <= (c) && (c) <= 'Z'))
159#define isspace(c) (c == ' ' || c == '\t' || c == 10 || c == 13 || c == 0)
160
161static char *help_string = "\
162Commands:\n\
163 b show breakpoints\n\
164 bd set data breakpoint\n\
165 bi set instruction breakpoint\n\
166 bc clear breakpoint\n"
167#ifdef CONFIG_SMP
168 "\
169 c print cpus stopped in xmon\n\
170 c# try to switch to cpu number h (in hex)\n"
171#endif
172 "\
173 C checksum\n\
174 d dump bytes\n\
175 di dump instructions\n\
176 df dump float values\n\
177 dd dump double values\n\
178 e print exception information\n\
179 f flush cache\n\
180 la lookup symbol+offset of specified address\n\
181 ls lookup address of specified symbol\n\
182 m examine/change memory\n\
183 mm move a block of memory\n\
184 ms set a block of memory\n\
185 md compare two blocks of memory\n\
186 ml locate a block of memory\n\
187 mz zero a block of memory\n\
188 mi show information about memory allocation\n\
189 p show the task list\n\
190 r print registers\n\
191 s single step\n\
192 S print special registers\n\
193 t print backtrace\n\
194 T Enable/Disable PPCDBG flags\n\
195 x exit monitor and recover\n\
196 X exit monitor and dont recover\n\
197 u dump segment table or SLB\n\
198 ? help\n"
199 "\
200 zr reboot\n\
201 zh halt\n"
202;
203
204static struct pt_regs *xmon_regs;
205
206extern inline void sync(void)
207{
208 asm volatile("sync; isync");
209}
210
211/* (Ref: 64-bit PowerPC ELF ABI Spplement; Ian Lance Taylor, Zembu Labs).
212 A PPC stack frame looks like this:
213
214 High Address
215 Back Chain
216 FP reg save area
217 GP reg save area
218 Local var space
219 Parameter save area (SP+48)
220 TOC save area (SP+40)
221 link editor doubleword (SP+32)
222 compiler doubleword (SP+24)
223 LR save (SP+16)
224 CR save (SP+8)
225 Back Chain (SP+0)
226
227 Note that the LR (ret addr) may not be saved in the current frame if
228 no functions have been called from the current function.
229 */
230
231/*
232 * Disable surveillance (the service processor watchdog function)
233 * while we are in xmon.
234 * XXX we should re-enable it when we leave. :)
235 */
236#define SURVEILLANCE_TOKEN 9000
237
238static inline void disable_surveillance(void)
239{
240#ifdef CONFIG_PPC_PSERIES
241 /* Since this can't be a module, args should end up below 4GB. */
242 static struct rtas_args args;
243
244 /*
245 * At this point we have got all the cpus we can into
246 * xmon, so there is hopefully no other cpu calling RTAS
247 * at the moment, even though we don't take rtas.lock.
248 * If we did try to take rtas.lock there would be a
249 * real possibility of deadlock.
250 */
251 args.token = rtas_token("set-indicator");
252 if (args.token == RTAS_UNKNOWN_SERVICE)
253 return;
254 args.nargs = 3;
255 args.nret = 1;
256 args.rets = &args.args[3];
257 args.args[0] = SURVEILLANCE_TOKEN;
258 args.args[1] = 0;
259 args.args[2] = 0;
260 enter_rtas(__pa(&args));
261#endif /* CONFIG_PPC_PSERIES */
262}
263
264#ifdef CONFIG_SMP
265static int xmon_speaker;
266
267static void get_output_lock(void)
268{
269 int me = smp_processor_id() + 0x100;
270 int last_speaker = 0, prev;
271 long timeout;
272
273 if (xmon_speaker == me)
274 return;
275 for (;;) {
276 if (xmon_speaker == 0) {
277 last_speaker = cmpxchg(&xmon_speaker, 0, me);
278 if (last_speaker == 0)
279 return;
280 }
281 timeout = 10000000;
282 while (xmon_speaker == last_speaker) {
283 if (--timeout > 0)
284 continue;
285 /* hostile takeover */
286 prev = cmpxchg(&xmon_speaker, last_speaker, me);
287 if (prev == last_speaker)
288 return;
289 break;
290 }
291 }
292}
293
294static void release_output_lock(void)
295{
296 xmon_speaker = 0;
297}
298#endif
299
300int xmon_core(struct pt_regs *regs, int fromipi)
301{
302 int cmd = 0;
303 unsigned long msr;
304 struct bpt *bp;
305 long recurse_jmp[JMP_BUF_LEN];
306 unsigned long offset;
307#ifdef CONFIG_SMP
308 int cpu;
309 int secondary;
310 unsigned long timeout;
311#endif
312
313 msr = get_msr();
314 set_msrd(msr & ~MSR_EE); /* disable interrupts */
315
316 bp = in_breakpoint_table(regs->nip, &offset);
317 if (bp != NULL) {
318 regs->nip = bp->address + offset;
319 atomic_dec(&bp->ref_count);
320 }
321
322 remove_cpu_bpts();
323
324#ifdef CONFIG_SMP
325 cpu = smp_processor_id();
326 if (cpu_isset(cpu, cpus_in_xmon)) {
327 get_output_lock();
328 excprint(regs);
329 printf("cpu 0x%x: Exception %lx %s in xmon, "
330 "returning to main loop\n",
331 cpu, regs->trap, getvecname(TRAP(regs)));
332 release_output_lock();
333 longjmp(xmon_fault_jmp[cpu], 1);
334 }
335
336 if (setjmp(recurse_jmp) != 0) {
337 if (!in_xmon || !xmon_gate) {
338 get_output_lock();
339 printf("xmon: WARNING: bad recursive fault "
340 "on cpu 0x%x\n", cpu);
341 release_output_lock();
342 goto waiting;
343 }
344 secondary = !(xmon_taken && cpu == xmon_owner);
345 goto cmdloop;
346 }
347
348 xmon_fault_jmp[cpu] = recurse_jmp;
349 cpu_set(cpu, cpus_in_xmon);
350
351 bp = NULL;
352 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) == (MSR_IR|MSR_SF))
353 bp = at_breakpoint(regs->nip);
354 if (bp || (regs->msr & MSR_RI) == 0)
355 fromipi = 0;
356
357 if (!fromipi) {
358 get_output_lock();
359 excprint(regs);
360 if (bp) {
361 printf("cpu 0x%x stopped at breakpoint 0x%x (",
362 cpu, BP_NUM(bp));
363 xmon_print_symbol(regs->nip, " ", ")\n");
364 }
365 if ((regs->msr & MSR_RI) == 0)
366 printf("WARNING: exception is not recoverable, "
367 "can't continue\n");
368 release_output_lock();
369 }
370
371 waiting:
372 secondary = 1;
373 while (secondary && !xmon_gate) {
374 if (in_xmon == 0) {
375 if (fromipi)
376 goto leave;
377 secondary = test_and_set_bit(0, &in_xmon);
378 }
379 barrier();
380 }
381
382 if (!secondary && !xmon_gate) {
383 /* we are the first cpu to come in */
384 /* interrupt other cpu(s) */
385 int ncpus = num_online_cpus();
386
387 xmon_owner = cpu;
388 mb();
389 if (ncpus > 1) {
390 smp_send_debugger_break(MSG_ALL_BUT_SELF);
391 /* wait for other cpus to come in */
392 for (timeout = 100000000; timeout != 0; --timeout) {
393 if (cpus_weight(cpus_in_xmon) >= ncpus)
394 break;
395 barrier();
396 }
397 }
398 remove_bpts();
399 disable_surveillance();
400 /* for breakpoint or single step, print the current instr. */
401 if (bp || TRAP(regs) == 0xd00)
402 ppc_inst_dump(regs->nip, 1, 0);
403 printf("enter ? for help\n");
404 mb();
405 xmon_gate = 1;
406 barrier();
407 }
408
409 cmdloop:
410 while (in_xmon) {
411 if (secondary) {
412 if (cpu == xmon_owner) {
413 if (!test_and_set_bit(0, &xmon_taken)) {
414 secondary = 0;
415 continue;
416 }
417 /* missed it */
418 while (cpu == xmon_owner)
419 barrier();
420 }
421 barrier();
422 } else {
423 cmd = cmds(regs);
424 if (cmd != 0) {
425 /* exiting xmon */
426 insert_bpts();
427 xmon_gate = 0;
428 wmb();
429 in_xmon = 0;
430 break;
431 }
432 /* have switched to some other cpu */
433 secondary = 1;
434 }
435 }
436 leave:
437 cpu_clear(cpu, cpus_in_xmon);
438 xmon_fault_jmp[cpu] = NULL;
439
440#else
441 /* UP is simple... */
442 if (in_xmon) {
443 printf("Exception %lx %s in xmon, returning to main loop\n",
444 regs->trap, getvecname(TRAP(regs)));
445 longjmp(xmon_fault_jmp[0], 1);
446 }
447 if (setjmp(recurse_jmp) == 0) {
448 xmon_fault_jmp[0] = recurse_jmp;
449 in_xmon = 1;
450
451 excprint(regs);
452 bp = at_breakpoint(regs->nip);
453 if (bp) {
454 printf("Stopped at breakpoint %x (", BP_NUM(bp));
455 xmon_print_symbol(regs->nip, " ", ")\n");
456 }
457 if ((regs->msr & MSR_RI) == 0)
458 printf("WARNING: exception is not recoverable, "
459 "can't continue\n");
460 remove_bpts();
461 disable_surveillance();
462 /* for breakpoint or single step, print the current instr. */
463 if (bp || TRAP(regs) == 0xd00)
464 ppc_inst_dump(regs->nip, 1, 0);
465 printf("enter ? for help\n");
466 }
467
468 cmd = cmds(regs);
469
470 insert_bpts();
471 in_xmon = 0;
472#endif
473
474 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) == (MSR_IR|MSR_SF)) {
475 bp = at_breakpoint(regs->nip);
476 if (bp != NULL) {
477 int stepped = emulate_step(regs, bp->instr[0]);
478 if (stepped == 0) {
479 regs->nip = (unsigned long) &bp->instr[0];
480 atomic_inc(&bp->ref_count);
481 } else if (stepped < 0) {
482 printf("Couldn't single-step %s instruction\n",
483 (IS_RFID(bp->instr[0])? "rfid": "mtmsrd"));
484 }
485 }
486 }
487
488 insert_cpu_bpts();
489
490 set_msrd(msr); /* restore interrupt enable */
491
492 return cmd != 'X';
493}
494
495int xmon(struct pt_regs *excp)
496{
497 struct pt_regs regs;
498
499 if (excp == NULL) {
500 /* Ok, grab regs as they are now.
501 This won't do a particularily good job because the
502 prologue has already been executed.
503 ToDo: We could reach back into the callers save
504 area to do a better job of representing the
505 caller's state.
506 */
507 asm volatile ("std 0,0(%0)\n\
508 std 1,8(%0)\n\
509 std 2,16(%0)\n\
510 std 3,24(%0)\n\
511 std 4,32(%0)\n\
512 std 5,40(%0)\n\
513 std 6,48(%0)\n\
514 std 7,56(%0)\n\
515 std 8,64(%0)\n\
516 std 9,72(%0)\n\
517 std 10,80(%0)\n\
518 std 11,88(%0)\n\
519 std 12,96(%0)\n\
520 std 13,104(%0)\n\
521 std 14,112(%0)\n\
522 std 15,120(%0)\n\
523 std 16,128(%0)\n\
524 std 17,136(%0)\n\
525 std 18,144(%0)\n\
526 std 19,152(%0)\n\
527 std 20,160(%0)\n\
528 std 21,168(%0)\n\
529 std 22,176(%0)\n\
530 std 23,184(%0)\n\
531 std 24,192(%0)\n\
532 std 25,200(%0)\n\
533 std 26,208(%0)\n\
534 std 27,216(%0)\n\
535 std 28,224(%0)\n\
536 std 29,232(%0)\n\
537 std 30,240(%0)\n\
538 std 31,248(%0)" : : "b" (&regs));
539
540 regs.nip = regs.link = ((unsigned long *)(regs.gpr[1]))[2];
541 regs.msr = get_msr();
542 regs.ctr = get_ctr();
543 regs.xer = get_xer();
544 regs.ccr = get_cr();
545 regs.trap = 0;
546 excp = &regs;
547 }
548 return xmon_core(excp, 0);
549}
550
551int xmon_bpt(struct pt_regs *regs)
552{
553 struct bpt *bp;
554 unsigned long offset;
555
556 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) != (MSR_IR|MSR_SF))
557 return 0;
558
559 /* Are we at the trap at bp->instr[1] for some bp? */
560 bp = in_breakpoint_table(regs->nip, &offset);
561 if (bp != NULL && offset == 4) {
562 regs->nip = bp->address + 4;
563 atomic_dec(&bp->ref_count);
564 return 1;
565 }
566
567 /* Are we at a breakpoint? */
568 bp = at_breakpoint(regs->nip);
569 if (!bp)
570 return 0;
571
572 xmon_core(regs, 0);
573
574 return 1;
575}
576
577int xmon_sstep(struct pt_regs *regs)
578{
579 if (user_mode(regs))
580 return 0;
581 xmon_core(regs, 0);
582 return 1;
583}
584
585int xmon_dabr_match(struct pt_regs *regs)
586{
587 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) != (MSR_IR|MSR_SF))
588 return 0;
589 if (dabr.enabled == 0)
590 return 0;
591 xmon_core(regs, 0);
592 return 1;
593}
594
595int xmon_iabr_match(struct pt_regs *regs)
596{
597 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) != (MSR_IR|MSR_SF))
598 return 0;
599 if (iabr == 0)
600 return 0;
601 xmon_core(regs, 0);
602 return 1;
603}
604
605int xmon_ipi(struct pt_regs *regs)
606{
607#ifdef CONFIG_SMP
608 if (in_xmon && !cpu_isset(smp_processor_id(), cpus_in_xmon))
609 xmon_core(regs, 1);
610#endif
611 return 0;
612}
613
614int xmon_fault_handler(struct pt_regs *regs)
615{
616 struct bpt *bp;
617 unsigned long offset;
618
619 if (in_xmon && catch_memory_errors)
620 handle_fault(regs); /* doesn't return */
621
622 if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) == (MSR_IR|MSR_SF)) {
623 bp = in_breakpoint_table(regs->nip, &offset);
624 if (bp != NULL) {
625 regs->nip = bp->address + offset;
626 atomic_dec(&bp->ref_count);
627 }
628 }
629
630 return 0;
631}
632
633static struct bpt *at_breakpoint(unsigned long pc)
634{
635 int i;
636 struct bpt *bp;
637
638 bp = bpts;
639 for (i = 0; i < NBPTS; ++i, ++bp)
640 if (bp->enabled && pc == bp->address)
641 return bp;
642 return NULL;
643}
644
645static struct bpt *in_breakpoint_table(unsigned long nip, unsigned long *offp)
646{
647 unsigned long off;
648
649 off = nip - (unsigned long) bpts;
650 if (off >= sizeof(bpts))
651 return NULL;
652 off %= sizeof(struct bpt);
653 if (off != offsetof(struct bpt, instr[0])
654 && off != offsetof(struct bpt, instr[1]))
655 return NULL;
656 *offp = off - offsetof(struct bpt, instr[0]);
657 return (struct bpt *) (nip - off);
658}
659
660static struct bpt *new_breakpoint(unsigned long a)
661{
662 struct bpt *bp;
663
664 a &= ~3UL;
665 bp = at_breakpoint(a);
666 if (bp)
667 return bp;
668
669 for (bp = bpts; bp < &bpts[NBPTS]; ++bp) {
670 if (!bp->enabled && atomic_read(&bp->ref_count) == 0) {
671 bp->address = a;
672 bp->instr[1] = bpinstr;
673 store_inst(&bp->instr[1]);
674 return bp;
675 }
676 }
677
678 printf("Sorry, no free breakpoints. Please clear one first.\n");
679 return NULL;
680}
681
682static void insert_bpts(void)
683{
684 int i;
685 struct bpt *bp;
686
687 bp = bpts;
688 for (i = 0; i < NBPTS; ++i, ++bp) {
689 if ((bp->enabled & (BP_TRAP|BP_IABR)) == 0)
690 continue;
691 if (mread(bp->address, &bp->instr[0], 4) != 4) {
692 printf("Couldn't read instruction at %lx, "
693 "disabling breakpoint there\n", bp->address);
694 bp->enabled = 0;
695 continue;
696 }
697 if (IS_MTMSRD(bp->instr[0]) || IS_RFID(bp->instr[0])) {
698 printf("Breakpoint at %lx is on an mtmsrd or rfid "
699 "instruction, disabling it\n", bp->address);
700 bp->enabled = 0;
701 continue;
702 }
703 store_inst(&bp->instr[0]);
704 if (bp->enabled & BP_IABR)
705 continue;
706 if (mwrite(bp->address, &bpinstr, 4) != 4) {
707 printf("Couldn't write instruction at %lx, "
708 "disabling breakpoint there\n", bp->address);
709 bp->enabled &= ~BP_TRAP;
710 continue;
711 }
712 store_inst((void *)bp->address);
713 }
714}
715
716static void insert_cpu_bpts(void)
717{
718 if (dabr.enabled)
719 set_dabr(dabr.address | (dabr.enabled & 7));
720 if (iabr && cpu_has_feature(CPU_FTR_IABR))
721 set_iabr(iabr->address
722 | (iabr->enabled & (BP_IABR|BP_IABR_TE)));
723}
724
725static void remove_bpts(void)
726{
727 int i;
728 struct bpt *bp;
729 unsigned instr;
730
731 bp = bpts;
732 for (i = 0; i < NBPTS; ++i, ++bp) {
733 if ((bp->enabled & (BP_TRAP|BP_IABR)) != BP_TRAP)
734 continue;
735 if (mread(bp->address, &instr, 4) == 4
736 && instr == bpinstr
737 && mwrite(bp->address, &bp->instr, 4) != 4)
738 printf("Couldn't remove breakpoint at %lx\n",
739 bp->address);
740 else
741 store_inst((void *)bp->address);
742 }
743}
744
745static void remove_cpu_bpts(void)
746{
747 set_dabr(0);
748 if (cpu_has_feature(CPU_FTR_IABR))
749 set_iabr(0);
750}
751
752/* Command interpreting routine */
753static char *last_cmd;
754
755static int
756cmds(struct pt_regs *excp)
757{
758 int cmd = 0;
759
760 last_cmd = NULL;
761 xmon_regs = excp;
762 for(;;) {
763#ifdef CONFIG_SMP
764 printf("%x:", smp_processor_id());
765#endif /* CONFIG_SMP */
766 printf("mon> ");
767 fflush(stdout);
768 flush_input();
769 termch = 0;
770 cmd = skipbl();
771 if( cmd == '\n' ) {
772 if (last_cmd == NULL)
773 continue;
774 take_input(last_cmd);
775 last_cmd = NULL;
776 cmd = inchar();
777 }
778 switch (cmd) {
779 case 'm':
780 cmd = inchar();
781 switch (cmd) {
782 case 'm':
783 case 's':
784 case 'd':
785 memops(cmd);
786 break;
787 case 'l':
788 memlocate();
789 break;
790 case 'z':
791 memzcan();
792 break;
793 case 'i':
794 show_mem();
795 break;
796 default:
797 termch = cmd;
798 memex();
799 }
800 break;
801 case 'd':
802 dump();
803 break;
804 case 'l':
805 symbol_lookup();
806 break;
807 case 'r':
808 prregs(excp); /* print regs */
809 break;
810 case 'e':
811 excprint(excp);
812 break;
813 case 'S':
814 super_regs();
815 break;
816 case 't':
817 backtrace(excp);
818 break;
819 case 'f':
820 cacheflush();
821 break;
822 case 's':
823 if (do_step(excp))
824 return cmd;
825 break;
826 case 'x':
827 case 'X':
828 case EOF:
829 return cmd;
830 case '?':
831 printf(help_string);
832 break;
833 case 'p':
834 show_state();
835 break;
836 case 'b':
837 bpt_cmds();
838 break;
839 case 'C':
840 csum();
841 break;
842 case 'c':
843 if (cpu_cmd())
844 return 0;
845 break;
846 case 'z':
847 bootcmds();
848 break;
849 case 'T':
850 debug_trace();
851 break;
852 case 'u':
853 dump_segments();
854 break;
855 default:
856 printf("Unrecognized command: ");
857 do {
858 if (' ' < cmd && cmd <= '~')
859 putchar(cmd);
860 else
861 printf("\\x%x", cmd);
862 cmd = inchar();
863 } while (cmd != '\n');
864 printf(" (type ? for help)\n");
865 break;
866 }
867 }
868}
869
870/*
871 * Step a single instruction.
872 * Some instructions we emulate, others we execute with MSR_SE set.
873 */
874static int do_step(struct pt_regs *regs)
875{
876 unsigned int instr;
877 int stepped;
878
879 /* check we are in 64-bit kernel mode, translation enabled */
880 if ((regs->msr & (MSR_SF|MSR_PR|MSR_IR)) == (MSR_SF|MSR_IR)) {
881 if (mread(regs->nip, &instr, 4) == 4) {
882 stepped = emulate_step(regs, instr);
883 if (stepped < 0) {
884 printf("Couldn't single-step %s instruction\n",
885 (IS_RFID(instr)? "rfid": "mtmsrd"));
886 return 0;
887 }
888 if (stepped > 0) {
889 regs->trap = 0xd00 | (regs->trap & 1);
890 printf("stepped to ");
891 xmon_print_symbol(regs->nip, " ", "\n");
892 ppc_inst_dump(regs->nip, 1, 0);
893 return 0;
894 }
895 }
896 }
897 regs->msr |= MSR_SE;
898 return 1;
899}
900
901static void bootcmds(void)
902{
903 int cmd;
904
905 cmd = inchar();
906 if (cmd == 'r')
907 ppc_md.restart(NULL);
908 else if (cmd == 'h')
909 ppc_md.halt();
910 else if (cmd == 'p')
911 ppc_md.power_off();
912}
913
914static int cpu_cmd(void)
915{
916#ifdef CONFIG_SMP
917 unsigned long cpu;
918 int timeout;
919 int count;
920
921 if (!scanhex(&cpu)) {
922 /* print cpus waiting or in xmon */
923 printf("cpus stopped:");
924 count = 0;
925 for (cpu = 0; cpu < NR_CPUS; ++cpu) {
926 if (cpu_isset(cpu, cpus_in_xmon)) {
927 if (count == 0)
928 printf(" %x", cpu);
929 ++count;
930 } else {
931 if (count > 1)
932 printf("-%x", cpu - 1);
933 count = 0;
934 }
935 }
936 if (count > 1)
937 printf("-%x", NR_CPUS - 1);
938 printf("\n");
939 return 0;
940 }
941 /* try to switch to cpu specified */
942 if (!cpu_isset(cpu, cpus_in_xmon)) {
943 printf("cpu 0x%x isn't in xmon\n", cpu);
944 return 0;
945 }
946 xmon_taken = 0;
947 mb();
948 xmon_owner = cpu;
949 timeout = 10000000;
950 while (!xmon_taken) {
951 if (--timeout == 0) {
952 if (test_and_set_bit(0, &xmon_taken))
953 break;
954 /* take control back */
955 mb();
956 xmon_owner = smp_processor_id();
957 printf("cpu %u didn't take control\n", cpu);
958 return 0;
959 }
960 barrier();
961 }
962 return 1;
963#else
964 return 0;
965#endif /* CONFIG_SMP */
966}
967
968static unsigned short fcstab[256] = {
969 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
970 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
971 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
972 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
973 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
974 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
975 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
976 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
977 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
978 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
979 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
980 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
981 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
982 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
983 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
984 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
985 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
986 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
987 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
988 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
989 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
990 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
991 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
992 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
993 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
994 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
995 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
996 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
997 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
998 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
999 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
1000 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
1001};
1002
1003#define FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
1004
1005static void
1006csum(void)
1007{
1008 unsigned int i;
1009 unsigned short fcs;
1010 unsigned char v;
1011
1012 if (!scanhex(&adrs))
1013 return;
1014 if (!scanhex(&ncsum))
1015 return;
1016 fcs = 0xffff;
1017 for (i = 0; i < ncsum; ++i) {
1018 if (mread(adrs+i, &v, 1) == 0) {
1019 printf("csum stopped at %x\n", adrs+i);
1020 break;
1021 }
1022 fcs = FCS(fcs, v);
1023 }
1024 printf("%x\n", fcs);
1025}
1026
1027/*
1028 * Check if this is a suitable place to put a breakpoint.
1029 */
1030static long check_bp_loc(unsigned long addr)
1031{
1032 unsigned int instr;
1033
1034 addr &= ~3;
1035 if (addr < KERNELBASE) {
1036 printf("Breakpoints may only be placed at kernel addresses\n");
1037 return 0;
1038 }
1039 if (!mread(addr, &instr, sizeof(instr))) {
1040 printf("Can't read instruction at address %lx\n", addr);
1041 return 0;
1042 }
1043 if (IS_MTMSRD(instr) || IS_RFID(instr)) {
1044 printf("Breakpoints may not be placed on mtmsrd or rfid "
1045 "instructions\n");
1046 return 0;
1047 }
1048 return 1;
1049}
1050
1051static char *breakpoint_help_string =
1052 "Breakpoint command usage:\n"
1053 "b show breakpoints\n"
1054 "b <addr> [cnt] set breakpoint at given instr addr\n"
1055 "bc clear all breakpoints\n"
1056 "bc <n/addr> clear breakpoint number n or at addr\n"
1057 "bi <addr> [cnt] set hardware instr breakpoint (POWER3/RS64 only)\n"
1058 "bd <addr> [cnt] set hardware data breakpoint\n"
1059 "";
1060
1061static void
1062bpt_cmds(void)
1063{
1064 int cmd;
1065 unsigned long a;
1066 int mode, i;
1067 struct bpt *bp;
1068 const char badaddr[] = "Only kernel addresses are permitted "
1069 "for breakpoints\n";
1070
1071 cmd = inchar();
1072 switch (cmd) {
1073 case 'd': /* bd - hardware data breakpoint */
1074 mode = 7;
1075 cmd = inchar();
1076 if (cmd == 'r')
1077 mode = 5;
1078 else if (cmd == 'w')
1079 mode = 6;
1080 else
1081 termch = cmd;
1082 dabr.address = 0;
1083 dabr.enabled = 0;
1084 if (scanhex(&dabr.address)) {
1085 if (dabr.address < KERNELBASE) {
1086 printf(badaddr);
1087 break;
1088 }
1089 dabr.address &= ~7;
1090 dabr.enabled = mode | BP_DABR;
1091 }
1092 break;
1093
1094 case 'i': /* bi - hardware instr breakpoint */
1095 if (!cpu_has_feature(CPU_FTR_IABR)) {
1096 printf("Hardware instruction breakpoint "
1097 "not supported on this cpu\n");
1098 break;
1099 }
1100 if (iabr) {
1101 iabr->enabled &= ~(BP_IABR | BP_IABR_TE);
1102 iabr = NULL;
1103 }
1104 if (!scanhex(&a))
1105 break;
1106 if (!check_bp_loc(a))
1107 break;
1108 bp = new_breakpoint(a);
1109 if (bp != NULL) {
1110 bp->enabled |= BP_IABR | BP_IABR_TE;
1111 iabr = bp;
1112 }
1113 break;
1114
1115 case 'c':
1116 if (!scanhex(&a)) {
1117 /* clear all breakpoints */
1118 for (i = 0; i < NBPTS; ++i)
1119 bpts[i].enabled = 0;
1120 iabr = NULL;
1121 dabr.enabled = 0;
1122 printf("All breakpoints cleared\n");
1123 break;
1124 }
1125
1126 if (a <= NBPTS && a >= 1) {
1127 /* assume a breakpoint number */
1128 bp = &bpts[a-1]; /* bp nums are 1 based */
1129 } else {
1130 /* assume a breakpoint address */
1131 bp = at_breakpoint(a);
1132 if (bp == 0) {
1133 printf("No breakpoint at %x\n", a);
1134 break;
1135 }
1136 }
1137
1138 printf("Cleared breakpoint %x (", BP_NUM(bp));
1139 xmon_print_symbol(bp->address, " ", ")\n");
1140 bp->enabled = 0;
1141 break;
1142
1143 default:
1144 termch = cmd;
1145 cmd = skipbl();
1146 if (cmd == '?') {
1147 printf(breakpoint_help_string);
1148 break;
1149 }
1150 termch = cmd;
1151 if (!scanhex(&a)) {
1152 /* print all breakpoints */
1153 printf(" type address\n");
1154 if (dabr.enabled) {
1155 printf(" data %.16lx [", dabr.address);
1156 if (dabr.enabled & 1)
1157 printf("r");
1158 if (dabr.enabled & 2)
1159 printf("w");
1160 printf("]\n");
1161 }
1162 for (bp = bpts; bp < &bpts[NBPTS]; ++bp) {
1163 if (!bp->enabled)
1164 continue;
1165 printf("%2x %s ", BP_NUM(bp),
1166 (bp->enabled & BP_IABR)? "inst": "trap");
1167 xmon_print_symbol(bp->address, " ", "\n");
1168 }
1169 break;
1170 }
1171
1172 if (!check_bp_loc(a))
1173 break;
1174 bp = new_breakpoint(a);
1175 if (bp != NULL)
1176 bp->enabled |= BP_TRAP;
1177 break;
1178 }
1179}
1180
1181/* Very cheap human name for vector lookup. */
1182static
1183const char *getvecname(unsigned long vec)
1184{
1185 char *ret;
1186
1187 switch (vec) {
1188 case 0x100: ret = "(System Reset)"; break;
1189 case 0x200: ret = "(Machine Check)"; break;
1190 case 0x300: ret = "(Data Access)"; break;
1191 case 0x380: ret = "(Data SLB Access)"; break;
1192 case 0x400: ret = "(Instruction Access)"; break;
1193 case 0x480: ret = "(Instruction SLB Access)"; break;
1194 case 0x500: ret = "(Hardware Interrupt)"; break;
1195 case 0x600: ret = "(Alignment)"; break;
1196 case 0x700: ret = "(Program Check)"; break;
1197 case 0x800: ret = "(FPU Unavailable)"; break;
1198 case 0x900: ret = "(Decrementer)"; break;
1199 case 0xc00: ret = "(System Call)"; break;
1200 case 0xd00: ret = "(Single Step)"; break;
1201 case 0xf00: ret = "(Performance Monitor)"; break;
1202 case 0xf20: ret = "(Altivec Unavailable)"; break;
1203 case 0x1300: ret = "(Instruction Breakpoint)"; break;
1204 default: ret = "";
1205 }
1206 return ret;
1207}
1208
1209static void get_function_bounds(unsigned long pc, unsigned long *startp,
1210 unsigned long *endp)
1211{
1212 unsigned long size, offset;
1213 const char *name;
1214 char *modname;
1215
1216 *startp = *endp = 0;
1217 if (pc == 0)
1218 return;
1219 if (setjmp(bus_error_jmp) == 0) {
1220 catch_memory_errors = 1;
1221 sync();
1222 name = kallsyms_lookup(pc, &size, &offset, &modname, tmpstr);
1223 if (name != NULL) {
1224 *startp = pc - offset;
1225 *endp = pc - offset + size;
1226 }
1227 sync();
1228 }
1229 catch_memory_errors = 0;
1230}
1231
1232static int xmon_depth_to_print = 64;
1233
1234static void xmon_show_stack(unsigned long sp, unsigned long lr,
1235 unsigned long pc)
1236{
1237 unsigned long ip;
1238 unsigned long newsp;
1239 unsigned long marker;
1240 int count = 0;
1241 struct pt_regs regs;
1242
1243 do {
1244 if (sp < PAGE_OFFSET) {
1245 if (sp != 0)
1246 printf("SP (%lx) is in userspace\n", sp);
1247 break;
1248 }
1249
1250 if (!mread(sp + 16, &ip, sizeof(unsigned long))
1251 || !mread(sp, &newsp, sizeof(unsigned long))) {
1252 printf("Couldn't read stack frame at %lx\n", sp);
1253 break;
1254 }
1255
1256 /*
1257 * For the first stack frame, try to work out if
1258 * LR and/or the saved LR value in the bottommost
1259 * stack frame are valid.
1260 */
1261 if ((pc | lr) != 0) {
1262 unsigned long fnstart, fnend;
1263 unsigned long nextip;
1264 int printip = 1;
1265
1266 get_function_bounds(pc, &fnstart, &fnend);
1267 nextip = 0;
1268 if (newsp > sp)
1269 mread(newsp + 16, &nextip,
1270 sizeof(unsigned long));
1271 if (lr == ip) {
1272 if (lr < PAGE_OFFSET
1273 || (fnstart <= lr && lr < fnend))
1274 printip = 0;
1275 } else if (lr == nextip) {
1276 printip = 0;
1277 } else if (lr >= PAGE_OFFSET
1278 && !(fnstart <= lr && lr < fnend)) {
1279 printf("[link register ] ");
1280 xmon_print_symbol(lr, " ", "\n");
1281 }
1282 if (printip) {
1283 printf("[%.16lx] ", sp);
1284 xmon_print_symbol(ip, " ", " (unreliable)\n");
1285 }
1286 pc = lr = 0;
1287
1288 } else {
1289 printf("[%.16lx] ", sp);
1290 xmon_print_symbol(ip, " ", "\n");
1291 }
1292
1293 /* Look for "regshere" marker to see if this is
1294 an exception frame. */
1295 if (mread(sp + 0x60, &marker, sizeof(unsigned long))
1296 && marker == 0x7265677368657265ul) {
1297 if (mread(sp + 0x70, &regs, sizeof(regs))
1298 != sizeof(regs)) {
1299 printf("Couldn't read registers at %lx\n",
1300 sp + 0x70);
1301 break;
1302 }
1303 printf("--- Exception: %lx %s at ", regs.trap,
1304 getvecname(TRAP(&regs)));
1305 pc = regs.nip;
1306 lr = regs.link;
1307 xmon_print_symbol(pc, " ", "\n");
1308 }
1309
1310 if (newsp == 0)
1311 break;
1312
1313 sp = newsp;
1314 } while (count++ < xmon_depth_to_print);
1315}
1316
1317static void backtrace(struct pt_regs *excp)
1318{
1319 unsigned long sp;
1320
1321 if (scanhex(&sp))
1322 xmon_show_stack(sp, 0, 0);
1323 else
1324 xmon_show_stack(excp->gpr[1], excp->link, excp->nip);
1325 scannl();
1326}
1327
1328static void print_bug_trap(struct pt_regs *regs)
1329{
1330 struct bug_entry *bug;
1331 unsigned long addr;
1332
1333 if (regs->msr & MSR_PR)
1334 return; /* not in kernel */
1335 addr = regs->nip; /* address of trap instruction */
1336 if (addr < PAGE_OFFSET)
1337 return;
1338 bug = find_bug(regs->nip);
1339 if (bug == NULL)
1340 return;
1341 if (bug->line & BUG_WARNING_TRAP)
1342 return;
1343
1344 printf("kernel BUG in %s at %s:%d!\n",
1345 bug->function, bug->file, (unsigned int)bug->line);
1346}
1347
1348void excprint(struct pt_regs *fp)
1349{
1350 unsigned long trap;
1351
1352#ifdef CONFIG_SMP
1353 printf("cpu 0x%x: ", smp_processor_id());
1354#endif /* CONFIG_SMP */
1355
1356 trap = TRAP(fp);
1357 printf("Vector: %lx %s at [%lx]\n", fp->trap, getvecname(trap), fp);
1358 printf(" pc: ");
1359 xmon_print_symbol(fp->nip, ": ", "\n");
1360
1361 printf(" lr: ", fp->link);
1362 xmon_print_symbol(fp->link, ": ", "\n");
1363
1364 printf(" sp: %lx\n", fp->gpr[1]);
1365 printf(" msr: %lx\n", fp->msr);
1366
1367 if (trap == 0x300 || trap == 0x380 || trap == 0x600) {
1368 printf(" dar: %lx\n", fp->dar);
1369 if (trap != 0x380)
1370 printf(" dsisr: %lx\n", fp->dsisr);
1371 }
1372
1373 printf(" current = 0x%lx\n", current);
1374 printf(" paca = 0x%lx\n", get_paca());
1375 if (current) {
1376 printf(" pid = %ld, comm = %s\n",
1377 current->pid, current->comm);
1378 }
1379
1380 if (trap == 0x700)
1381 print_bug_trap(fp);
1382}
1383
1384void prregs(struct pt_regs *fp)
1385{
1386 int n;
1387 unsigned long base;
1388 struct pt_regs regs;
1389
1390 if (scanhex(&base)) {
1391 if (setjmp(bus_error_jmp) == 0) {
1392 catch_memory_errors = 1;
1393 sync();
1394 regs = *(struct pt_regs *)base;
1395 sync();
1396 __delay(200);
1397 } else {
1398 catch_memory_errors = 0;
1399 printf("*** Error reading registers from %.16lx\n",
1400 base);
1401 return;
1402 }
1403 catch_memory_errors = 0;
1404 fp = &regs;
1405 }
1406
1407 if (FULL_REGS(fp)) {
1408 for (n = 0; n < 16; ++n)
1409 printf("R%.2ld = %.16lx R%.2ld = %.16lx\n",
1410 n, fp->gpr[n], n+16, fp->gpr[n+16]);
1411 } else {
1412 for (n = 0; n < 7; ++n)
1413 printf("R%.2ld = %.16lx R%.2ld = %.16lx\n",
1414 n, fp->gpr[n], n+7, fp->gpr[n+7]);
1415 }
1416 printf("pc = ");
1417 xmon_print_symbol(fp->nip, " ", "\n");
1418 printf("lr = ");
1419 xmon_print_symbol(fp->link, " ", "\n");
1420 printf("msr = %.16lx cr = %.8lx\n", fp->msr, fp->ccr);
1421 printf("ctr = %.16lx xer = %.16lx trap = %8lx\n",
1422 fp->ctr, fp->xer, fp->trap);
1423}
1424
1425void cacheflush(void)
1426{
1427 int cmd;
1428 unsigned long nflush;
1429
1430 cmd = inchar();
1431 if (cmd != 'i')
1432 termch = cmd;
1433 scanhex((void *)&adrs);
1434 if (termch != '\n')
1435 termch = 0;
1436 nflush = 1;
1437 scanhex(&nflush);
1438 nflush = (nflush + L1_CACHE_BYTES - 1) / L1_CACHE_BYTES;
1439 if (setjmp(bus_error_jmp) == 0) {
1440 catch_memory_errors = 1;
1441 sync();
1442
1443 if (cmd != 'i') {
1444 for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
1445 cflush((void *) adrs);
1446 } else {
1447 for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
1448 cinval((void *) adrs);
1449 }
1450 sync();
1451 /* wait a little while to see if we get a machine check */
1452 __delay(200);
1453 }
1454 catch_memory_errors = 0;
1455}
1456
1457unsigned long
1458read_spr(int n)
1459{
1460 unsigned int instrs[2];
1461 unsigned long (*code)(void);
1462 unsigned long opd[3];
1463 unsigned long ret = -1UL;
1464
1465 instrs[0] = 0x7c6002a6 + ((n & 0x1F) << 16) + ((n & 0x3e0) << 6);
1466 instrs[1] = 0x4e800020;
1467 opd[0] = (unsigned long)instrs;
1468 opd[1] = 0;
1469 opd[2] = 0;
1470 store_inst(instrs);
1471 store_inst(instrs+1);
1472 code = (unsigned long (*)(void)) opd;
1473
1474 if (setjmp(bus_error_jmp) == 0) {
1475 catch_memory_errors = 1;
1476 sync();
1477
1478 ret = code();
1479
1480 sync();
1481 /* wait a little while to see if we get a machine check */
1482 __delay(200);
1483 n = size;
1484 }
1485
1486 return ret;
1487}
1488
1489void
1490write_spr(int n, unsigned long val)
1491{
1492 unsigned int instrs[2];
1493 unsigned long (*code)(unsigned long);
1494 unsigned long opd[3];
1495
1496 instrs[0] = 0x7c6003a6 + ((n & 0x1F) << 16) + ((n & 0x3e0) << 6);
1497 instrs[1] = 0x4e800020;
1498 opd[0] = (unsigned long)instrs;
1499 opd[1] = 0;
1500 opd[2] = 0;
1501 store_inst(instrs);
1502 store_inst(instrs+1);
1503 code = (unsigned long (*)(unsigned long)) opd;
1504
1505 if (setjmp(bus_error_jmp) == 0) {
1506 catch_memory_errors = 1;
1507 sync();
1508
1509 code(val);
1510
1511 sync();
1512 /* wait a little while to see if we get a machine check */
1513 __delay(200);
1514 n = size;
1515 }
1516}
1517
1518static unsigned long regno;
1519extern char exc_prolog;
1520extern char dec_exc;
1521
1522void
1523super_regs(void)
1524{
1525 int cmd;
1526 unsigned long val;
1527#ifdef CONFIG_PPC_ISERIES
1528 struct paca_struct *ptrPaca = NULL;
1529 struct lppaca *ptrLpPaca = NULL;
1530 struct ItLpRegSave *ptrLpRegSave = NULL;
1531#endif
1532
1533 cmd = skipbl();
1534 if (cmd == '\n') {
1535 unsigned long sp, toc;
1536 asm("mr %0,1" : "=r" (sp) :);
1537 asm("mr %0,2" : "=r" (toc) :);
1538
1539 printf("msr = %.16lx sprg0= %.16lx\n", get_msr(), get_sprg0());
1540 printf("pvr = %.16lx sprg1= %.16lx\n", get_pvr(), get_sprg1());
1541 printf("dec = %.16lx sprg2= %.16lx\n", get_dec(), get_sprg2());
1542 printf("sp = %.16lx sprg3= %.16lx\n", sp, get_sprg3());
1543 printf("toc = %.16lx dar = %.16lx\n", toc, get_dar());
1544 printf("srr0 = %.16lx srr1 = %.16lx\n", get_srr0(), get_srr1());
1545#ifdef CONFIG_PPC_ISERIES
1546 // Dump out relevant Paca data areas.
1547 printf("Paca: \n");
1548 ptrPaca = get_paca();
1549
1550 printf(" Local Processor Control Area (LpPaca): \n");
1551 ptrLpPaca = ptrPaca->lppaca_ptr;
1552 printf(" Saved Srr0=%.16lx Saved Srr1=%.16lx \n",
1553 ptrLpPaca->saved_srr0, ptrLpPaca->saved_srr1);
1554 printf(" Saved Gpr3=%.16lx Saved Gpr4=%.16lx \n",
1555 ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4);
1556 printf(" Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5);
1557
1558 printf(" Local Processor Register Save Area (LpRegSave): \n");
1559 ptrLpRegSave = ptrPaca->reg_save_ptr;
1560 printf(" Saved Sprg0=%.16lx Saved Sprg1=%.16lx \n",
1561 ptrLpRegSave->xSPRG0, ptrLpRegSave->xSPRG0);
1562 printf(" Saved Sprg2=%.16lx Saved Sprg3=%.16lx \n",
1563 ptrLpRegSave->xSPRG2, ptrLpRegSave->xSPRG3);
1564 printf(" Saved Msr =%.16lx Saved Nia =%.16lx \n",
1565 ptrLpRegSave->xMSR, ptrLpRegSave->xNIA);
1566#endif
1567
1568 return;
1569 }
1570
1571 scanhex(&regno);
1572 switch (cmd) {
1573 case 'w':
1574 val = read_spr(regno);
1575 scanhex(&val);
1576 write_spr(regno, val);
1577 /* fall through */
1578 case 'r':
1579 printf("spr %lx = %lx\n", regno, read_spr(regno));
1580 break;
1581 case 'm':
1582 val = get_msr();
1583 scanhex(&val);
1584 set_msrd(val);
1585 break;
1586 }
1587 scannl();
1588}
1589
1590/*
1591 * Stuff for reading and writing memory safely
1592 */
1593int
1594mread(unsigned long adrs, void *buf, int size)
1595{
1596 volatile int n;
1597 char *p, *q;
1598
1599 n = 0;
1600 if (setjmp(bus_error_jmp) == 0) {
1601 catch_memory_errors = 1;
1602 sync();
1603 p = (char *)adrs;
1604 q = (char *)buf;
1605 switch (size) {
1606 case 2:
1607 *(short *)q = *(short *)p;
1608 break;
1609 case 4:
1610 *(int *)q = *(int *)p;
1611 break;
1612 case 8:
1613 *(long *)q = *(long *)p;
1614 break;
1615 default:
1616 for( ; n < size; ++n) {
1617 *q++ = *p++;
1618 sync();
1619 }
1620 }
1621 sync();
1622 /* wait a little while to see if we get a machine check */
1623 __delay(200);
1624 n = size;
1625 }
1626 catch_memory_errors = 0;
1627 return n;
1628}
1629
1630int
1631mwrite(unsigned long adrs, void *buf, int size)
1632{
1633 volatile int n;
1634 char *p, *q;
1635
1636 n = 0;
1637 if (setjmp(bus_error_jmp) == 0) {
1638 catch_memory_errors = 1;
1639 sync();
1640 p = (char *) adrs;
1641 q = (char *) buf;
1642 switch (size) {
1643 case 2:
1644 *(short *)p = *(short *)q;
1645 break;
1646 case 4:
1647 *(int *)p = *(int *)q;
1648 break;
1649 case 8:
1650 *(long *)p = *(long *)q;
1651 break;
1652 default:
1653 for ( ; n < size; ++n) {
1654 *p++ = *q++;
1655 sync();
1656 }
1657 }
1658 sync();
1659 /* wait a little while to see if we get a machine check */
1660 __delay(200);
1661 n = size;
1662 } else {
1663 printf("*** Error writing address %x\n", adrs + n);
1664 }
1665 catch_memory_errors = 0;
1666 return n;
1667}
1668
1669static int fault_type;
1670static char *fault_chars[] = { "--", "**", "##" };
1671
1672static int
1673handle_fault(struct pt_regs *regs)
1674{
1675 switch (TRAP(regs)) {
1676 case 0x200:
1677 fault_type = 0;
1678 break;
1679 case 0x300:
1680 case 0x380:
1681 fault_type = 1;
1682 break;
1683 default:
1684 fault_type = 2;
1685 }
1686
1687 longjmp(bus_error_jmp, 1);
1688
1689 return 0;
1690}
1691
1692#define SWAP(a, b, t) ((t) = (a), (a) = (b), (b) = (t))
1693
1694void
1695byterev(unsigned char *val, int size)
1696{
1697 int t;
1698
1699 switch (size) {
1700 case 2:
1701 SWAP(val[0], val[1], t);
1702 break;
1703 case 4:
1704 SWAP(val[0], val[3], t);
1705 SWAP(val[1], val[2], t);
1706 break;
1707 case 8: /* is there really any use for this? */
1708 SWAP(val[0], val[7], t);
1709 SWAP(val[1], val[6], t);
1710 SWAP(val[2], val[5], t);
1711 SWAP(val[3], val[4], t);
1712 break;
1713 }
1714}
1715
1716static int brev;
1717static int mnoread;
1718
1719static char *memex_help_string =
1720 "Memory examine command usage:\n"
1721 "m [addr] [flags] examine/change memory\n"
1722 " addr is optional. will start where left off.\n"
1723 " flags may include chars from this set:\n"
1724 " b modify by bytes (default)\n"
1725 " w modify by words (2 byte)\n"
1726 " l modify by longs (4 byte)\n"
1727 " d modify by doubleword (8 byte)\n"
1728 " r toggle reverse byte order mode\n"
1729 " n do not read memory (for i/o spaces)\n"
1730 " . ok to read (default)\n"
1731 "NOTE: flags are saved as defaults\n"
1732 "";
1733
1734static char *memex_subcmd_help_string =
1735 "Memory examine subcommands:\n"
1736 " hexval write this val to current location\n"
1737 " 'string' write chars from string to this location\n"
1738 " ' increment address\n"
1739 " ^ decrement address\n"
1740 " / increment addr by 0x10. //=0x100, ///=0x1000, etc\n"
1741 " \\ decrement addr by 0x10. \\\\=0x100, \\\\\\=0x1000, etc\n"
1742 " ` clear no-read flag\n"
1743 " ; stay at this addr\n"
1744 " v change to byte mode\n"
1745 " w change to word (2 byte) mode\n"
1746 " l change to long (4 byte) mode\n"
1747 " u change to doubleword (8 byte) mode\n"
1748 " m addr change current addr\n"
1749 " n toggle no-read flag\n"
1750 " r toggle byte reverse flag\n"
1751 " < count back up count bytes\n"
1752 " > count skip forward count bytes\n"
1753 " x exit this mode\n"
1754 "";
1755
1756void
1757memex(void)
1758{
1759 int cmd, inc, i, nslash;
1760 unsigned long n;
1761 unsigned char val[16];
1762
1763 scanhex((void *)&adrs);
1764 cmd = skipbl();
1765 if (cmd == '?') {
1766 printf(memex_help_string);
1767 return;
1768 } else {
1769 termch = cmd;
1770 }
1771 last_cmd = "m\n";
1772 while ((cmd = skipbl()) != '\n') {
1773 switch( cmd ){
1774 case 'b': size = 1; break;
1775 case 'w': size = 2; break;
1776 case 'l': size = 4; break;
1777 case 'd': size = 8; break;
1778 case 'r': brev = !brev; break;
1779 case 'n': mnoread = 1; break;
1780 case '.': mnoread = 0; break;
1781 }
1782 }
1783 if( size <= 0 )
1784 size = 1;
1785 else if( size > 8 )
1786 size = 8;
1787 for(;;){
1788 if (!mnoread)
1789 n = mread(adrs, val, size);
1790 printf("%.16x%c", adrs, brev? 'r': ' ');
1791 if (!mnoread) {
1792 if (brev)
1793 byterev(val, size);
1794 putchar(' ');
1795 for (i = 0; i < n; ++i)
1796 printf("%.2x", val[i]);
1797 for (; i < size; ++i)
1798 printf("%s", fault_chars[fault_type]);
1799 }
1800 putchar(' ');
1801 inc = size;
1802 nslash = 0;
1803 for(;;){
1804 if( scanhex(&n) ){
1805 for (i = 0; i < size; ++i)
1806 val[i] = n >> (i * 8);
1807 if (!brev)
1808 byterev(val, size);
1809 mwrite(adrs, val, size);
1810 inc = size;
1811 }
1812 cmd = skipbl();
1813 if (cmd == '\n')
1814 break;
1815 inc = 0;
1816 switch (cmd) {
1817 case '\'':
1818 for(;;){
1819 n = inchar();
1820 if( n == '\\' )
1821 n = bsesc();
1822 else if( n == '\'' )
1823 break;
1824 for (i = 0; i < size; ++i)
1825 val[i] = n >> (i * 8);
1826 if (!brev)
1827 byterev(val, size);
1828 mwrite(adrs, val, size);
1829 adrs += size;
1830 }
1831 adrs -= size;
1832 inc = size;
1833 break;
1834 case ',':
1835 adrs += size;
1836 break;
1837 case '.':
1838 mnoread = 0;
1839 break;
1840 case ';':
1841 break;
1842 case 'x':
1843 case EOF:
1844 scannl();
1845 return;
1846 case 'b':
1847 case 'v':
1848 size = 1;
1849 break;
1850 case 'w':
1851 size = 2;
1852 break;
1853 case 'l':
1854 size = 4;
1855 break;
1856 case 'u':
1857 size = 8;
1858 break;
1859 case '^':
1860 adrs -= size;
1861 break;
1862 break;
1863 case '/':
1864 if (nslash > 0)
1865 adrs -= 1 << nslash;
1866 else
1867 nslash = 0;
1868 nslash += 4;
1869 adrs += 1 << nslash;
1870 break;
1871 case '\\':
1872 if (nslash < 0)
1873 adrs += 1 << -nslash;
1874 else
1875 nslash = 0;
1876 nslash -= 4;
1877 adrs -= 1 << -nslash;
1878 break;
1879 case 'm':
1880 scanhex((void *)&adrs);
1881 break;
1882 case 'n':
1883 mnoread = 1;
1884 break;
1885 case 'r':
1886 brev = !brev;
1887 break;
1888 case '<':
1889 n = size;
1890 scanhex(&n);
1891 adrs -= n;
1892 break;
1893 case '>':
1894 n = size;
1895 scanhex(&n);
1896 adrs += n;
1897 break;
1898 case '?':
1899 printf(memex_subcmd_help_string);
1900 break;
1901 }
1902 }
1903 adrs += inc;
1904 }
1905}
1906
1907int
1908bsesc(void)
1909{
1910 int c;
1911
1912 c = inchar();
1913 switch( c ){
1914 case 'n': c = '\n'; break;
1915 case 'r': c = '\r'; break;
1916 case 'b': c = '\b'; break;
1917 case 't': c = '\t'; break;
1918 }
1919 return c;
1920}
1921
1922#define isxdigit(c) (('0' <= (c) && (c) <= '9') \
1923 || ('a' <= (c) && (c) <= 'f') \
1924 || ('A' <= (c) && (c) <= 'F'))
1925void
1926dump(void)
1927{
1928 int c;
1929
1930 c = inchar();
1931 if ((isxdigit(c) && c != 'f' && c != 'd') || c == '\n')
1932 termch = c;
1933 scanhex((void *)&adrs);
1934 if (termch != '\n')
1935 termch = 0;
1936 if (c == 'i') {
1937 scanhex(&nidump);
1938 if (nidump == 0)
1939 nidump = 16;
1940 else if (nidump > MAX_DUMP)
1941 nidump = MAX_DUMP;
1942 adrs += ppc_inst_dump(adrs, nidump, 1);
1943 last_cmd = "di\n";
1944 } else {
1945 scanhex(&ndump);
1946 if (ndump == 0)
1947 ndump = 64;
1948 else if (ndump > MAX_DUMP)
1949 ndump = MAX_DUMP;
1950 prdump(adrs, ndump);
1951 adrs += ndump;
1952 last_cmd = "d\n";
1953 }
1954}
1955
1956void
1957prdump(unsigned long adrs, long ndump)
1958{
1959 long n, m, c, r, nr;
1960 unsigned char temp[16];
1961
1962 for (n = ndump; n > 0;) {
1963 printf("%.16lx", adrs);
1964 putchar(' ');
1965 r = n < 16? n: 16;
1966 nr = mread(adrs, temp, r);
1967 adrs += nr;
1968 for (m = 0; m < r; ++m) {
1969 if ((m & 7) == 0 && m > 0)
1970 putchar(' ');
1971 if (m < nr)
1972 printf("%.2x", temp[m]);
1973 else
1974 printf("%s", fault_chars[fault_type]);
1975 }
1976 if (m <= 8)
1977 printf(" ");
1978 for (; m < 16; ++m)
1979 printf(" ");
1980 printf(" |");
1981 for (m = 0; m < r; ++m) {
1982 if (m < nr) {
1983 c = temp[m];
1984 putchar(' ' <= c && c <= '~'? c: '.');
1985 } else
1986 putchar(' ');
1987 }
1988 n -= r;
1989 for (; m < 16; ++m)
1990 putchar(' ');
1991 printf("|\n");
1992 if (nr < r)
1993 break;
1994 }
1995}
1996
1997int
1998ppc_inst_dump(unsigned long adr, long count, int praddr)
1999{
2000 int nr, dotted;
2001 unsigned long first_adr;
2002 unsigned long inst, last_inst = 0;
2003 unsigned char val[4];
2004
2005 dotted = 0;
2006 for (first_adr = adr; count > 0; --count, adr += 4) {
2007 nr = mread(adr, val, 4);
2008 if (nr == 0) {
2009 if (praddr) {
2010 const char *x = fault_chars[fault_type];
2011 printf("%.16lx %s%s%s%s\n", adr, x, x, x, x);
2012 }
2013 break;
2014 }
2015 inst = GETWORD(val);
2016 if (adr > first_adr && inst == last_inst) {
2017 if (!dotted) {
2018 printf(" ...\n");
2019 dotted = 1;
2020 }
2021 continue;
2022 }
2023 dotted = 0;
2024 last_inst = inst;
2025 if (praddr)
2026 printf("%.16lx %.8x", adr, inst);
2027 printf("\t");
2028 print_insn_powerpc(inst, adr, 0); /* always returns 4 */
2029 printf("\n");
2030 }
2031 return adr - first_adr;
2032}
2033
2034void
2035print_address(unsigned long addr)
2036{
2037 xmon_print_symbol(addr, "\t# ", "");
2038}
2039
2040
2041/*
2042 * Memory operations - move, set, print differences
2043 */
2044static unsigned long mdest; /* destination address */
2045static unsigned long msrc; /* source address */
2046static unsigned long mval; /* byte value to set memory to */
2047static unsigned long mcount; /* # bytes to affect */
2048static unsigned long mdiffs; /* max # differences to print */
2049
2050void
2051memops(int cmd)
2052{
2053 scanhex((void *)&mdest);
2054 if( termch != '\n' )
2055 termch = 0;
2056 scanhex((void *)(cmd == 's'? &mval: &msrc));
2057 if( termch != '\n' )
2058 termch = 0;
2059 scanhex((void *)&mcount);
2060 switch( cmd ){
2061 case 'm':
2062 memmove((void *)mdest, (void *)msrc, mcount);
2063 break;
2064 case 's':
2065 memset((void *)mdest, mval, mcount);
2066 break;
2067 case 'd':
2068 if( termch != '\n' )
2069 termch = 0;
2070 scanhex((void *)&mdiffs);
2071 memdiffs((unsigned char *)mdest, (unsigned char *)msrc, mcount, mdiffs);
2072 break;
2073 }
2074}
2075
2076void
2077memdiffs(unsigned char *p1, unsigned char *p2, unsigned nb, unsigned maxpr)
2078{
2079 unsigned n, prt;
2080
2081 prt = 0;
2082 for( n = nb; n > 0; --n )
2083 if( *p1++ != *p2++ )
2084 if( ++prt <= maxpr )
2085 printf("%.16x %.2x # %.16x %.2x\n", p1 - 1,
2086 p1[-1], p2 - 1, p2[-1]);
2087 if( prt > maxpr )
2088 printf("Total of %d differences\n", prt);
2089}
2090
2091static unsigned mend;
2092static unsigned mask;
2093
2094void
2095memlocate(void)
2096{
2097 unsigned a, n;
2098 unsigned char val[4];
2099
2100 last_cmd = "ml";
2101 scanhex((void *)&mdest);
2102 if (termch != '\n') {
2103 termch = 0;
2104 scanhex((void *)&mend);
2105 if (termch != '\n') {
2106 termch = 0;
2107 scanhex((void *)&mval);
2108 mask = ~0;
2109 if (termch != '\n') termch = 0;
2110 scanhex((void *)&mask);
2111 }
2112 }
2113 n = 0;
2114 for (a = mdest; a < mend; a += 4) {
2115 if (mread(a, val, 4) == 4
2116 && ((GETWORD(val) ^ mval) & mask) == 0) {
2117 printf("%.16x: %.16x\n", a, GETWORD(val));
2118 if (++n >= 10)
2119 break;
2120 }
2121 }
2122}
2123
2124static unsigned long mskip = 0x1000;
2125static unsigned long mlim = 0xffffffff;
2126
2127void
2128memzcan(void)
2129{
2130 unsigned char v;
2131 unsigned a;
2132 int ok, ook;
2133
2134 scanhex(&mdest);
2135 if (termch != '\n') termch = 0;
2136 scanhex(&mskip);
2137 if (termch != '\n') termch = 0;
2138 scanhex(&mlim);
2139 ook = 0;
2140 for (a = mdest; a < mlim; a += mskip) {
2141 ok = mread(a, &v, 1);
2142 if (ok && !ook) {
2143 printf("%.8x .. ", a);
2144 fflush(stdout);
2145 } else if (!ok && ook)
2146 printf("%.8x\n", a - mskip);
2147 ook = ok;
2148 if (a + mskip < a)
2149 break;
2150 }
2151 if (ook)
2152 printf("%.8x\n", a - mskip);
2153}
2154
2155/* Input scanning routines */
2156int
2157skipbl(void)
2158{
2159 int c;
2160
2161 if( termch != 0 ){
2162 c = termch;
2163 termch = 0;
2164 } else
2165 c = inchar();
2166 while( c == ' ' || c == '\t' )
2167 c = inchar();
2168 return c;
2169}
2170
2171#define N_PTREGS 44
2172static char *regnames[N_PTREGS] = {
2173 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2174 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2175 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
2176 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
2177 "pc", "msr", "or3", "ctr", "lr", "xer", "ccr", "softe",
2178 "trap", "dar", "dsisr", "res"
2179};
2180
2181int
2182scanhex(unsigned long *vp)
2183{
2184 int c, d;
2185 unsigned long v;
2186
2187 c = skipbl();
2188 if (c == '%') {
2189 /* parse register name */
2190 char regname[8];
2191 int i;
2192
2193 for (i = 0; i < sizeof(regname) - 1; ++i) {
2194 c = inchar();
2195 if (!isalnum(c)) {
2196 termch = c;
2197 break;
2198 }
2199 regname[i] = c;
2200 }
2201 regname[i] = 0;
2202 for (i = 0; i < N_PTREGS; ++i) {
2203 if (strcmp(regnames[i], regname) == 0) {
2204 if (xmon_regs == NULL) {
2205 printf("regs not available\n");
2206 return 0;
2207 }
2208 *vp = ((unsigned long *)xmon_regs)[i];
2209 return 1;
2210 }
2211 }
2212 printf("invalid register name '%%%s'\n", regname);
2213 return 0;
2214 }
2215
2216 /* skip leading "0x" if any */
2217
2218 if (c == '0') {
2219 c = inchar();
2220 if (c == 'x') {
2221 c = inchar();
2222 } else {
2223 d = hexdigit(c);
2224 if (d == EOF) {
2225 termch = c;
2226 *vp = 0;
2227 return 1;
2228 }
2229 }
2230 } else if (c == '$') {
2231 int i;
2232 for (i=0; i<63; i++) {
2233 c = inchar();
2234 if (isspace(c)) {
2235 termch = c;
2236 break;
2237 }
2238 tmpstr[i] = c;
2239 }
2240 tmpstr[i++] = 0;
2241 *vp = 0;
2242 if (setjmp(bus_error_jmp) == 0) {
2243 catch_memory_errors = 1;
2244 sync();
2245 *vp = kallsyms_lookup_name(tmpstr);
2246 sync();
2247 }
2248 catch_memory_errors = 0;
2249 if (!(*vp)) {
2250 printf("unknown symbol '%s'\n", tmpstr);
2251 return 0;
2252 }
2253 return 1;
2254 }
2255
2256 d = hexdigit(c);
2257 if (d == EOF) {
2258 termch = c;
2259 return 0;
2260 }
2261 v = 0;
2262 do {
2263 v = (v << 4) + d;
2264 c = inchar();
2265 d = hexdigit(c);
2266 } while (d != EOF);
2267 termch = c;
2268 *vp = v;
2269 return 1;
2270}
2271
2272void
2273scannl(void)
2274{
2275 int c;
2276
2277 c = termch;
2278 termch = 0;
2279 while( c != '\n' )
2280 c = inchar();
2281}
2282
2283int
2284hexdigit(int c)
2285{
2286 if( '0' <= c && c <= '9' )
2287 return c - '0';
2288 if( 'A' <= c && c <= 'F' )
2289 return c - ('A' - 10);
2290 if( 'a' <= c && c <= 'f' )
2291 return c - ('a' - 10);
2292 return EOF;
2293}
2294
2295void
2296getstring(char *s, int size)
2297{
2298 int c;
2299
2300 c = skipbl();
2301 do {
2302 if( size > 1 ){
2303 *s++ = c;
2304 --size;
2305 }
2306 c = inchar();
2307 } while( c != ' ' && c != '\t' && c != '\n' );
2308 termch = c;
2309 *s = 0;
2310}
2311
2312static char line[256];
2313static char *lineptr;
2314
2315void
2316flush_input(void)
2317{
2318 lineptr = NULL;
2319}
2320
2321int
2322inchar(void)
2323{
2324 if (lineptr == NULL || *lineptr == 0) {
2325 if (fgets(line, sizeof(line), stdin) == NULL) {
2326 lineptr = NULL;
2327 return EOF;
2328 }
2329 lineptr = line;
2330 }
2331 return *lineptr++;
2332}
2333
2334void
2335take_input(char *str)
2336{
2337 lineptr = str;
2338}
2339
2340
2341static void
2342symbol_lookup(void)
2343{
2344 int type = inchar();
2345 unsigned long addr;
2346 static char tmp[64];
2347
2348 switch (type) {
2349 case 'a':
2350 if (scanhex(&addr))
2351 xmon_print_symbol(addr, ": ", "\n");
2352 termch = 0;
2353 break;
2354 case 's':
2355 getstring(tmp, 64);
2356 if (setjmp(bus_error_jmp) == 0) {
2357 catch_memory_errors = 1;
2358 sync();
2359 addr = kallsyms_lookup_name(tmp);
2360 if (addr)
2361 printf("%s: %lx\n", tmp, addr);
2362 else
2363 printf("Symbol '%s' not found.\n", tmp);
2364 sync();
2365 }
2366 catch_memory_errors = 0;
2367 termch = 0;
2368 break;
2369 }
2370}
2371
2372
2373/* Print an address in numeric and symbolic form (if possible) */
2374static void xmon_print_symbol(unsigned long address, const char *mid,
2375 const char *after)
2376{
2377 char *modname;
2378 const char *name = NULL;
2379 unsigned long offset, size;
2380
2381 printf("%.16lx", address);
2382 if (setjmp(bus_error_jmp) == 0) {
2383 catch_memory_errors = 1;
2384 sync();
2385 name = kallsyms_lookup(address, &size, &offset, &modname,
2386 tmpstr);
2387 sync();
2388 /* wait a little while to see if we get a machine check */
2389 __delay(200);
2390 }
2391
2392 catch_memory_errors = 0;
2393
2394 if (name) {
2395 printf("%s%s+%#lx/%#lx", mid, name, offset, size);
2396 if (modname)
2397 printf(" [%s]", modname);
2398 }
2399 printf("%s", after);
2400}
2401
2402static void debug_trace(void)
2403{
2404 unsigned long val, cmd, on;
2405
2406 cmd = skipbl();
2407 if (cmd == '\n') {
2408 /* show current state */
2409 unsigned long i;
2410 printf("ppc64_debug_switch = 0x%lx\n", ppc64_debug_switch);
2411 for (i = 0; i < PPCDBG_NUM_FLAGS ;i++) {
2412 on = PPCDBG_BITVAL(i) & ppc64_debug_switch;
2413 printf("%02x %s %12s ", i, on ? "on " : "off", trace_names[i] ? trace_names[i] : "");
2414 if (((i+1) % 3) == 0)
2415 printf("\n");
2416 }
2417 printf("\n");
2418 return;
2419 }
2420 while (cmd != '\n') {
2421 on = 1; /* default if no sign given */
2422 while (cmd == '+' || cmd == '-') {
2423 on = (cmd == '+');
2424 cmd = inchar();
2425 if (cmd == ' ' || cmd == '\n') { /* Turn on or off based on + or - */
2426 ppc64_debug_switch = on ? PPCDBG_ALL:PPCDBG_NONE;
2427 printf("Setting all values to %s...\n", on ? "on" : "off");
2428 if (cmd == '\n') return;
2429 else cmd = skipbl();
2430 }
2431 else
2432 termch = cmd;
2433 }
2434 termch = cmd; /* not +/- ... let scanhex see it */
2435 scanhex((void *)&val);
2436 if (val >= 64) {
2437 printf("Value %x out of range:\n", val);
2438 return;
2439 }
2440 if (on) {
2441 ppc64_debug_switch |= PPCDBG_BITVAL(val);
2442 printf("enable debug %x %s\n", val, trace_names[val] ? trace_names[val] : "");
2443 } else {
2444 ppc64_debug_switch &= ~PPCDBG_BITVAL(val);
2445 printf("disable debug %x %s\n", val, trace_names[val] ? trace_names[val] : "");
2446 }
2447 cmd = skipbl();
2448 }
2449}
2450
2451static void dump_slb(void)
2452{
2453 int i;
2454 unsigned long tmp;
2455
2456 printf("SLB contents of cpu %x\n", smp_processor_id());
2457
2458 for (i = 0; i < SLB_NUM_ENTRIES; i++) {
2459 asm volatile("slbmfee %0,%1" : "=r" (tmp) : "r" (i));
2460 printf("%02d %016lx ", i, tmp);
2461
2462 asm volatile("slbmfev %0,%1" : "=r" (tmp) : "r" (i));
2463 printf("%016lx\n", tmp);
2464 }
2465}
2466
2467static void dump_stab(void)
2468{
2469 int i;
2470 unsigned long *tmp = (unsigned long *)get_paca()->stab_addr;
2471
2472 printf("Segment table contents of cpu %x\n", smp_processor_id());
2473
2474 for (i = 0; i < PAGE_SIZE/16; i++) {
2475 unsigned long a, b;
2476
2477 a = *tmp++;
2478 b = *tmp++;
2479
2480 if (a || b) {
2481 printf("%03d %016lx ", i, a);
2482 printf("%016lx\n", b);
2483 }
2484 }
2485}
2486
2487void xmon_init(int enable)
2488{
2489 if (enable) {
2490 __debugger = xmon;
2491 __debugger_ipi = xmon_ipi;
2492 __debugger_bpt = xmon_bpt;
2493 __debugger_sstep = xmon_sstep;
2494 __debugger_iabr_match = xmon_iabr_match;
2495 __debugger_dabr_match = xmon_dabr_match;
2496 __debugger_fault_handler = xmon_fault_handler;
2497 } else {
2498 __debugger = NULL;
2499 __debugger_ipi = NULL;
2500 __debugger_bpt = NULL;
2501 __debugger_sstep = NULL;
2502 __debugger_iabr_match = NULL;
2503 __debugger_dabr_match = NULL;
2504 __debugger_fault_handler = NULL;
2505 }
2506}
2507
2508void dump_segments(void)
2509{
2510 if (cpu_has_feature(CPU_FTR_SLB))
2511 dump_slb();
2512 else
2513 dump_stab();
2514}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 19:23:32 -0500