[PATCH] Invert sense of SLB class bit

Currently, we set the class bit in kernel SLB entries, and clear it on
user SLB entries.  On POWER5, ERAT entries created in real mode have
the class bit clear.  So to avoid flushing kernel ERAT entries on each
context switch, this patch inverts our usage of the class bit, setting
it on user SLB entries and clearing it on kernel SLB entries.

Booted on POWER5 and G5.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/ppc64/mm/slb.c b/arch/ppc64/mm/slb.c
index 244150a0bc18..0473953f6a37 100644
--- a/arch/ppc64/mm/slb.c
+++ b/arch/ppc64/mm/slb.c
@@ -87,8 +87,8 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
                 int i;
                 asm volatile("isync" : : : "memory");
                 for (i = 0; i < offset; i++) {
-                        esid_data = (unsigned long)get_paca()->slb_cache[i]
-                                << SID_SHIFT;
+                        esid_data = ((unsigned long)get_paca()->slb_cache[i]
+                                << SID_SHIFT) | SLBIE_C;
                         asm volatile("slbie %0" : : "r" (esid_data));
                 }
                 asm volatile("isync" : : : "memory");