[PATCH] Invert sense of SLB class bit

Currently, we set the class bit in kernel SLB entries, and clear it on
user SLB entries.  On POWER5, ERAT entries created in real mode have
the class bit clear.  So to avoid flushing kernel ERAT entries on each
context switch, this patch inverts our usage of the class bit, setting
it on user SLB entries and clearing it on kernel SLB entries.

Booted on POWER5 and G5.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 4 insertions, 2 deletions

diff --git a/arch/ppc64/mm/hugetlbpage.c b/arch/ppc64/mm/hugetlbpage.c
index e7833c80eb68..338771ec70d7 100644
--- a/arch/ppc64/mm/hugetlbpage.c
+++ b/arch/ppc64/mm/hugetlbpage.c
@@ -144,7 +144,8 @@ static void flush_low_segments(void *parm)
         for (i = 0; i < NUM_LOW_AREAS; i++) {
                 if (! (areas & (1U << i)))
                         continue;
-                asm volatile("slbie %0" : : "r" (i << SID_SHIFT));
+                asm volatile("slbie %0"
+                             : : "r" ((i << SID_SHIFT) | SLBIE_C));
         }
 
         asm volatile("isync" : : : "memory");
@@ -164,7 +165,8 @@ static void flush_high_segments(void *parm)
                         continue;
                 for (j = 0; j < (1UL << (HTLB_AREA_SHIFT-SID_SHIFT)); j++)
                         asm volatile("slbie %0"
-                                     :: "r" ((i << HTLB_AREA_SHIFT) + (j << SID_SHIFT)));
+                                     :: "r" (((i << HTLB_AREA_SHIFT)
+                                             + (j << SID_SHIFT)) | SLBIE_C));
         }
 
         asm volatile("isync" : : : "memory");