aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ppc64/mm/hash_native.c
diff options
context:
space:
mode:
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2005-09-28 00:45:45 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-28 10:46:42 -0400
commit0f9578b70a9f112bfb541e1d5ab486a376e64503 (patch)
tree00e93df9f9920c43ace34e28298255dc8a0f9263 /arch/ppc64/mm/hash_native.c
parent485ef69edefd7fc7f351c94d0d77b3ed8a242f7b (diff)
[PATCH] ppc64: More hugepage fixes
My previous patch fixing invalidation of huge PTEs wasn't good enough, we still had an issue if a PTE invalidation batch contained both small and large pages. This patch fixes this by making sure the batch is flushed if the page size fed to it changes. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc64/mm/hash_native.c')
-rw-r--r--arch/ppc64/mm/hash_native.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/ppc64/mm/hash_native.c b/arch/ppc64/mm/hash_native.c
index eb1bbb5b6c16..bfd385b7713c 100644
--- a/arch/ppc64/mm/hash_native.c
+++ b/arch/ppc64/mm/hash_native.c
@@ -343,7 +343,7 @@ static void native_flush_hash_range(unsigned long context,
343 hpte_t *hptep; 343 hpte_t *hptep;
344 unsigned long hpte_v; 344 unsigned long hpte_v;
345 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); 345 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
346 unsigned long large; 346 unsigned long large = batch->large;
347 347
348 local_irq_save(flags); 348 local_irq_save(flags);
349 349
@@ -356,7 +356,6 @@ static void native_flush_hash_range(unsigned long context,
356 356
357 va = (vsid << 28) | (batch->addr[i] & 0x0fffffff); 357 va = (vsid << 28) | (batch->addr[i] & 0x0fffffff);
358 batch->vaddr[j] = va; 358 batch->vaddr[j] = va;
359 large = pte_huge(batch->pte[i]);
360 if (large) 359 if (large)
361 vpn = va >> HPAGE_SHIFT; 360 vpn = va >> HPAGE_SHIFT;
362 else 361 else
@@ -406,7 +405,7 @@ static void native_flush_hash_range(unsigned long context,
406 asm volatile("ptesync":::"memory"); 405 asm volatile("ptesync":::"memory");
407 406
408 for (i = 0; i < j; i++) 407 for (i = 0; i < j; i++)
409 __tlbie(batch->vaddr[i], 0); 408 __tlbie(batch->vaddr[i], large);
410 409
411 asm volatile("eieio; tlbsync; ptesync":::"memory"); 410 asm volatile("eieio; tlbsync; ptesync":::"memory");
412 411