[PATCH] ppc64: use c99 initialisers in cputable code

Use c99 initialisers in the cputable code. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
author: Anton Blanchard <anton@samba.org> 2005-07-07 20:56:11 -0400
committer: Linus Torvalds <torvalds@g5.osdl.org> 2005-07-07 21:23:36 -0400
commit: 315a699851722a6bc31e35f91562f31f55d4c4a2 (patch)
tree: 546c54bed0e5c46a63cd0ad89ddea43841409e9a /arch/ppc64/kernel
parent: 2098eec22882e8a50a21eb214df4742b34927dae (diff)
1 files changed, 212 insertions, 153 deletions
diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c
index 1d162c7c59df..c301366176ef 100644
--- a/arch/ppc64/kernel/cputable.c
+++ b/arch/ppc64/kernel/cputable.c
@@ -49,160 +49,219 @@ extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
 #endif
 struct cpu_spec cpu_specs[] = {
-    {   /* Power3 */
+        {       /* Power3 */
-            0xffff0000, 0x00400000, "POWER3 (630)",
+                .pvr_mask               = 0xffff0000,
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                .pvr_value              = 0x00400000,
-                    CPU_FTR_IABR | CPU_FTR_PMC8,
+                .cpu_name               = "POWER3 (630)",
-            COMMON_USER_PPC64,
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-            128, 128,
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
-            __setup_cpu_power3,
+                        CPU_FTR_PMC8,
-            COMMON_PPC64_FW
+                .cpu_user_features = COMMON_USER_PPC64,
-    },
+                .icache_bsize           = 128,
-    {   /* Power3+ */
+                .dcache_bsize           = 128,
-            0xffff0000, 0x00410000, "POWER3 (630+)",
+                .cpu_setup              = __setup_cpu_power3,
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                .firmware_features      = COMMON_PPC64_FW,
-                    CPU_FTR_IABR | CPU_FTR_PMC8,
+        },
-            COMMON_USER_PPC64,
+        {       /* Power3+ */
-            128, 128,
+                .pvr_mask               = 0xffff0000,
-            __setup_cpu_power3,
+                .pvr_value              = 0x00410000,
-            COMMON_PPC64_FW
+                .cpu_name               = "POWER3 (630+)",
-    },
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-    {   /* Northstar */
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
-            0xffff0000, 0x00330000, "RS64-II (northstar)",
+                        CPU_FTR_PMC8,
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                .cpu_user_features      = COMMON_USER_PPC64,
-                    CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                .icache_bsize           = 128,
-            COMMON_USER_PPC64,
+                .dcache_bsize           = 128,
-            128, 128,
+                .cpu_setup              = __setup_cpu_power3,
-            __setup_cpu_power3,
+                .firmware_features      = COMMON_PPC64_FW,
-            COMMON_PPC64_FW
+        },
-    },
+        {       /* Northstar */
-    {   /* Pulsar */
+                .pvr_mask               = 0xffff0000,
-            0xffff0000, 0x00340000, "RS64-III (pulsar)",
+                .pvr_value              = 0x00330000,
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                .cpu_name               = "RS64-II (northstar)",
-                    CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-            COMMON_USER_PPC64,
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
-            128, 128,
+                        CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-            __setup_cpu_power3,
+                .cpu_user_features      = COMMON_USER_PPC64,
-            COMMON_PPC64_FW
+                .icache_bsize           = 128,
-    },
+                .dcache_bsize           = 128,
-    {   /* I-star */
+                .cpu_setup              = __setup_cpu_power3,
-            0xffff0000, 0x00360000, "RS64-III (icestar)",
+                .firmware_features      = COMMON_PPC64_FW,
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+        },
-                    CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+        {       /* Pulsar */
-            COMMON_USER_PPC64,
+                .pvr_mask               = 0xffff0000,
-            128, 128,
+                .pvr_value              = 0x00340000,
-            __setup_cpu_power3,
+                .cpu_name               = "RS64-III (pulsar)",
-            COMMON_PPC64_FW
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-    },
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
-    {   /* S-star */
+                        CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-            0xffff0000, 0x00370000, "RS64-IV (sstar)",
+                .cpu_user_features      = COMMON_USER_PPC64,
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                .icache_bsize           = 128,
-                    CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                .dcache_bsize           = 128,
-            COMMON_USER_PPC64,
+                .cpu_setup              = __setup_cpu_power3,
-            128, 128,
+                .firmware_features      = COMMON_PPC64_FW,
-            __setup_cpu_power3,
+        },
-            COMMON_PPC64_FW
+        {       /* I-star */
-    },
+                .pvr_mask               = 0xffff0000,
-    {   /* Power4 */
+                .pvr_value              = 0x00360000,
-            0xffff0000, 0x00350000, "POWER4 (gp)",
+                .cpu_name               = "RS64-III (icestar)",
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-                    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
-            COMMON_USER_PPC64,
+                        CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-            128, 128,
+                .cpu_user_features      = COMMON_USER_PPC64,
-            __setup_cpu_power4,
+                .icache_bsize           = 128,
-            COMMON_PPC64_FW
+                .dcache_bsize           = 128,
-    },
+                .cpu_setup              = __setup_cpu_power3,
-    {   /* Power4+ */
+                .firmware_features      = COMMON_PPC64_FW,
-            0xffff0000, 0x00380000, "POWER4+ (gq)",
+        },
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+        {       /* S-star */
-                    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                .pvr_mask               = 0xffff0000,
-            COMMON_USER_PPC64,
+                .pvr_value              = 0x00370000,
-            128, 128,
+                .cpu_name               = "RS64-IV (sstar)",
-            __setup_cpu_power4,
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-            COMMON_PPC64_FW
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
-    },
+                        CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-    {   /* PPC970 */
+                .cpu_user_features      = COMMON_USER_PPC64,
-            0xffff0000, 0x00390000, "PPC970",
+                .icache_bsize           = 128,
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                .dcache_bsize           = 128,
-                    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
+                .cpu_setup              = __setup_cpu_power3,
-                    CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                .firmware_features      = COMMON_PPC64_FW,
-            COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
+        },
-            128, 128,
+        {       /* Power4 */
-            __setup_cpu_ppc970,
+                .pvr_mask               = 0xffff0000,
-            COMMON_PPC64_FW
+                .pvr_value              = 0x00350000,
-    },
+                .cpu_name               = "POWER4 (gp)",
-    {   /* PPC970FX */
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-            0xffff0000, 0x003c0000, "PPC970FX",
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                        CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-                    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
+                .cpu_user_features      = COMMON_USER_PPC64,
-                    CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+                .icache_bsize           = 128,
-            COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
+                .dcache_bsize           = 128,
-            128, 128,
+                .cpu_setup              = __setup_cpu_power4,
-            __setup_cpu_ppc970,
+                .firmware_features      = COMMON_PPC64_FW,
-            COMMON_PPC64_FW
+        },
-    },
+        {       /* Power4+ */
-    {   /* Power5 */
+                .pvr_mask               = 0xffff0000,
-            0xffff0000, 0x003a0000, "POWER5 (gr)",
+                .pvr_value              = 0x00380000,
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                .cpu_name               = "POWER4+ (gq)",
-                    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-                    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-                    CPU_FTR_MMCRA_SIHV,
+                        CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-            COMMON_USER_PPC64,
+                .cpu_user_features      = COMMON_USER_PPC64,
-            128, 128,
+                .icache_bsize           = 128,
-            __setup_cpu_power4,
+                .dcache_bsize           = 128,
-            COMMON_PPC64_FW
+                .cpu_setup              = __setup_cpu_power4,
-    },
+                .firmware_features      = COMMON_PPC64_FW,
-    {   /* Power5 */
+        },
-            0xffff0000, 0x003b0000, "POWER5 (gs)",
+        {       /* PPC970 */
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                .pvr_mask               = 0xffff0000,
-                    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
+                .pvr_value              = 0x00390000,
-                    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+                .cpu_name               = "PPC970",
-                    CPU_FTR_MMCRA_SIHV,
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-            COMMON_USER_PPC64,
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-            128, 128,
+                        CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
-            __setup_cpu_power4,
+                        CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-            COMMON_PPC64_FW
+                .cpu_user_features      = COMMON_USER_PPC64 |
-    },
+                        PPC_FEATURE_HAS_ALTIVEC_COMP,
-    {   /* BE DD1.x  */
+                .icache_bsize           = 128,
-            0xffff0000, 0x00700000, "Broadband Engine",
+                .dcache_bsize           = 128,
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                .cpu_setup              = __setup_cpu_ppc970,
-                    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
+                .firmware_features      = COMMON_PPC64_FW,
-                    CPU_FTR_SMT,
+        },
-            COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP,
+        {       /* PPC970FX */
-            128, 128,
+                .pvr_mask               = 0xffff0000,
-            __setup_cpu_be,
+                .pvr_value              = 0x003c0000,
-            COMMON_PPC64_FW
+                .cpu_name               = "PPC970FX",
-    },
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
-    {   /* default match */
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-            0x00000000, 0x00000000, "POWER4 (compatible)",
+                        CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
-            CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                        CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
-                    CPU_FTR_PPCAS_ARCH_V2,
+                .cpu_user_features      = COMMON_USER_PPC64 |
-            COMMON_USER_PPC64,
+                        PPC_FEATURE_HAS_ALTIVEC_COMP,
-            128, 128,
+                .icache_bsize           = 128,
-            __setup_cpu_power4,
+                .dcache_bsize           = 128,
-            COMMON_PPC64_FW
+                .cpu_setup              = __setup_cpu_ppc970,
-    }
+                .firmware_features      = COMMON_PPC64_FW,
+        },
+        {       /* Power5 */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x003a0000,
+                .cpu_name               = "POWER5 (gr)",
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                        CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
+                        CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+                        CPU_FTR_MMCRA_SIHV,
+                .cpu_user_features      = COMMON_USER_PPC64,
+                .icache_bsize           = 128,
+                .dcache_bsize           = 128,
+                .cpu_setup              = __setup_cpu_power4,
+                .firmware_features      = COMMON_PPC64_FW,
+        },
+        {       /* Power5 */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x003b0000,
+                .cpu_name               = "POWER5 (gs)",
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                        CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
+                        CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+                        CPU_FTR_MMCRA_SIHV,
+                .cpu_user_features      = COMMON_USER_PPC64,
+                .icache_bsize           = 128,
+                .dcache_bsize           = 128,
+                .cpu_setup              = __setup_cpu_power4,
+                .firmware_features      = COMMON_PPC64_FW,
+        },
+        {       /* BE DD1.x */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x00700000,
+                .cpu_name               = "Broadband Engine",
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                        CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
+                        CPU_FTR_SMT,
+                .cpu_user_features      = COMMON_USER_PPC64 |
+                        PPC_FEATURE_HAS_ALTIVEC_COMP,
+                .icache_bsize           = 128,
+                .dcache_bsize           = 128,
+                .cpu_setup              = __setup_cpu_be,
+                .firmware_features      = COMMON_PPC64_FW,
+        },
+        {       /* default match */
+                .pvr_mask               = 0x00000000,
+                .pvr_value              = 0x00000000,
+                .cpu_name               = "POWER4 (compatible)",
+                .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                        CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+                        CPU_FTR_PPCAS_ARCH_V2,
+                .cpu_user_features      = COMMON_USER_PPC64,
+                .icache_bsize           = 128,
+                .dcache_bsize           = 128,
+                .cpu_setup              = __setup_cpu_power4,
+                .firmware_features      = COMMON_PPC64_FW,
+        }
 };
 firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {
-    {FW_FEATURE_PFT,            "hcall-pft"},
+        {FW_FEATURE_PFT,                "hcall-pft"},
-    {FW_FEATURE_TCE,            "hcall-tce"},
+        {FW_FEATURE_TCE,                "hcall-tce"},
-    {FW_FEATURE_SPRG0,          "hcall-sprg0"},
+        {FW_FEATURE_SPRG0,              "hcall-sprg0"},
-    {FW_FEATURE_DABR,           "hcall-dabr"},
+        {FW_FEATURE_DABR,               "hcall-dabr"},
-    {FW_FEATURE_COPY,           "hcall-copy"},
+        {FW_FEATURE_COPY,               "hcall-copy"},
-    {FW_FEATURE_ASR,            "hcall-asr"},
+        {FW_FEATURE_ASR,                "hcall-asr"},
-    {FW_FEATURE_DEBUG,          "hcall-debug"},
+        {FW_FEATURE_DEBUG,              "hcall-debug"},
-    {FW_FEATURE_PERF,           "hcall-perf"},
+        {FW_FEATURE_PERF,               "hcall-perf"},
-    {FW_FEATURE_DUMP,           "hcall-dump"},
+        {FW_FEATURE_DUMP,               "hcall-dump"},
-    {FW_FEATURE_INTERRUPT,      "hcall-interrupt"},
+        {FW_FEATURE_INTERRUPT,          "hcall-interrupt"},
-    {FW_FEATURE_MIGRATE,        "hcall-migrate"},
+        {FW_FEATURE_MIGRATE,            "hcall-migrate"},
-    {FW_FEATURE_PERFMON,        "hcall-perfmon"},
+        {FW_FEATURE_PERFMON,            "hcall-perfmon"},
-    {FW_FEATURE_CRQ,            "hcall-crq"},
+        {FW_FEATURE_CRQ,                "hcall-crq"},
-    {FW_FEATURE_VIO,            "hcall-vio"},
+        {FW_FEATURE_VIO,                "hcall-vio"},
-    {FW_FEATURE_RDMA,           "hcall-rdma"},
+        {FW_FEATURE_RDMA,               "hcall-rdma"},
-    {FW_FEATURE_LLAN,           "hcall-lLAN"},
+        {FW_FEATURE_LLAN,               "hcall-lLAN"},
-    {FW_FEATURE_BULK,           "hcall-bulk"},
+        {FW_FEATURE_BULK,               "hcall-bulk"},
-    {FW_FEATURE_XDABR,          "hcall-xdabr"},
+        {FW_FEATURE_XDABR,              "hcall-xdabr"},
-    {FW_FEATURE_MULTITCE,       "hcall-multi-tce"},
+        {FW_FEATURE_MULTITCE,           "hcall-multi-tce"},
-    {FW_FEATURE_SPLPAR,         "hcall-splpar"},
+        {FW_FEATURE_SPLPAR,             "hcall-splpar"},
 };
author	Anton Blanchard <anton@samba.org>	2005-07-07 20:56:11 -0400
committer	Linus Torvalds <torvalds@g5.osdl.org>	2005-07-07 21:23:36 -0400
commit	315a699851722a6bc31e35f91562f31f55d4c4a2 (patch)
tree	546c54bed0e5c46a63cd0ad89ddea43841409e9a /arch/ppc64/kernel
parent	2098eec22882e8a50a21eb214df4742b34927dae (diff)

diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c index 1d162c7c59df..c301366176ef 100644 --- a/arch/ppc64/kernel/cputable.c +++ b/arch/ppc64/kernel/cputable.c
@@ -49,160 +49,219 @@ extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
49	#endif	49	#endif
50		50
51	struct cpu_spec cpu_specs[] = {	51	struct cpu_spec cpu_specs[] = {
52	{ /* Power3 */	52	{ /* Power3 */
53	0xffff0000, 0x00400000, "POWER3 (630)",	53	.pvr_mask = 0xffff0000,
54	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	54	.pvr_value = 0x00400000,
55	CPU_FTR_IABR \| CPU_FTR_PMC8,	55	.cpu_name = "POWER3 (630)",
56	COMMON_USER_PPC64,	56	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
57	128, 128,	57	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|
58	__setup_cpu_power3,	58	CPU_FTR_PMC8,
59	COMMON_PPC64_FW	59	.cpu_user_features = COMMON_USER_PPC64,
60	},	60	.icache_bsize = 128,
61	{ /* Power3+ */	61	.dcache_bsize = 128,
62	0xffff0000, 0x00410000, "POWER3 (630+)",	62	.cpu_setup = __setup_cpu_power3,
63	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	63	.firmware_features = COMMON_PPC64_FW,
64	CPU_FTR_IABR \| CPU_FTR_PMC8,	64	},
65	COMMON_USER_PPC64,	65	{ /* Power3+ */
66	128, 128,	66	.pvr_mask = 0xffff0000,
67	__setup_cpu_power3,	67	.pvr_value = 0x00410000,
68	COMMON_PPC64_FW	68	.cpu_name = "POWER3 (630+)",
69	},	69	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
70	{ /* Northstar */	70	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|
71	0xffff0000, 0x00330000, "RS64-II (northstar)",	71	CPU_FTR_PMC8,
72	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	72	.cpu_user_features = COMMON_USER_PPC64,
73	CPU_FTR_IABR \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,	73	.icache_bsize = 128,
74	COMMON_USER_PPC64,	74	.dcache_bsize = 128,
75	128, 128,	75	.cpu_setup = __setup_cpu_power3,
76	__setup_cpu_power3,	76	.firmware_features = COMMON_PPC64_FW,
77	COMMON_PPC64_FW	77	},
78	},	78	{ /* Northstar */
79	{ /* Pulsar */	79	.pvr_mask = 0xffff0000,
80	0xffff0000, 0x00340000, "RS64-III (pulsar)",	80	.pvr_value = 0x00330000,
81	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	81	.cpu_name = "RS64-II (northstar)",
82	CPU_FTR_IABR \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,	82	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
83	COMMON_USER_PPC64,	83	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|
84	128, 128,	84	CPU_FTR_PMC8 \| CPU_FTR_MMCRA,
85	__setup_cpu_power3,	85	.cpu_user_features = COMMON_USER_PPC64,
86	COMMON_PPC64_FW	86	.icache_bsize = 128,
87	},	87	.dcache_bsize = 128,
88	{ /* I-star */	88	.cpu_setup = __setup_cpu_power3,
89	0xffff0000, 0x00360000, "RS64-III (icestar)",	89	.firmware_features = COMMON_PPC64_FW,
90	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	90	},
91	CPU_FTR_IABR \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,	91	{ /* Pulsar */
92	COMMON_USER_PPC64,	92	.pvr_mask = 0xffff0000,
93	128, 128,	93	.pvr_value = 0x00340000,
94	__setup_cpu_power3,	94	.cpu_name = "RS64-III (pulsar)",
95	COMMON_PPC64_FW	95	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
96	},	96	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|
97	{ /* S-star */	97	CPU_FTR_PMC8 \| CPU_FTR_MMCRA,
98	0xffff0000, 0x00370000, "RS64-IV (sstar)",	98	.cpu_user_features = COMMON_USER_PPC64,
99	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	99	.icache_bsize = 128,
100	CPU_FTR_IABR \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,	100	.dcache_bsize = 128,
101	COMMON_USER_PPC64,	101	.cpu_setup = __setup_cpu_power3,
102	128, 128,	102	.firmware_features = COMMON_PPC64_FW,
103	__setup_cpu_power3,	103	},
104	COMMON_PPC64_FW	104	{ /* I-star */
105	},	105	.pvr_mask = 0xffff0000,
106	{ /* Power4 */	106	.pvr_value = 0x00360000,
107	0xffff0000, 0x00350000, "POWER4 (gp)",	107	.cpu_name = "RS64-III (icestar)",
108	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	108	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
109	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,	109	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|
110	COMMON_USER_PPC64,	110	CPU_FTR_PMC8 \| CPU_FTR_MMCRA,
111	128, 128,	111	.cpu_user_features = COMMON_USER_PPC64,
112	__setup_cpu_power4,	112	.icache_bsize = 128,
113	COMMON_PPC64_FW	113	.dcache_bsize = 128,
114	},	114	.cpu_setup = __setup_cpu_power3,
115	{ /* Power4+ */	115	.firmware_features = COMMON_PPC64_FW,
116	0xffff0000, 0x00380000, "POWER4+ (gq)",	116	},
117	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	117	{ /* S-star */
118	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,	118	.pvr_mask = 0xffff0000,
119	COMMON_USER_PPC64,	119	.pvr_value = 0x00370000,
120	128, 128,	120	.cpu_name = "RS64-IV (sstar)",
121	__setup_cpu_power4,	121	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
122	COMMON_PPC64_FW	122	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \|
123	},	123	CPU_FTR_PMC8 \| CPU_FTR_MMCRA,
124	{ /* PPC970 */	124	.cpu_user_features = COMMON_USER_PPC64,
125	0xffff0000, 0x00390000, "PPC970",	125	.icache_bsize = 128,
126	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	126	.dcache_bsize = 128,
127	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|	127	.cpu_setup = __setup_cpu_power3,
128	CPU_FTR_CAN_NAP \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,	128	.firmware_features = COMMON_PPC64_FW,
129	COMMON_USER_PPC64 \| PPC_FEATURE_HAS_ALTIVEC_COMP,	129	},
130	128, 128,	130	{ /* Power4 */
131	__setup_cpu_ppc970,	131	.pvr_mask = 0xffff0000,
132	COMMON_PPC64_FW	132	.pvr_value = 0x00350000,
133	},	133	.cpu_name = "POWER4 (gp)",
134	{ /* PPC970FX */	134	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
135	0xffff0000, 0x003c0000, "PPC970FX",	135	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
136	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	136	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,
137	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|	137	.cpu_user_features = COMMON_USER_PPC64,
138	CPU_FTR_CAN_NAP \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,	138	.icache_bsize = 128,
139	COMMON_USER_PPC64 \| PPC_FEATURE_HAS_ALTIVEC_COMP,	139	.dcache_bsize = 128,
140	128, 128,	140	.cpu_setup = __setup_cpu_power4,
141	__setup_cpu_ppc970,	141	.firmware_features = COMMON_PPC64_FW,
142	COMMON_PPC64_FW	142	},
143	},	143	{ /* Power4+ */
144	{ /* Power5 */	144	.pvr_mask = 0xffff0000,
145	0xffff0000, 0x003a0000, "POWER5 (gr)",	145	.pvr_value = 0x00380000,
146	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	146	.cpu_name = "POWER4+ (gq)",
147	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_MMCRA \| CPU_FTR_SMT \|	147	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
148	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \|	148	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
149	CPU_FTR_MMCRA_SIHV,	149	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,
150	COMMON_USER_PPC64,	150	.cpu_user_features = COMMON_USER_PPC64,
151	128, 128,	151	.icache_bsize = 128,
152	__setup_cpu_power4,	152	.dcache_bsize = 128,
153	COMMON_PPC64_FW	153	.cpu_setup = __setup_cpu_power4,
154	},	154	.firmware_features = COMMON_PPC64_FW,
155	{ /* Power5 */	155	},
156	0xffff0000, 0x003b0000, "POWER5 (gs)",	156	{ /* PPC970 */
157	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	157	.pvr_mask = 0xffff0000,
158	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_MMCRA \| CPU_FTR_SMT \|	158	.pvr_value = 0x00390000,
159	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \|	159	.cpu_name = "PPC970",
160	CPU_FTR_MMCRA_SIHV,	160	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
161	COMMON_USER_PPC64,	161	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
162	128, 128,	162	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|
163	__setup_cpu_power4,	163	CPU_FTR_CAN_NAP \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,
164	COMMON_PPC64_FW	164	.cpu_user_features = COMMON_USER_PPC64 \|
165	},	165	PPC_FEATURE_HAS_ALTIVEC_COMP,
166	{ /* BE DD1.x */	166	.icache_bsize = 128,
167	0xffff0000, 0x00700000, "Broadband Engine",	167	.dcache_bsize = 128,
168	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	168	.cpu_setup = __setup_cpu_ppc970,
169	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|	169	.firmware_features = COMMON_PPC64_FW,
170	CPU_FTR_SMT,	170	},
171	COMMON_USER_PPC64 \| PPC_FEATURE_HAS_ALTIVEC_COMP,	171	{ /* PPC970FX */
172	128, 128,	172	.pvr_mask = 0xffff0000,
173	__setup_cpu_be,	173	.pvr_value = 0x003c0000,
174	COMMON_PPC64_FW	174	.cpu_name = "PPC970FX",
175	},	175	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
176	{ /* default match */	176	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
177	0x00000000, 0x00000000, "POWER4 (compatible)",	177	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|
178	CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|	178	CPU_FTR_CAN_NAP \| CPU_FTR_PMC8 \| CPU_FTR_MMCRA,
179	CPU_FTR_PPCAS_ARCH_V2,	179	.cpu_user_features = COMMON_USER_PPC64 \|
180	COMMON_USER_PPC64,	180	PPC_FEATURE_HAS_ALTIVEC_COMP,
181	128, 128,	181	.icache_bsize = 128,
182	__setup_cpu_power4,	182	.dcache_bsize = 128,
183	COMMON_PPC64_FW	183	.cpu_setup = __setup_cpu_ppc970,
184	}	184	.firmware_features = COMMON_PPC64_FW,
		185	},
		186	{ /* Power5 */
		187	.pvr_mask = 0xffff0000,
		188	.pvr_value = 0x003a0000,
		189	.cpu_name = "POWER5 (gr)",
		190	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
		191	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
		192	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_MMCRA \| CPU_FTR_SMT \|
		193	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \|
		194	CPU_FTR_MMCRA_SIHV,
		195	.cpu_user_features = COMMON_USER_PPC64,
		196	.icache_bsize = 128,
		197	.dcache_bsize = 128,
		198	.cpu_setup = __setup_cpu_power4,
		199	.firmware_features = COMMON_PPC64_FW,
		200	},
		201	{ /* Power5 */
		202	.pvr_mask = 0xffff0000,
		203	.pvr_value = 0x003b0000,
		204	.cpu_name = "POWER5 (gs)",
		205	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
		206	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
		207	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_MMCRA \| CPU_FTR_SMT \|
		208	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \|
		209	CPU_FTR_MMCRA_SIHV,
		210	.cpu_user_features = COMMON_USER_PPC64,
		211	.icache_bsize = 128,
		212	.dcache_bsize = 128,
		213	.cpu_setup = __setup_cpu_power4,
		214	.firmware_features = COMMON_PPC64_FW,
		215	},
		216	{ /* BE DD1.x */
		217	.pvr_mask = 0xffff0000,
		218	.pvr_value = 0x00700000,
		219	.cpu_name = "Broadband Engine",
		220	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
		221	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
		222	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \|
		223	CPU_FTR_SMT,
		224	.cpu_user_features = COMMON_USER_PPC64 \|
		225	PPC_FEATURE_HAS_ALTIVEC_COMP,
		226	.icache_bsize = 128,
		227	.dcache_bsize = 128,
		228	.cpu_setup = __setup_cpu_be,
		229	.firmware_features = COMMON_PPC64_FW,
		230	},
		231	{ /* default match */
		232	.pvr_mask = 0x00000000,
		233	.pvr_value = 0x00000000,
		234	.cpu_name = "POWER4 (compatible)",
		235	.cpu_features = CPU_FTR_SPLIT_ID_CACHE \|
		236	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \|
		237	CPU_FTR_PPCAS_ARCH_V2,
		238	.cpu_user_features = COMMON_USER_PPC64,
		239	.icache_bsize = 128,
		240	.dcache_bsize = 128,
		241	.cpu_setup = __setup_cpu_power4,
		242	.firmware_features = COMMON_PPC64_FW,
		243	}
185	};	244	};
186		245
187	firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {	246	firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {
188	{FW_FEATURE_PFT, "hcall-pft"},	247	{FW_FEATURE_PFT, "hcall-pft"},
189	{FW_FEATURE_TCE, "hcall-tce"},	248	{FW_FEATURE_TCE, "hcall-tce"},
190	{FW_FEATURE_SPRG0, "hcall-sprg0"},	249	{FW_FEATURE_SPRG0, "hcall-sprg0"},
191	{FW_FEATURE_DABR, "hcall-dabr"},	250	{FW_FEATURE_DABR, "hcall-dabr"},
192	{FW_FEATURE_COPY, "hcall-copy"},	251	{FW_FEATURE_COPY, "hcall-copy"},
193	{FW_FEATURE_ASR, "hcall-asr"},	252	{FW_FEATURE_ASR, "hcall-asr"},
194	{FW_FEATURE_DEBUG, "hcall-debug"},	253	{FW_FEATURE_DEBUG, "hcall-debug"},
195	{FW_FEATURE_PERF, "hcall-perf"},	254	{FW_FEATURE_PERF, "hcall-perf"},
196	{FW_FEATURE_DUMP, "hcall-dump"},	255	{FW_FEATURE_DUMP, "hcall-dump"},
197	{FW_FEATURE_INTERRUPT, "hcall-interrupt"},	256	{FW_FEATURE_INTERRUPT, "hcall-interrupt"},
198	{FW_FEATURE_MIGRATE, "hcall-migrate"},	257	{FW_FEATURE_MIGRATE, "hcall-migrate"},
199	{FW_FEATURE_PERFMON, "hcall-perfmon"},	258	{FW_FEATURE_PERFMON, "hcall-perfmon"},
200	{FW_FEATURE_CRQ, "hcall-crq"},	259	{FW_FEATURE_CRQ, "hcall-crq"},
201	{FW_FEATURE_VIO, "hcall-vio"},	260	{FW_FEATURE_VIO, "hcall-vio"},
202	{FW_FEATURE_RDMA, "hcall-rdma"},	261	{FW_FEATURE_RDMA, "hcall-rdma"},
203	{FW_FEATURE_LLAN, "hcall-lLAN"},	262	{FW_FEATURE_LLAN, "hcall-lLAN"},
204	{FW_FEATURE_BULK, "hcall-bulk"},	263	{FW_FEATURE_BULK, "hcall-bulk"},
205	{FW_FEATURE_XDABR, "hcall-xdabr"},	264	{FW_FEATURE_XDABR, "hcall-xdabr"},
206	{FW_FEATURE_MULTITCE, "hcall-multi-tce"},	265	{FW_FEATURE_MULTITCE, "hcall-multi-tce"},
207	{FW_FEATURE_SPLPAR, "hcall-splpar"},	266	{FW_FEATURE_SPLPAR, "hcall-splpar"},
208	};	267	};