aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ppc64/kernel/pSeries_iommu.c
diff options
context:
space:
mode:
authorPaul Mackerras <paulus@samba.org>2005-10-10 08:03:41 -0400
committerPaul Mackerras <paulus@samba.org>2005-10-10 08:03:41 -0400
commit69a80d3f69d0b2d7fae5a73c6e034d402d434d8a (patch)
treedd66f34510eae791a04c8dd77ce77a223b2f46d6 /arch/ppc64/kernel/pSeries_iommu.c
parentab1f9dac6eea25ee59e4c8e1cf0b7476afbbfe07 (diff)
powerpc: move pSeries files to arch/powerpc/platforms/pseries
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc64/kernel/pSeries_iommu.c')
-rw-r--r--arch/ppc64/kernel/pSeries_iommu.c606
1 files changed, 0 insertions, 606 deletions
diff --git a/arch/ppc64/kernel/pSeries_iommu.c b/arch/ppc64/kernel/pSeries_iommu.c
deleted file mode 100644
index 9e90d41131d8..000000000000
--- a/arch/ppc64/kernel/pSeries_iommu.c
+++ /dev/null
@@ -1,606 +0,0 @@
1/*
2 * arch/ppc64/kernel/pSeries_iommu.c
3 *
4 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
5 *
6 * Rewrite, cleanup:
7 *
8 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
9 *
10 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
11 *
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/config.h>
29#include <linux/init.h>
30#include <linux/types.h>
31#include <linux/slab.h>
32#include <linux/mm.h>
33#include <linux/spinlock.h>
34#include <linux/string.h>
35#include <linux/pci.h>
36#include <linux/dma-mapping.h>
37#include <asm/io.h>
38#include <asm/prom.h>
39#include <asm/rtas.h>
40#include <asm/ppcdebug.h>
41#include <asm/iommu.h>
42#include <asm/pci-bridge.h>
43#include <asm/machdep.h>
44#include <asm/abs_addr.h>
45#include <asm/plpar_wrappers.h>
46#include <asm/pSeries_reconfig.h>
47#include <asm/systemcfg.h>
48#include <asm/firmware.h>
49#include <asm/tce.h>
50#include <asm/ppc-pci.h>
51
52#define DBG(fmt...)
53
54extern int is_python(struct device_node *);
55
56static void tce_build_pSeries(struct iommu_table *tbl, long index,
57 long npages, unsigned long uaddr,
58 enum dma_data_direction direction)
59{
60 union tce_entry t;
61 union tce_entry *tp;
62
63 index <<= TCE_PAGE_FACTOR;
64 npages <<= TCE_PAGE_FACTOR;
65
66 t.te_word = 0;
67 t.te_rdwr = 1; // Read allowed
68
69 if (direction != DMA_TO_DEVICE)
70 t.te_pciwr = 1;
71
72 tp = ((union tce_entry *)tbl->it_base) + index;
73
74 while (npages--) {
75 /* can't move this out since we might cross LMB boundary */
76 t.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
77
78 tp->te_word = t.te_word;
79
80 uaddr += TCE_PAGE_SIZE;
81 tp++;
82 }
83}
84
85
86static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
87{
88 union tce_entry t;
89 union tce_entry *tp;
90
91 npages <<= TCE_PAGE_FACTOR;
92 index <<= TCE_PAGE_FACTOR;
93
94 t.te_word = 0;
95 tp = ((union tce_entry *)tbl->it_base) + index;
96
97 while (npages--) {
98 tp->te_word = t.te_word;
99
100 tp++;
101 }
102}
103
104
105static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
106 long npages, unsigned long uaddr,
107 enum dma_data_direction direction)
108{
109 u64 rc;
110 union tce_entry tce;
111
112 tce.te_word = 0;
113 tce.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
114 tce.te_rdwr = 1;
115 if (direction != DMA_TO_DEVICE)
116 tce.te_pciwr = 1;
117
118 while (npages--) {
119 rc = plpar_tce_put((u64)tbl->it_index,
120 (u64)tcenum << 12,
121 tce.te_word );
122
123 if (rc && printk_ratelimit()) {
124 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
125 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
126 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
127 printk("\ttce val = 0x%lx\n", tce.te_word );
128 show_stack(current, (unsigned long *)__get_SP());
129 }
130
131 tcenum++;
132 tce.te_rpn++;
133 }
134}
135
136static DEFINE_PER_CPU(void *, tce_page) = NULL;
137
138static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
139 long npages, unsigned long uaddr,
140 enum dma_data_direction direction)
141{
142 u64 rc;
143 union tce_entry tce, *tcep;
144 long l, limit;
145
146 tcenum <<= TCE_PAGE_FACTOR;
147 npages <<= TCE_PAGE_FACTOR;
148
149 if (npages == 1)
150 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
151 direction);
152
153 tcep = __get_cpu_var(tce_page);
154
155 /* This is safe to do since interrupts are off when we're called
156 * from iommu_alloc{,_sg}()
157 */
158 if (!tcep) {
159 tcep = (void *)__get_free_page(GFP_ATOMIC);
160 /* If allocation fails, fall back to the loop implementation */
161 if (!tcep)
162 return tce_build_pSeriesLP(tbl, tcenum, npages,
163 uaddr, direction);
164 __get_cpu_var(tce_page) = tcep;
165 }
166
167 tce.te_word = 0;
168 tce.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
169 tce.te_rdwr = 1;
170 if (direction != DMA_TO_DEVICE)
171 tce.te_pciwr = 1;
172
173 /* We can map max one pageful of TCEs at a time */
174 do {
175 /*
176 * Set up the page with TCE data, looping through and setting
177 * the values.
178 */
179 limit = min_t(long, npages, 4096/sizeof(union tce_entry));
180
181 for (l = 0; l < limit; l++) {
182 tcep[l] = tce;
183 tce.te_rpn++;
184 }
185
186 rc = plpar_tce_put_indirect((u64)tbl->it_index,
187 (u64)tcenum << 12,
188 (u64)virt_to_abs(tcep),
189 limit);
190
191 npages -= limit;
192 tcenum += limit;
193 } while (npages > 0 && !rc);
194
195 if (rc && printk_ratelimit()) {
196 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
197 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
198 printk("\tnpages = 0x%lx\n", (u64)npages);
199 printk("\ttce[0] val = 0x%lx\n", tcep[0].te_word);
200 show_stack(current, (unsigned long *)__get_SP());
201 }
202}
203
204static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
205{
206 u64 rc;
207 union tce_entry tce;
208
209 tcenum <<= TCE_PAGE_FACTOR;
210 npages <<= TCE_PAGE_FACTOR;
211
212 tce.te_word = 0;
213
214 while (npages--) {
215 rc = plpar_tce_put((u64)tbl->it_index,
216 (u64)tcenum << 12,
217 tce.te_word);
218
219 if (rc && printk_ratelimit()) {
220 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
221 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
222 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
223 printk("\ttce val = 0x%lx\n", tce.te_word );
224 show_stack(current, (unsigned long *)__get_SP());
225 }
226
227 tcenum++;
228 }
229}
230
231
232static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
233{
234 u64 rc;
235 union tce_entry tce;
236
237 tcenum <<= TCE_PAGE_FACTOR;
238 npages <<= TCE_PAGE_FACTOR;
239
240 tce.te_word = 0;
241
242 rc = plpar_tce_stuff((u64)tbl->it_index,
243 (u64)tcenum << 12,
244 tce.te_word,
245 npages);
246
247 if (rc && printk_ratelimit()) {
248 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
249 printk("\trc = %ld\n", rc);
250 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
251 printk("\tnpages = 0x%lx\n", (u64)npages);
252 printk("\ttce val = 0x%lx\n", tce.te_word );
253 show_stack(current, (unsigned long *)__get_SP());
254 }
255}
256
257static void iommu_table_setparms(struct pci_controller *phb,
258 struct device_node *dn,
259 struct iommu_table *tbl)
260{
261 struct device_node *node;
262 unsigned long *basep;
263 unsigned int *sizep;
264
265 node = (struct device_node *)phb->arch_data;
266
267 basep = (unsigned long *)get_property(node, "linux,tce-base", NULL);
268 sizep = (unsigned int *)get_property(node, "linux,tce-size", NULL);
269 if (basep == NULL || sizep == NULL) {
270 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
271 "missing tce entries !\n", dn->full_name);
272 return;
273 }
274
275 tbl->it_base = (unsigned long)__va(*basep);
276 memset((void *)tbl->it_base, 0, *sizep);
277
278 tbl->it_busno = phb->bus->number;
279
280 /* Units of tce entries */
281 tbl->it_offset = phb->dma_window_base_cur >> PAGE_SHIFT;
282
283 /* Test if we are going over 2GB of DMA space */
284 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
285 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
286 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
287 }
288
289 phb->dma_window_base_cur += phb->dma_window_size;
290
291 /* Set the tce table size - measured in entries */
292 tbl->it_size = phb->dma_window_size >> PAGE_SHIFT;
293
294 tbl->it_index = 0;
295 tbl->it_blocksize = 16;
296 tbl->it_type = TCE_PCI;
297}
298
299/*
300 * iommu_table_setparms_lpar
301 *
302 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
303 *
304 * ToDo: properly interpret the ibm,dma-window property. The definition is:
305 * logical-bus-number (1 word)
306 * phys-address (#address-cells words)
307 * size (#cell-size words)
308 *
309 * Currently we hard code these sizes (more or less).
310 */
311static void iommu_table_setparms_lpar(struct pci_controller *phb,
312 struct device_node *dn,
313 struct iommu_table *tbl,
314 unsigned int *dma_window)
315{
316 tbl->it_busno = PCI_DN(dn)->bussubno;
317
318 /* TODO: Parse field size properties properly. */
319 tbl->it_size = (((unsigned long)dma_window[4] << 32) |
320 (unsigned long)dma_window[5]) >> PAGE_SHIFT;
321 tbl->it_offset = (((unsigned long)dma_window[2] << 32) |
322 (unsigned long)dma_window[3]) >> PAGE_SHIFT;
323 tbl->it_base = 0;
324 tbl->it_index = dma_window[0];
325 tbl->it_blocksize = 16;
326 tbl->it_type = TCE_PCI;
327}
328
329static void iommu_bus_setup_pSeries(struct pci_bus *bus)
330{
331 struct device_node *dn;
332 struct iommu_table *tbl;
333 struct device_node *isa_dn, *isa_dn_orig;
334 struct device_node *tmp;
335 struct pci_dn *pci;
336 int children;
337
338 DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self);
339
340 dn = pci_bus_to_OF_node(bus);
341 pci = PCI_DN(dn);
342
343 if (bus->self) {
344 /* This is not a root bus, any setup will be done for the
345 * device-side of the bridge in iommu_dev_setup_pSeries().
346 */
347 return;
348 }
349
350 /* Check if the ISA bus on the system is under
351 * this PHB.
352 */
353 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
354
355 while (isa_dn && isa_dn != dn)
356 isa_dn = isa_dn->parent;
357
358 if (isa_dn_orig)
359 of_node_put(isa_dn_orig);
360
361 /* Count number of direct PCI children of the PHB.
362 * All PCI device nodes have class-code property, so it's
363 * an easy way to find them.
364 */
365 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
366 if (get_property(tmp, "class-code", NULL))
367 children++;
368
369 DBG("Children: %d\n", children);
370
371 /* Calculate amount of DMA window per slot. Each window must be
372 * a power of two (due to pci_alloc_consistent requirements).
373 *
374 * Keep 256MB aside for PHBs with ISA.
375 */
376
377 if (!isa_dn) {
378 /* No ISA/IDE - just set window size and return */
379 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
380
381 while (pci->phb->dma_window_size * children > 0x80000000ul)
382 pci->phb->dma_window_size >>= 1;
383 DBG("No ISA/IDE, window size is 0x%lx\n",
384 pci->phb->dma_window_size);
385 pci->phb->dma_window_base_cur = 0;
386
387 return;
388 }
389
390 /* If we have ISA, then we probably have an IDE
391 * controller too. Allocate a 128MB table but
392 * skip the first 128MB to avoid stepping on ISA
393 * space.
394 */
395 pci->phb->dma_window_size = 0x8000000ul;
396 pci->phb->dma_window_base_cur = 0x8000000ul;
397
398 tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
399
400 iommu_table_setparms(pci->phb, dn, tbl);
401 pci->iommu_table = iommu_init_table(tbl);
402
403 /* Divide the rest (1.75GB) among the children */
404 pci->phb->dma_window_size = 0x80000000ul;
405 while (pci->phb->dma_window_size * children > 0x70000000ul)
406 pci->phb->dma_window_size >>= 1;
407
408 DBG("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size);
409
410}
411
412
413static void iommu_bus_setup_pSeriesLP(struct pci_bus *bus)
414{
415 struct iommu_table *tbl;
416 struct device_node *dn, *pdn;
417 struct pci_dn *ppci;
418 unsigned int *dma_window = NULL;
419
420 DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus, bus->self);
421
422 dn = pci_bus_to_OF_node(bus);
423
424 /* Find nearest ibm,dma-window, walking up the device tree */
425 for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
426 dma_window = (unsigned int *)get_property(pdn, "ibm,dma-window", NULL);
427 if (dma_window != NULL)
428 break;
429 }
430
431 if (dma_window == NULL) {
432 DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn->full_name);
433 return;
434 }
435
436 ppci = pdn->data;
437 if (!ppci->iommu_table) {
438 /* Bussubno hasn't been copied yet.
439 * Do it now because iommu_table_setparms_lpar needs it.
440 */
441
442 ppci->bussubno = bus->number;
443
444 tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
445 GFP_KERNEL);
446
447 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
448
449 ppci->iommu_table = iommu_init_table(tbl);
450 }
451
452 if (pdn != dn)
453 PCI_DN(dn)->iommu_table = ppci->iommu_table;
454}
455
456
457static void iommu_dev_setup_pSeries(struct pci_dev *dev)
458{
459 struct device_node *dn, *mydn;
460 struct iommu_table *tbl;
461
462 DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev, pci_name(dev));
463
464 mydn = dn = pci_device_to_OF_node(dev);
465
466 /* If we're the direct child of a root bus, then we need to allocate
467 * an iommu table ourselves. The bus setup code should have setup
468 * the window sizes already.
469 */
470 if (!dev->bus->self) {
471 DBG(" --> first child, no bridge. Allocating iommu table.\n");
472 tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);
473 iommu_table_setparms(PCI_DN(dn)->phb, dn, tbl);
474 PCI_DN(mydn)->iommu_table = iommu_init_table(tbl);
475
476 return;
477 }
478
479 /* If this device is further down the bus tree, search upwards until
480 * an already allocated iommu table is found and use that.
481 */
482
483 while (dn && dn->data && PCI_DN(dn)->iommu_table == NULL)
484 dn = dn->parent;
485
486 if (dn && dn->data) {
487 PCI_DN(mydn)->iommu_table = PCI_DN(dn)->iommu_table;
488 } else {
489 DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev, pci_name(dev));
490 }
491}
492
493static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
494{
495 int err = NOTIFY_OK;
496 struct device_node *np = node;
497 struct pci_dn *pci = np->data;
498
499 switch (action) {
500 case PSERIES_RECONFIG_REMOVE:
501 if (pci->iommu_table &&
502 get_property(np, "ibm,dma-window", NULL))
503 iommu_free_table(np);
504 break;
505 default:
506 err = NOTIFY_DONE;
507 break;
508 }
509 return err;
510}
511
512static struct notifier_block iommu_reconfig_nb = {
513 .notifier_call = iommu_reconfig_notifier,
514};
515
516static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev)
517{
518 struct device_node *pdn, *dn;
519 struct iommu_table *tbl;
520 int *dma_window = NULL;
521 struct pci_dn *pci;
522
523 DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev, pci_name(dev));
524
525 /* dev setup for LPAR is a little tricky, since the device tree might
526 * contain the dma-window properties per-device and not neccesarily
527 * for the bus. So we need to search upwards in the tree until we
528 * either hit a dma-window property, OR find a parent with a table
529 * already allocated.
530 */
531 dn = pci_device_to_OF_node(dev);
532
533 for (pdn = dn; pdn && pdn->data && !PCI_DN(pdn)->iommu_table;
534 pdn = pdn->parent) {
535 dma_window = (unsigned int *)
536 get_property(pdn, "ibm,dma-window", NULL);
537 if (dma_window)
538 break;
539 }
540
541 /* Check for parent == NULL so we don't try to setup the empty EADS
542 * slots on POWER4 machines.
543 */
544 if (dma_window == NULL || pdn->parent == NULL) {
545 DBG("No dma window for device, linking to parent\n");
546 PCI_DN(dn)->iommu_table = PCI_DN(pdn)->iommu_table;
547 return;
548 } else {
549 DBG("Found DMA window, allocating table\n");
550 }
551
552 pci = pdn->data;
553 if (!pci->iommu_table) {
554 /* iommu_table_setparms_lpar needs bussubno. */
555 pci->bussubno = pci->phb->bus->number;
556
557 tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table),
558 GFP_KERNEL);
559
560 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
561
562 pci->iommu_table = iommu_init_table(tbl);
563 }
564
565 if (pdn != dn)
566 PCI_DN(dn)->iommu_table = pci->iommu_table;
567}
568
569static void iommu_bus_setup_null(struct pci_bus *b) { }
570static void iommu_dev_setup_null(struct pci_dev *d) { }
571
572/* These are called very early. */
573void iommu_init_early_pSeries(void)
574{
575 if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) {
576 /* Direct I/O, IOMMU off */
577 ppc_md.iommu_dev_setup = iommu_dev_setup_null;
578 ppc_md.iommu_bus_setup = iommu_bus_setup_null;
579 pci_direct_iommu_init();
580
581 return;
582 }
583
584 if (systemcfg->platform & PLATFORM_LPAR) {
585 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
586 ppc_md.tce_build = tce_buildmulti_pSeriesLP;
587 ppc_md.tce_free = tce_freemulti_pSeriesLP;
588 } else {
589 ppc_md.tce_build = tce_build_pSeriesLP;
590 ppc_md.tce_free = tce_free_pSeriesLP;
591 }
592 ppc_md.iommu_bus_setup = iommu_bus_setup_pSeriesLP;
593 ppc_md.iommu_dev_setup = iommu_dev_setup_pSeriesLP;
594 } else {
595 ppc_md.tce_build = tce_build_pSeries;
596 ppc_md.tce_free = tce_free_pSeries;
597 ppc_md.iommu_bus_setup = iommu_bus_setup_pSeries;
598 ppc_md.iommu_dev_setup = iommu_dev_setup_pSeries;
599 }
600
601
602 pSeries_reconfig_notifier_register(&iommu_reconfig_nb);
603
604 pci_iommu_init();
605}
606
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 10:00:40 -0500