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authorKumar Gala <galak@freescale.com>2005-09-23 15:08:58 -0400
committerPaul Mackerras <paulus@samba.org>2005-09-28 01:42:53 -0400
commit10b35d9978ac35556aec0d2642055742d8941488 (patch)
tree7c59c62e2840d7d9971076e1acccaa0cadd678b8 /arch/ppc64/kernel/cputable.c
parenta559c91d77c3220be521453bd23815e1e1980a82 (diff)
[PATCH] powerpc: merged asm/cputable.h
Merged cputable.h between ppc32 and ppc64. In doing this removed support for the BEGIN_FTR_SECTION/END_FTR_SECTION macros in C code since they dont compile correctly. C code should use cpu_has_feature(). This is based on Arnd Bergmann's initial patch. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc64/kernel/cputable.c')
-rw-r--r--arch/ppc64/kernel/cputable.c82
1 files changed, 17 insertions, 65 deletions
diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c
index 8831a28c3c4e..5134c53d536d 100644
--- a/arch/ppc64/kernel/cputable.c
+++ b/arch/ppc64/kernel/cputable.c
@@ -37,26 +37,13 @@ extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
37extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec); 37extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
38extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec); 38extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
39 39
40
41/* We only set the altivec features if the kernel was compiled with altivec
42 * support
43 */
44#ifdef CONFIG_ALTIVEC
45#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
46#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
47#else
48#define CPU_FTR_ALTIVEC_COMP 0
49#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
50#endif
51
52struct cpu_spec cpu_specs[] = { 40struct cpu_spec cpu_specs[] = {
53 { /* Power3 */ 41 { /* Power3 */
54 .pvr_mask = 0xffff0000, 42 .pvr_mask = 0xffff0000,
55 .pvr_value = 0x00400000, 43 .pvr_value = 0x00400000,
56 .cpu_name = "POWER3 (630)", 44 .cpu_name = "POWER3 (630)",
57 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 45 .cpu_features = CPU_FTRS_POWER3,
58 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR, 46 .cpu_user_features = COMMON_USER_PPC64,
59 .cpu_user_features = COMMON_USER_PPC64,
60 .icache_bsize = 128, 47 .icache_bsize = 128,
61 .dcache_bsize = 128, 48 .dcache_bsize = 128,
62 .num_pmcs = 8, 49 .num_pmcs = 8,
@@ -70,8 +57,7 @@ struct cpu_spec cpu_specs[] = {
70 .pvr_mask = 0xffff0000, 57 .pvr_mask = 0xffff0000,
71 .pvr_value = 0x00410000, 58 .pvr_value = 0x00410000,
72 .cpu_name = "POWER3 (630+)", 59 .cpu_name = "POWER3 (630+)",
73 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 60 .cpu_features = CPU_FTRS_POWER3,
74 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
75 .cpu_user_features = COMMON_USER_PPC64, 61 .cpu_user_features = COMMON_USER_PPC64,
76 .icache_bsize = 128, 62 .icache_bsize = 128,
77 .dcache_bsize = 128, 63 .dcache_bsize = 128,
@@ -86,9 +72,7 @@ struct cpu_spec cpu_specs[] = {
86 .pvr_mask = 0xffff0000, 72 .pvr_mask = 0xffff0000,
87 .pvr_value = 0x00330000, 73 .pvr_value = 0x00330000,
88 .cpu_name = "RS64-II (northstar)", 74 .cpu_name = "RS64-II (northstar)",
89 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 75 .cpu_features = CPU_FTRS_RS64,
90 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
91 CPU_FTR_MMCRA | CPU_FTR_CTRL,
92 .cpu_user_features = COMMON_USER_PPC64, 76 .cpu_user_features = COMMON_USER_PPC64,
93 .icache_bsize = 128, 77 .icache_bsize = 128,
94 .dcache_bsize = 128, 78 .dcache_bsize = 128,
@@ -103,9 +87,7 @@ struct cpu_spec cpu_specs[] = {
103 .pvr_mask = 0xffff0000, 87 .pvr_mask = 0xffff0000,
104 .pvr_value = 0x00340000, 88 .pvr_value = 0x00340000,
105 .cpu_name = "RS64-III (pulsar)", 89 .cpu_name = "RS64-III (pulsar)",
106 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 90 .cpu_features = CPU_FTRS_RS64,
107 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
108 CPU_FTR_MMCRA | CPU_FTR_CTRL,
109 .cpu_user_features = COMMON_USER_PPC64, 91 .cpu_user_features = COMMON_USER_PPC64,
110 .icache_bsize = 128, 92 .icache_bsize = 128,
111 .dcache_bsize = 128, 93 .dcache_bsize = 128,
@@ -120,9 +102,7 @@ struct cpu_spec cpu_specs[] = {
120 .pvr_mask = 0xffff0000, 102 .pvr_mask = 0xffff0000,
121 .pvr_value = 0x00360000, 103 .pvr_value = 0x00360000,
122 .cpu_name = "RS64-III (icestar)", 104 .cpu_name = "RS64-III (icestar)",
123 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 105 .cpu_features = CPU_FTRS_RS64,
124 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
125 CPU_FTR_MMCRA | CPU_FTR_CTRL,
126 .cpu_user_features = COMMON_USER_PPC64, 106 .cpu_user_features = COMMON_USER_PPC64,
127 .icache_bsize = 128, 107 .icache_bsize = 128,
128 .dcache_bsize = 128, 108 .dcache_bsize = 128,
@@ -137,9 +117,7 @@ struct cpu_spec cpu_specs[] = {
137 .pvr_mask = 0xffff0000, 117 .pvr_mask = 0xffff0000,
138 .pvr_value = 0x00370000, 118 .pvr_value = 0x00370000,
139 .cpu_name = "RS64-IV (sstar)", 119 .cpu_name = "RS64-IV (sstar)",
140 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 120 .cpu_features = CPU_FTRS_RS64,
141 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
142 CPU_FTR_MMCRA | CPU_FTR_CTRL,
143 .cpu_user_features = COMMON_USER_PPC64, 121 .cpu_user_features = COMMON_USER_PPC64,
144 .icache_bsize = 128, 122 .icache_bsize = 128,
145 .dcache_bsize = 128, 123 .dcache_bsize = 128,
@@ -154,9 +132,7 @@ struct cpu_spec cpu_specs[] = {
154 .pvr_mask = 0xffff0000, 132 .pvr_mask = 0xffff0000,
155 .pvr_value = 0x00350000, 133 .pvr_value = 0x00350000,
156 .cpu_name = "POWER4 (gp)", 134 .cpu_name = "POWER4 (gp)",
157 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 135 .cpu_features = CPU_FTRS_POWER4,
158 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
159 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
160 .cpu_user_features = COMMON_USER_PPC64, 136 .cpu_user_features = COMMON_USER_PPC64,
161 .icache_bsize = 128, 137 .icache_bsize = 128,
162 .dcache_bsize = 128, 138 .dcache_bsize = 128,
@@ -171,9 +147,7 @@ struct cpu_spec cpu_specs[] = {
171 .pvr_mask = 0xffff0000, 147 .pvr_mask = 0xffff0000,
172 .pvr_value = 0x00380000, 148 .pvr_value = 0x00380000,
173 .cpu_name = "POWER4+ (gq)", 149 .cpu_name = "POWER4+ (gq)",
174 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 150 .cpu_features = CPU_FTRS_POWER4,
175 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
176 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
177 .cpu_user_features = COMMON_USER_PPC64, 151 .cpu_user_features = COMMON_USER_PPC64,
178 .icache_bsize = 128, 152 .icache_bsize = 128,
179 .dcache_bsize = 128, 153 .dcache_bsize = 128,
@@ -188,10 +162,7 @@ struct cpu_spec cpu_specs[] = {
188 .pvr_mask = 0xffff0000, 162 .pvr_mask = 0xffff0000,
189 .pvr_value = 0x00390000, 163 .pvr_value = 0x00390000,
190 .cpu_name = "PPC970", 164 .cpu_name = "PPC970",
191 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 165 .cpu_features = CPU_FTRS_PPC970,
192 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
193 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
194 CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
195 .cpu_user_features = COMMON_USER_PPC64 | 166 .cpu_user_features = COMMON_USER_PPC64 |
196 PPC_FEATURE_HAS_ALTIVEC_COMP, 167 PPC_FEATURE_HAS_ALTIVEC_COMP,
197 .icache_bsize = 128, 168 .icache_bsize = 128,
@@ -207,10 +178,7 @@ struct cpu_spec cpu_specs[] = {
207 .pvr_mask = 0xffff0000, 178 .pvr_mask = 0xffff0000,
208 .pvr_value = 0x003c0000, 179 .pvr_value = 0x003c0000,
209 .cpu_name = "PPC970FX", 180 .cpu_name = "PPC970FX",
210 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 181 .cpu_features = CPU_FTRS_PPC970,
211 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
212 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
213 CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
214 .cpu_user_features = COMMON_USER_PPC64 | 182 .cpu_user_features = COMMON_USER_PPC64 |
215 PPC_FEATURE_HAS_ALTIVEC_COMP, 183 PPC_FEATURE_HAS_ALTIVEC_COMP,
216 .icache_bsize = 128, 184 .icache_bsize = 128,
@@ -226,10 +194,7 @@ struct cpu_spec cpu_specs[] = {
226 .pvr_mask = 0xffff0000, 194 .pvr_mask = 0xffff0000,
227 .pvr_value = 0x00440000, 195 .pvr_value = 0x00440000,
228 .cpu_name = "PPC970MP", 196 .cpu_name = "PPC970MP",
229 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 197 .cpu_features = CPU_FTRS_PPC970,
230 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
231 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
232 CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
233 .cpu_user_features = COMMON_USER_PPC64 | 198 .cpu_user_features = COMMON_USER_PPC64 |
234 PPC_FEATURE_HAS_ALTIVEC_COMP, 199 PPC_FEATURE_HAS_ALTIVEC_COMP,
235 .icache_bsize = 128, 200 .icache_bsize = 128,
@@ -244,11 +209,7 @@ struct cpu_spec cpu_specs[] = {
244 .pvr_mask = 0xffff0000, 209 .pvr_mask = 0xffff0000,
245 .pvr_value = 0x003a0000, 210 .pvr_value = 0x003a0000,
246 .cpu_name = "POWER5 (gr)", 211 .cpu_name = "POWER5 (gr)",
247 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 212 .cpu_features = CPU_FTRS_POWER5,
248 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
249 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
250 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
251 CPU_FTR_MMCRA_SIHV,
252 .cpu_user_features = COMMON_USER_PPC64, 213 .cpu_user_features = COMMON_USER_PPC64,
253 .icache_bsize = 128, 214 .icache_bsize = 128,
254 .dcache_bsize = 128, 215 .dcache_bsize = 128,
@@ -263,11 +224,7 @@ struct cpu_spec cpu_specs[] = {
263 .pvr_mask = 0xffff0000, 224 .pvr_mask = 0xffff0000,
264 .pvr_value = 0x003b0000, 225 .pvr_value = 0x003b0000,
265 .cpu_name = "POWER5 (gs)", 226 .cpu_name = "POWER5 (gs)",
266 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 227 .cpu_features = CPU_FTRS_POWER5,
267 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
268 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
269 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
270 CPU_FTR_MMCRA_SIHV,
271 .cpu_user_features = COMMON_USER_PPC64, 228 .cpu_user_features = COMMON_USER_PPC64,
272 .icache_bsize = 128, 229 .icache_bsize = 128,
273 .dcache_bsize = 128, 230 .dcache_bsize = 128,
@@ -281,11 +238,8 @@ struct cpu_spec cpu_specs[] = {
281 { /* BE DD1.x */ 238 { /* BE DD1.x */
282 .pvr_mask = 0xffff0000, 239 .pvr_mask = 0xffff0000,
283 .pvr_value = 0x00700000, 240 .pvr_value = 0x00700000,
284 .cpu_name = "Broadband Engine", 241 .cpu_name = "Cell Broadband Engine",
285 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 242 .cpu_features = CPU_FTRS_CELL,
286 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
287 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
288 CPU_FTR_SMT,
289 .cpu_user_features = COMMON_USER_PPC64 | 243 .cpu_user_features = COMMON_USER_PPC64 |
290 PPC_FEATURE_HAS_ALTIVEC_COMP, 244 PPC_FEATURE_HAS_ALTIVEC_COMP,
291 .icache_bsize = 128, 245 .icache_bsize = 128,
@@ -296,9 +250,7 @@ struct cpu_spec cpu_specs[] = {
296 .pvr_mask = 0x00000000, 250 .pvr_mask = 0x00000000,
297 .pvr_value = 0x00000000, 251 .pvr_value = 0x00000000,
298 .cpu_name = "POWER4 (compatible)", 252 .cpu_name = "POWER4 (compatible)",
299 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 253 .cpu_features = CPU_FTRS_COMPATIBLE,
300 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
301 CPU_FTR_PPCAS_ARCH_V2,
302 .cpu_user_features = COMMON_USER_PPC64, 254 .cpu_user_features = COMMON_USER_PPC64,
303 .icache_bsize = 128, 255 .icache_bsize = 128,
304 .dcache_bsize = 128, 256 .dcache_bsize = 128,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 18:06:31 -0500