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authorPaul Mackerras <paulus@samba.org>2008-06-09 00:01:46 -0400
committerPaul Mackerras <paulus@samba.org>2008-06-10 07:40:22 -0400
commit917f0af9e5a9ceecf9e72537fabb501254ba321d (patch)
tree1ef207755c6d83ce4af93ef2b5e4645eebd65886 /arch/ppc/xmon
parent0f3d6bcd391b058c619fc30e8022e8a29fbf4bef (diff)
powerpc: Remove arch/ppc and include/asm-ppc
All the maintained platforms are now in arch/powerpc, so the old arch/ppc stuff can now go away. Acked-by: Adrian Bunk <bunk@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Jochen Friedrich <jochen@scram.de> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Sean MacLennan <smaclennan@pikatech.com> Acked-by: Segher Boessenkool <segher@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/xmon')
-rw-r--r--arch/ppc/xmon/Makefile8
-rw-r--r--arch/ppc/xmon/ansidecl.h141
-rw-r--r--arch/ppc/xmon/nonstdio.h22
-rw-r--r--arch/ppc/xmon/ppc-dis.c190
-rw-r--r--arch/ppc/xmon/ppc-opc.c2720
-rw-r--r--arch/ppc/xmon/ppc.h240
-rw-r--r--arch/ppc/xmon/privinst.h90
-rw-r--r--arch/ppc/xmon/setjmp.c29
-rw-r--r--arch/ppc/xmon/start.c342
-rw-r--r--arch/ppc/xmon/start_8xx.c287
-rw-r--r--arch/ppc/xmon/subr_prf.c55
-rw-r--r--arch/ppc/xmon/xmon.c1780
12 files changed, 0 insertions, 5904 deletions
diff --git a/arch/ppc/xmon/Makefile b/arch/ppc/xmon/Makefile
deleted file mode 100644
index 9aa260b926f5..000000000000
--- a/arch/ppc/xmon/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1# Makefile for xmon
2
3ifdef CONFIG_8xx
4obj-y := start_8xx.o
5else
6obj-y := start.o
7endif
8obj-y += xmon.o ppc-dis.o ppc-opc.o subr_prf.o setjmp.o
diff --git a/arch/ppc/xmon/ansidecl.h b/arch/ppc/xmon/ansidecl.h
deleted file mode 100644
index c9b9f0929e9e..000000000000
--- a/arch/ppc/xmon/ansidecl.h
+++ /dev/null
@@ -1,141 +0,0 @@
1/* ANSI and traditional C compatibility macros
2 Copyright 1991, 1992 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4
5This program is free software; you can redistribute it and/or modify
6it under the terms of the GNU General Public License as published by
7the Free Software Foundation; either version 2 of the License, or
8(at your option) any later version.
9
10This program is distributed in the hope that it will be useful,
11but WITHOUT ANY WARRANTY; without even the implied warranty of
12MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13GNU General Public License for more details.
14
15You should have received a copy of the GNU General Public License
16along with this program; if not, write to the Free Software
17Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
18
19/* ANSI and traditional C compatibility macros
20
21 ANSI C is assumed if __STDC__ is #defined.
22
23 Macro ANSI C definition Traditional C definition
24 ----- ---- - ---------- ----------- - ----------
25 PTR `void *' `char *'
26 LONG_DOUBLE `long double' `double'
27 VOLATILE `volatile' `'
28 SIGNED `signed' `'
29 PTRCONST `void *const' `char *'
30 ANSI_PROTOTYPES 1 not defined
31
32 CONST is also defined, but is obsolete. Just use const.
33
34 DEFUN (name, arglist, args)
35
36 Defines function NAME.
37
38 ARGLIST lists the arguments, separated by commas and enclosed in
39 parentheses. ARGLIST becomes the argument list in traditional C.
40
41 ARGS list the arguments with their types. It becomes a prototype in
42 ANSI C, and the type declarations in traditional C. Arguments should
43 be separated with `AND'. For functions with a variable number of
44 arguments, the last thing listed should be `DOTS'.
45
46 DEFUN_VOID (name)
47
48 Defines a function NAME, which takes no arguments.
49
50 obsolete -- EXFUN (name, (prototype)) -- obsolete.
51
52 Replaced by PARAMS. Do not use; will disappear someday soon.
53 Was used in external function declarations.
54 In ANSI C it is `NAME PROTOTYPE' (so PROTOTYPE should be enclosed in
55 parentheses). In traditional C it is `NAME()'.
56 For a function that takes no arguments, PROTOTYPE should be `(void)'.
57
58 PARAMS ((args))
59
60 We could use the EXFUN macro to handle prototype declarations, but
61 the name is misleading and the result is ugly. So we just define a
62 simple macro to handle the parameter lists, as in:
63
64 static int foo PARAMS ((int, char));
65
66 This produces: `static int foo();' or `static int foo (int, char);'
67
68 EXFUN would have done it like this:
69
70 static int EXFUN (foo, (int, char));
71
72 but the function is not external...and it's hard to visually parse
73 the function name out of the mess. EXFUN should be considered
74 obsolete; new code should be written to use PARAMS.
75
76 For example:
77 extern int printf PARAMS ((CONST char *format DOTS));
78 int DEFUN(fprintf, (stream, format),
79 FILE *stream AND CONST char *format DOTS) { ... }
80 void DEFUN_VOID(abort) { ... }
81*/
82
83#ifndef _ANSIDECL_H
84
85#define _ANSIDECL_H 1
86
87
88/* Every source file includes this file,
89 so they will all get the switch for lint. */
90/* LINTLIBRARY */
91
92
93#if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(WIN32)
94/* All known AIX compilers implement these things (but don't always
95 define __STDC__). The RISC/OS MIPS compiler defines these things
96 in SVR4 mode, but does not define __STDC__. */
97
98#define PTR void *
99#define PTRCONST void *CONST
100#define LONG_DOUBLE long double
101
102#define AND ,
103#define NOARGS void
104#define CONST const
105#define VOLATILE volatile
106#define SIGNED signed
107#define DOTS , ...
108
109#define EXFUN(name, proto) name proto
110#define DEFUN(name, arglist, args) name(args)
111#define DEFUN_VOID(name) name(void)
112
113#define PROTO(type, name, arglist) type name arglist
114#define PARAMS(paramlist) paramlist
115#define ANSI_PROTOTYPES 1
116
117#else /* Not ANSI C. */
118
119#define PTR char *
120#define PTRCONST PTR
121#define LONG_DOUBLE double
122
123#define AND ;
124#define NOARGS
125#define CONST
126#ifndef const /* some systems define it in header files for non-ansi mode */
127#define const
128#endif
129#define VOLATILE
130#define SIGNED
131#define DOTS
132
133#define EXFUN(name, proto) name()
134#define DEFUN(name, arglist, args) name arglist args;
135#define DEFUN_VOID(name) name()
136#define PROTO(type, name, arglist) type name ()
137#define PARAMS(paramlist) ()
138
139#endif /* ANSI C. */
140
141#endif /* ansidecl.h */
diff --git a/arch/ppc/xmon/nonstdio.h b/arch/ppc/xmon/nonstdio.h
deleted file mode 100644
index 0240bc573c96..000000000000
--- a/arch/ppc/xmon/nonstdio.h
+++ /dev/null
@@ -1,22 +0,0 @@
1typedef int FILE;
2extern FILE *xmon_stdin, *xmon_stdout;
3#define EOF (-1)
4#define stdin xmon_stdin
5#define stdout xmon_stdout
6#define printf xmon_printf
7#define fprintf xmon_fprintf
8#define fputs xmon_fputs
9#define fgets xmon_fgets
10#define putchar xmon_putchar
11#define getchar xmon_getchar
12#define putc xmon_putc
13#define getc xmon_getc
14#define fopen(n, m) NULL
15#define fflush(f) do {} while (0)
16#define fclose(f) do {} while (0)
17extern char *fgets(char *, int, void *);
18extern void xmon_fprintf(void *, const char *, ...);
19extern void xmon_sprintf(char *, const char *, ...);
20extern void xmon_puts(char*);
21
22#define perror(s) printf("%s: no files!\n", (s))
diff --git a/arch/ppc/xmon/ppc-dis.c b/arch/ppc/xmon/ppc-dis.c
deleted file mode 100644
index 798ac1a677f6..000000000000
--- a/arch/ppc/xmon/ppc-dis.c
+++ /dev/null
@@ -1,190 +0,0 @@
1/* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
102, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#include "nonstdio.h"
22#include "ansidecl.h"
23#include "ppc.h"
24
25static int print_insn_powerpc PARAMS ((FILE *, unsigned long insn,
26 unsigned memaddr, int dialect));
27
28extern void print_address PARAMS((unsigned memaddr));
29
30/* Print a big endian PowerPC instruction. For convenience, also
31 disassemble instructions supported by the Motorola PowerPC 601. */
32
33int
34print_insn_big_powerpc (FILE *out, unsigned long insn, unsigned memaddr)
35{
36 return print_insn_powerpc (out, insn, memaddr,
37 PPC_OPCODE_PPC | PPC_OPCODE_601);
38}
39
40/* Print a PowerPC or POWER instruction. */
41
42static int
43print_insn_powerpc (FILE *out, unsigned long insn, unsigned memaddr,
44 int dialect)
45{
46 const struct powerpc_opcode *opcode;
47 const struct powerpc_opcode *opcode_end;
48 unsigned long op;
49
50 /* Get the major opcode of the instruction. */
51 op = PPC_OP (insn);
52
53 /* Find the first match in the opcode table. We could speed this up
54 a bit by doing a binary search on the major opcode. */
55 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
56 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
57 {
58 unsigned long table_op;
59 const unsigned char *opindex;
60 const struct powerpc_operand *operand;
61 int invalid;
62 int need_comma;
63 int need_paren;
64
65 table_op = PPC_OP (opcode->opcode);
66 if (op < table_op)
67 break;
68 if (op > table_op)
69 continue;
70
71 if ((insn & opcode->mask) != opcode->opcode
72 || (opcode->flags & dialect) == 0)
73 continue;
74
75 /* Make two passes over the operands. First see if any of them
76 have extraction functions, and, if they do, make sure the
77 instruction is valid. */
78 invalid = 0;
79 for (opindex = opcode->operands; *opindex != 0; opindex++)
80 {
81 operand = powerpc_operands + *opindex;
82 if (operand->extract)
83 (*operand->extract) (insn, &invalid);
84 }
85 if (invalid)
86 continue;
87
88 /* The instruction is valid. */
89 fprintf(out, "%s", opcode->name);
90 if (opcode->operands[0] != 0)
91 fprintf(out, "\t");
92
93 /* Now extract and print the operands. */
94 need_comma = 0;
95 need_paren = 0;
96 for (opindex = opcode->operands; *opindex != 0; opindex++)
97 {
98 long value;
99
100 operand = powerpc_operands + *opindex;
101
102 /* Operands that are marked FAKE are simply ignored. We
103 already made sure that the extract function considered
104 the instruction to be valid. */
105 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
106 continue;
107
108 /* Extract the value from the instruction. */
109 if (operand->extract)
110 value = (*operand->extract) (insn, (int *) 0);
111 else
112 {
113 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
114 if ((operand->flags & PPC_OPERAND_SIGNED) != 0
115 && (value & (1 << (operand->bits - 1))) != 0)
116 value -= 1 << operand->bits;
117 }
118
119 /* If the operand is optional, and the value is zero, don't
120 print anything. */
121 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
122 && (operand->flags & PPC_OPERAND_NEXT) == 0
123 && value == 0)
124 continue;
125
126 if (need_comma)
127 {
128 fprintf(out, ",");
129 need_comma = 0;
130 }
131
132 /* Print the operand as directed by the flags. */
133 if ((operand->flags & PPC_OPERAND_GPR) != 0)
134 fprintf(out, "r%ld", value);
135 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
136 fprintf(out, "f%ld", value);
137 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
138 print_address (memaddr + value);
139 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
140 print_address (value & 0xffffffff);
141 else if ((operand->flags & PPC_OPERAND_CR) == 0
142 || (dialect & PPC_OPCODE_PPC) == 0)
143 fprintf(out, "%ld", value);
144 else
145 {
146 if (operand->bits == 3)
147 fprintf(out, "cr%d", value);
148 else
149 {
150 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
151 int cr;
152 int cc;
153
154 cr = value >> 2;
155 if (cr != 0)
156 fprintf(out, "4*cr%d", cr);
157 cc = value & 3;
158 if (cc != 0)
159 {
160 if (cr != 0)
161 fprintf(out, "+");
162 fprintf(out, "%s", cbnames[cc]);
163 }
164 }
165 }
166
167 if (need_paren)
168 {
169 fprintf(out, ")");
170 need_paren = 0;
171 }
172
173 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
174 need_comma = 1;
175 else
176 {
177 fprintf(out, "(");
178 need_paren = 1;
179 }
180 }
181
182 /* We have found and printed an instruction; return. */
183 return 4;
184 }
185
186 /* We could not find a match. */
187 fprintf(out, ".long 0x%lx", insn);
188
189 return 4;
190}
diff --git a/arch/ppc/xmon/ppc-opc.c b/arch/ppc/xmon/ppc-opc.c
deleted file mode 100644
index 034313cef6e7..000000000000
--- a/arch/ppc/xmon/ppc-opc.c
+++ /dev/null
@@ -1,2720 +0,0 @@
1/* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
102, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#include <linux/posix_types.h>
22#include <linux/kernel.h>
23#include "ansidecl.h"
24#include "ppc.h"
25
26/* This file holds the PowerPC opcode table. The opcode table
27 includes almost all of the extended instruction mnemonics. This
28 permits the disassembler to use them, and simplifies the assembler
29 logic, at the cost of increasing the table size. The table is
30 strictly constant data, so the compiler should be able to put it in
31 the .text section.
32
33 This file also holds the operand table. All knowledge about
34 inserting operands into instructions and vice-versa is kept in this
35 file. */
36
37/* Local insertion and extraction functions. */
38
39static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
40static long extract_bat PARAMS ((unsigned long, int *));
41static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
42static long extract_bba PARAMS ((unsigned long, int *));
43static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
44static long extract_bd PARAMS ((unsigned long, int *));
45static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
46static long extract_bdm PARAMS ((unsigned long, int *));
47static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
48static long extract_bdp PARAMS ((unsigned long, int *));
49static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
50static long extract_bo PARAMS ((unsigned long, int *));
51static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
52static long extract_boe PARAMS ((unsigned long, int *));
53static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
54static long extract_ds PARAMS ((unsigned long, int *));
55static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
56static long extract_li PARAMS ((unsigned long, int *));
57static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
58static long extract_mbe PARAMS ((unsigned long, int *));
59static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
60static long extract_mb6 PARAMS ((unsigned long, int *));
61static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
62static long extract_nb PARAMS ((unsigned long, int *));
63static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
64static long extract_nsi PARAMS ((unsigned long, int *));
65static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
66static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
67static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
68static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
69static long extract_rbs PARAMS ((unsigned long, int *));
70static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
71static long extract_sh6 PARAMS ((unsigned long, int *));
72static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
73static long extract_spr PARAMS ((unsigned long, int *));
74static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
75static long extract_tbr PARAMS ((unsigned long, int *));
76
77/* The operands table.
78
79 The fields are bits, shift, signed, insert, extract, flags. */
80
81const struct powerpc_operand powerpc_operands[] =
82{
83 /* The zero index is used to indicate the end of the list of
84 operands. */
85#define UNUSED (0)
86 { 0, 0, NULL, NULL, 0 },
87
88 /* The BA field in an XL form instruction. */
89#define BA (1)
90#define BA_MASK (0x1f << 16)
91 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
92
93 /* The BA field in an XL form instruction when it must be the same
94 as the BT field in the same instruction. */
95#define BAT (2)
96 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
97
98 /* The BB field in an XL form instruction. */
99#define BB (3)
100#define BB_MASK (0x1f << 11)
101 { 5, 11, NULL, NULL, PPC_OPERAND_CR },
102
103 /* The BB field in an XL form instruction when it must be the same
104 as the BA field in the same instruction. */
105#define BBA (4)
106 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
107
108 /* The BD field in a B form instruction. The lower two bits are
109 forced to zero. */
110#define BD (5)
111 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
112
113 /* The BD field in a B form instruction when absolute addressing is
114 used. */
115#define BDA (6)
116 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
117
118 /* The BD field in a B form instruction when the - modifier is used.
119 This sets the y bit of the BO field appropriately. */
120#define BDM (7)
121 { 16, 0, insert_bdm, extract_bdm,
122 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
123
124 /* The BD field in a B form instruction when the - modifier is used
125 and absolute address is used. */
126#define BDMA (8)
127 { 16, 0, insert_bdm, extract_bdm,
128 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
129
130 /* The BD field in a B form instruction when the + modifier is used.
131 This sets the y bit of the BO field appropriately. */
132#define BDP (9)
133 { 16, 0, insert_bdp, extract_bdp,
134 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
135
136 /* The BD field in a B form instruction when the + modifier is used
137 and absolute addressing is used. */
138#define BDPA (10)
139 { 16, 0, insert_bdp, extract_bdp,
140 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
141
142 /* The BF field in an X or XL form instruction. */
143#define BF (11)
144 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
145
146 /* An optional BF field. This is used for comparison instructions,
147 in which an omitted BF field is taken as zero. */
148#define OBF (12)
149 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
150
151 /* The BFA field in an X or XL form instruction. */
152#define BFA (13)
153 { 3, 18, NULL, NULL, PPC_OPERAND_CR },
154
155 /* The BI field in a B form or XL form instruction. */
156#define BI (14)
157#define BI_MASK (0x1f << 16)
158 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
159
160 /* The BO field in a B form instruction. Certain values are
161 illegal. */
162#define BO (15)
163#define BO_MASK (0x1f << 21)
164 { 5, 21, insert_bo, extract_bo, 0 },
165
166 /* The BO field in a B form instruction when the + or - modifier is
167 used. This is like the BO field, but it must be even. */
168#define BOE (16)
169 { 5, 21, insert_boe, extract_boe, 0 },
170
171 /* The BT field in an X or XL form instruction. */
172#define BT (17)
173 { 5, 21, NULL, NULL, PPC_OPERAND_CR },
174
175 /* The condition register number portion of the BI field in a B form
176 or XL form instruction. This is used for the extended
177 conditional branch mnemonics, which set the lower two bits of the
178 BI field. This field is optional. */
179#define CR (18)
180 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
181
182 /* The D field in a D form instruction. This is a displacement off
183 a register, and implies that the next operand is a register in
184 parentheses. */
185#define D (19)
186 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
187
188 /* The DS field in a DS form instruction. This is like D, but the
189 lower two bits are forced to zero. */
190#define DS (20)
191 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
192
193 /* The FL1 field in a POWER SC form instruction. */
194#define FL1 (21)
195 { 4, 12, NULL, NULL, 0 },
196
197 /* The FL2 field in a POWER SC form instruction. */
198#define FL2 (22)
199 { 3, 2, NULL, NULL, 0 },
200
201 /* The FLM field in an XFL form instruction. */
202#define FLM (23)
203 { 8, 17, NULL, NULL, 0 },
204
205 /* The FRA field in an X or A form instruction. */
206#define FRA (24)
207#define FRA_MASK (0x1f << 16)
208 { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
209
210 /* The FRB field in an X or A form instruction. */
211#define FRB (25)
212#define FRB_MASK (0x1f << 11)
213 { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
214
215 /* The FRC field in an A form instruction. */
216#define FRC (26)
217#define FRC_MASK (0x1f << 6)
218 { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
219
220 /* The FRS field in an X form instruction or the FRT field in a D, X
221 or A form instruction. */
222#define FRS (27)
223#define FRT (FRS)
224 { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
225
226 /* The FXM field in an XFX instruction. */
227#define FXM (28)
228#define FXM_MASK (0xff << 12)
229 { 8, 12, NULL, NULL, 0 },
230
231 /* The L field in a D or X form instruction. */
232#define L (29)
233 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
234
235 /* The LEV field in a POWER SC form instruction. */
236#define LEV (30)
237 { 7, 5, NULL, NULL, 0 },
238
239 /* The LI field in an I form instruction. The lower two bits are
240 forced to zero. */
241#define LI (31)
242 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
243
244 /* The LI field in an I form instruction when used as an absolute
245 address. */
246#define LIA (32)
247 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
248
249 /* The MB field in an M form instruction. */
250#define MB (33)
251#define MB_MASK (0x1f << 6)
252 { 5, 6, NULL, NULL, 0 },
253
254 /* The ME field in an M form instruction. */
255#define ME (34)
256#define ME_MASK (0x1f << 1)
257 { 5, 1, NULL, NULL, 0 },
258
259 /* The MB and ME fields in an M form instruction expressed a single
260 operand which is a bitmask indicating which bits to select. This
261 is a two operand form using PPC_OPERAND_NEXT. See the
262 description in opcode/ppc.h for what this means. */
263#define MBE (35)
264 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
265 { 32, 0, insert_mbe, extract_mbe, 0 },
266
267 /* The MB or ME field in an MD or MDS form instruction. The high
268 bit is wrapped to the low end. */
269#define MB6 (37)
270#define ME6 (MB6)
271#define MB6_MASK (0x3f << 5)
272 { 6, 5, insert_mb6, extract_mb6, 0 },
273
274 /* The NB field in an X form instruction. The value 32 is stored as
275 0. */
276#define NB (38)
277 { 6, 11, insert_nb, extract_nb, 0 },
278
279 /* The NSI field in a D form instruction. This is the same as the
280 SI field, only negated. */
281#define NSI (39)
282 { 16, 0, insert_nsi, extract_nsi,
283 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
284
285 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
286#define RA (40)
287#define RA_MASK (0x1f << 16)
288 { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
289
290 /* The RA field in a D or X form instruction which is an updating
291 load, which means that the RA field may not be zero and may not
292 equal the RT field. */
293#define RAL (41)
294 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR },
295
296 /* The RA field in an lmw instruction, which has special value
297 restrictions. */
298#define RAM (42)
299 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR },
300
301 /* The RA field in a D or X form instruction which is an updating
302 store or an updating floating point load, which means that the RA
303 field may not be zero. */
304#define RAS (43)
305 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR },
306
307 /* The RB field in an X, XO, M, or MDS form instruction. */
308#define RB (44)
309#define RB_MASK (0x1f << 11)
310 { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
311
312 /* The RB field in an X form instruction when it must be the same as
313 the RS field in the instruction. This is used for extended
314 mnemonics like mr. */
315#define RBS (45)
316 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
317
318 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
319 instruction or the RT field in a D, DS, X, XFX or XO form
320 instruction. */
321#define RS (46)
322#define RT (RS)
323#define RT_MASK (0x1f << 21)
324 { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
325
326 /* The SH field in an X or M form instruction. */
327#define SH (47)
328#define SH_MASK (0x1f << 11)
329 { 5, 11, NULL, NULL, 0 },
330
331 /* The SH field in an MD form instruction. This is split. */
332#define SH6 (48)
333#define SH6_MASK ((0x1f << 11) | (1 << 1))
334 { 6, 1, insert_sh6, extract_sh6, 0 },
335
336 /* The SI field in a D form instruction. */
337#define SI (49)
338 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
339
340 /* The SI field in a D form instruction when we accept a wide range
341 of positive values. */
342#define SISIGNOPT (50)
343 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
344
345 /* The SPR field in an XFX form instruction. This is flipped--the
346 lower 5 bits are stored in the upper 5 and vice- versa. */
347#define SPR (51)
348#define SPR_MASK (0x3ff << 11)
349 { 10, 11, insert_spr, extract_spr, 0 },
350
351 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
352#define SPRBAT (52)
353#define SPRBAT_MASK (0x3 << 17)
354 { 2, 17, NULL, NULL, 0 },
355
356 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
357#define SPRG (53)
358#define SPRG_MASK (0x3 << 16)
359 { 2, 16, NULL, NULL, 0 },
360
361 /* The SR field in an X form instruction. */
362#define SR (54)
363 { 4, 16, NULL, NULL, 0 },
364
365 /* The SV field in a POWER SC form instruction. */
366#define SV (55)
367 { 14, 2, NULL, NULL, 0 },
368
369 /* The TBR field in an XFX form instruction. This is like the SPR
370 field, but it is optional. */
371#define TBR (56)
372 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
373
374 /* The TO field in a D or X form instruction. */
375#define TO (57)
376#define TO_MASK (0x1f << 21)
377 { 5, 21, NULL, NULL, 0 },
378
379 /* The U field in an X form instruction. */
380#define U (58)
381 { 4, 12, NULL, NULL, 0 },
382
383 /* The UI field in a D form instruction. */
384#define UI (59)
385 { 16, 0, NULL, NULL, 0 },
386};
387
388/* The functions used to insert and extract complicated operands. */
389
390/* The BA field in an XL form instruction when it must be the same as
391 the BT field in the same instruction. This operand is marked FAKE.
392 The insertion function just copies the BT field into the BA field,
393 and the extraction function just checks that the fields are the
394 same. */
395
396/*ARGSUSED*/
397static unsigned long
398insert_bat(unsigned long insn, long value, const char **errmsg)
399{
400 return insn | (((insn >> 21) & 0x1f) << 16);
401}
402
403static long
404extract_bat(unsigned long insn, int *invalid)
405{
406 if (invalid != (int *) NULL
407 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
408 *invalid = 1;
409 return 0;
410}
411
412/* The BB field in an XL form instruction when it must be the same as
413 the BA field in the same instruction. This operand is marked FAKE.
414 The insertion function just copies the BA field into the BB field,
415 and the extraction function just checks that the fields are the
416 same. */
417
418/*ARGSUSED*/
419static unsigned long
420insert_bba(unsigned long insn, long value, const char **errmsg)
421{
422 return insn | (((insn >> 16) & 0x1f) << 11);
423}
424
425static long
426extract_bba(unsigned long insn, int *invalid)
427{
428 if (invalid != (int *) NULL
429 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
430 *invalid = 1;
431 return 0;
432}
433
434/* The BD field in a B form instruction. The lower two bits are
435 forced to zero. */
436
437/*ARGSUSED*/
438static unsigned long
439insert_bd(unsigned long insn, long value, const char **errmsg)
440{
441 return insn | (value & 0xfffc);
442}
443
444/*ARGSUSED*/
445static long
446extract_bd(unsigned long insn, int *invalid)
447{
448 if ((insn & 0x8000) != 0)
449 return (insn & 0xfffc) - 0x10000;
450 else
451 return insn & 0xfffc;
452}
453
454/* The BD field in a B form instruction when the - modifier is used.
455 This modifier means that the branch is not expected to be taken.
456 We must set the y bit of the BO field to 1 if the offset is
457 negative. When extracting, we require that the y bit be 1 and that
458 the offset be positive, since if the y bit is 0 we just want to
459 print the normal form of the instruction. */
460
461/*ARGSUSED*/
462static unsigned long
463insert_bdm(unsigned long insn, long value, const char **errmsg)
464{
465 if ((value & 0x8000) != 0)
466 insn |= 1 << 21;
467 return insn | (value & 0xfffc);
468}
469
470static long
471extract_bdm(unsigned long insn, int *invalid)
472{
473 if (invalid != (int *) NULL
474 && ((insn & (1 << 21)) == 0
475 || (insn & (1 << 15)) == 0))
476 *invalid = 1;
477 if ((insn & 0x8000) != 0)
478 return (insn & 0xfffc) - 0x10000;
479 else
480 return insn & 0xfffc;
481}
482
483/* The BD field in a B form instruction when the + modifier is used.
484 This is like BDM, above, except that the branch is expected to be
485 taken. */
486
487/*ARGSUSED*/
488static unsigned long
489insert_bdp(unsigned long insn, long value, const char **errmsg)
490{
491 if ((value & 0x8000) == 0)
492 insn |= 1 << 21;
493 return insn | (value & 0xfffc);
494}
495
496static long
497extract_bdp(unsigned long insn, int *invalid)
498{
499 if (invalid != (int *) NULL
500 && ((insn & (1 << 21)) == 0
501 || (insn & (1 << 15)) != 0))
502 *invalid = 1;
503 if ((insn & 0x8000) != 0)
504 return (insn & 0xfffc) - 0x10000;
505 else
506 return insn & 0xfffc;
507}
508
509/* Check for legal values of a BO field. */
510
511static int
512valid_bo (long value)
513{
514 /* Certain encodings have bits that are required to be zero. These
515 are (z must be zero, y may be anything):
516 001zy
517 011zy
518 1z00y
519 1z01y
520 1z1zz
521 */
522 switch (value & 0x14)
523 {
524 default:
525 case 0:
526 return 1;
527 case 0x4:
528 return (value & 0x2) == 0;
529 case 0x10:
530 return (value & 0x8) == 0;
531 case 0x14:
532 return value == 0x14;
533 }
534}
535
536/* The BO field in a B form instruction. Warn about attempts to set
537 the field to an illegal value. */
538
539static unsigned long
540insert_bo(unsigned long insn, long value, const char **errmsg)
541{
542 if (errmsg != (const char **) NULL
543 && ! valid_bo (value))
544 *errmsg = "invalid conditional option";
545 return insn | ((value & 0x1f) << 21);
546}
547
548static long
549extract_bo(unsigned long insn, int *invalid)
550{
551 long value;
552
553 value = (insn >> 21) & 0x1f;
554 if (invalid != (int *) NULL
555 && ! valid_bo (value))
556 *invalid = 1;
557 return value;
558}
559
560/* The BO field in a B form instruction when the + or - modifier is
561 used. This is like the BO field, but it must be even. When
562 extracting it, we force it to be even. */
563
564static unsigned long
565insert_boe(unsigned long insn, long value, const char **errmsg)
566{
567 if (errmsg != (const char **) NULL)
568 {
569 if (! valid_bo (value))
570 *errmsg = "invalid conditional option";
571 else if ((value & 1) != 0)
572 *errmsg = "attempt to set y bit when using + or - modifier";
573 }
574 return insn | ((value & 0x1f) << 21);
575}
576
577static long
578extract_boe(unsigned long insn, int *invalid)
579{
580 long value;
581
582 value = (insn >> 21) & 0x1f;
583 if (invalid != (int *) NULL
584 && ! valid_bo (value))
585 *invalid = 1;
586 return value & 0x1e;
587}
588
589/* The DS field in a DS form instruction. This is like D, but the
590 lower two bits are forced to zero. */
591
592/*ARGSUSED*/
593static unsigned long
594insert_ds(unsigned long insn, long value, const char **errmsg)
595{
596 return insn | (value & 0xfffc);
597}
598
599/*ARGSUSED*/
600static long
601extract_ds(unsigned long insn, int *invalid)
602{
603 if ((insn & 0x8000) != 0)
604 return (insn & 0xfffc) - 0x10000;
605 else
606 return insn & 0xfffc;
607}
608
609/* The LI field in an I form instruction. The lower two bits are
610 forced to zero. */
611
612/*ARGSUSED*/
613static unsigned long
614insert_li(unsigned long insn, long value, const char **errmsg)
615{
616 return insn | (value & 0x3fffffc);
617}
618
619/*ARGSUSED*/
620static long
621extract_li(unsigned long insn, int *invalid)
622{
623 if ((insn & 0x2000000) != 0)
624 return (insn & 0x3fffffc) - 0x4000000;
625 else
626 return insn & 0x3fffffc;
627}
628
629/* The MB and ME fields in an M form instruction expressed as a single
630 operand which is itself a bitmask. The extraction function always
631 marks it as invalid, since we never want to recognize an
632 instruction which uses a field of this type. */
633
634static unsigned long
635insert_mbe(unsigned long insn, long value, const char **errmsg)
636{
637 unsigned long uval;
638 int mb, me;
639
640 uval = value;
641
642 if (uval == 0)
643 {
644 if (errmsg != (const char **) NULL)
645 *errmsg = "illegal bitmask";
646 return insn;
647 }
648
649 me = 31;
650 while ((uval & 1) == 0)
651 {
652 uval >>= 1;
653 --me;
654 }
655
656 mb = me;
657 uval >>= 1;
658 while ((uval & 1) != 0)
659 {
660 uval >>= 1;
661 --mb;
662 }
663
664 if (uval != 0)
665 {
666 if (errmsg != (const char **) NULL)
667 *errmsg = "illegal bitmask";
668 }
669
670 return insn | (mb << 6) | (me << 1);
671}
672
673static long
674extract_mbe(unsigned long insn, int *invalid)
675{
676 long ret;
677 int mb, me;
678 int i;
679
680 if (invalid != (int *) NULL)
681 *invalid = 1;
682
683 ret = 0;
684 mb = (insn >> 6) & 0x1f;
685 me = (insn >> 1) & 0x1f;
686 for (i = mb; i < me; i++)
687 ret |= 1 << (31 - i);
688 return ret;
689}
690
691/* The MB or ME field in an MD or MDS form instruction. The high bit
692 is wrapped to the low end. */
693
694/*ARGSUSED*/
695static unsigned long
696insert_mb6(unsigned long insn, long value, const char **errmsg)
697{
698 return insn | ((value & 0x1f) << 6) | (value & 0x20);
699}
700
701/*ARGSUSED*/
702static long
703extract_mb6(unsigned long insn, int *invalid)
704{
705 return ((insn >> 6) & 0x1f) | (insn & 0x20);
706}
707
708/* The NB field in an X form instruction. The value 32 is stored as
709 0. */
710
711static unsigned long
712insert_nb(unsigned long insn, long value, const char **errmsg)
713{
714 if (value < 0 || value > 32)
715 *errmsg = "value out of range";
716 if (value == 32)
717 value = 0;
718 return insn | ((value & 0x1f) << 11);
719}
720
721/*ARGSUSED*/
722static long
723extract_nb(unsigned long insn, int *invalid)
724{
725 long ret;
726
727 ret = (insn >> 11) & 0x1f;
728 if (ret == 0)
729 ret = 32;
730 return ret;
731}
732
733/* The NSI field in a D form instruction. This is the same as the SI
734 field, only negated. The extraction function always marks it as
735 invalid, since we never want to recognize an instruction which uses
736 a field of this type. */
737
738/*ARGSUSED*/
739static unsigned long
740insert_nsi(unsigned long insn, long value, const char **errmsg)
741{
742 return insn | ((- value) & 0xffff);
743}
744
745static long
746extract_nsi(unsigned long insn, int *invalid)
747{
748 if (invalid != (int *) NULL)
749 *invalid = 1;
750 if ((insn & 0x8000) != 0)
751 return - ((insn & 0xffff) - 0x10000);
752 else
753 return - (insn & 0xffff);
754}
755
756/* The RA field in a D or X form instruction which is an updating
757 load, which means that the RA field may not be zero and may not
758 equal the RT field. */
759
760static unsigned long
761insert_ral(unsigned long insn, long value, const char **errmsg)
762{
763 if (value == 0
764 || value == ((insn >> 21) & 0x1f))
765 *errmsg = "invalid register operand when updating";
766 return insn | ((value & 0x1f) << 16);
767}
768
769/* The RA field in an lmw instruction, which has special value
770 restrictions. */
771
772static unsigned long
773insert_ram(unsigned long insn, long value, const char **errmsg)
774{
775 if (value >= ((insn >> 21) & 0x1f))
776 *errmsg = "index register in load range";
777 return insn | ((value & 0x1f) << 16);
778}
779
780/* The RA field in a D or X form instruction which is an updating
781 store or an updating floating point load, which means that the RA
782 field may not be zero. */
783
784static unsigned long
785insert_ras(unsigned long insn, long value, const char **errmsg)
786{
787 if (value == 0)
788 *errmsg = "invalid register operand when updating";
789 return insn | ((value & 0x1f) << 16);
790}
791
792/* The RB field in an X form instruction when it must be the same as
793 the RS field in the instruction. This is used for extended
794 mnemonics like mr. This operand is marked FAKE. The insertion
795 function just copies the BT field into the BA field, and the
796 extraction function just checks that the fields are the same. */
797
798/*ARGSUSED*/
799static unsigned long
800insert_rbs(unsigned long insn, long value, const char **errmsg)
801{
802 return insn | (((insn >> 21) & 0x1f) << 11);
803}
804
805static long
806extract_rbs(unsigned long insn, int *invalid)
807{
808 if (invalid != (int *) NULL
809 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
810 *invalid = 1;
811 return 0;
812}
813
814/* The SH field in an MD form instruction. This is split. */
815
816/*ARGSUSED*/
817static unsigned long
818insert_sh6(unsigned long insn, long value, const char **errmsg)
819{
820 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
821}
822
823/*ARGSUSED*/
824static long
825extract_sh6(unsigned long insn, int *invalid)
826{
827 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
828}
829
830/* The SPR field in an XFX form instruction. This is flipped--the
831 lower 5 bits are stored in the upper 5 and vice- versa. */
832
833static unsigned long
834insert_spr(unsigned long insn, long value, const char **errmsg)
835{
836 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
837}
838
839static long
840extract_spr(unsigned long insn, int *invalid)
841{
842 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
843}
844
845/* The TBR field in an XFX instruction. This is just like SPR, but it
846 is optional. When TBR is omitted, it must be inserted as 268 (the
847 magic number of the TB register). These functions treat 0
848 (indicating an omitted optional operand) as 268. This means that
849 ``mftb 4,0'' is not handled correctly. This does not matter very
850 much, since the architecture manual does not define mftb as
851 accepting any values other than 268 or 269. */
852
853#define TB (268)
854
855static unsigned long
856insert_tbr(unsigned long insn, long value, const char **errmsg)
857{
858 if (value == 0)
859 value = TB;
860 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
861}
862
863static long
864extract_tbr(unsigned long insn, int *invalid)
865{
866 long ret;
867
868 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
869 if (ret == TB)
870 ret = 0;
871 return ret;
872}
873
874/* Macros used to form opcodes. */
875
876/* The main opcode. */
877#define OP(x) (((x) & 0x3f) << 26)
878#define OP_MASK OP (0x3f)
879
880/* The main opcode combined with a trap code in the TO field of a D
881 form instruction. Used for extended mnemonics for the trap
882 instructions. */
883#define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21))
884#define OPTO_MASK (OP_MASK | TO_MASK)
885
886/* The main opcode combined with a comparison size bit in the L field
887 of a D form or X form instruction. Used for extended mnemonics for
888 the comparison instructions. */
889#define OPL(x,l) (OP (x) | (((l) & 1) << 21))
890#define OPL_MASK OPL (0x3f,1)
891
892/* An A form instruction. */
893#define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1))
894#define A_MASK A (0x3f, 0x1f, 1)
895
896/* An A_MASK with the FRB field fixed. */
897#define AFRB_MASK (A_MASK | FRB_MASK)
898
899/* An A_MASK with the FRC field fixed. */
900#define AFRC_MASK (A_MASK | FRC_MASK)
901
902/* An A_MASK with the FRA and FRC fields fixed. */
903#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
904
905/* A B form instruction. */
906#define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1))
907#define B_MASK B (0x3f, 1, 1)
908
909/* A B form instruction setting the BO field. */
910#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21))
911#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
912
913/* A BBO_MASK with the y bit of the BO field removed. This permits
914 matching a conditional branch regardless of the setting of the y
915 bit. */
916#define Y_MASK (1 << 21)
917#define BBOY_MASK (BBO_MASK &~ Y_MASK)
918
919/* A B form instruction setting the BO field and the condition bits of
920 the BI field. */
921#define BBOCB(op, bo, cb, aa, lk) \
922 (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16))
923#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
924
925/* A BBOCB_MASK with the y bit of the BO field removed. */
926#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
927
928/* A BBOYCB_MASK in which the BI field is fixed. */
929#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
930
931/* The main opcode mask with the RA field clear. */
932#define DRA_MASK (OP_MASK | RA_MASK)
933
934/* A DS form instruction. */
935#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
936#define DS_MASK DSO (0x3f, 3)
937
938/* An M form instruction. */
939#define M(op, rc) (OP (op) | ((rc) & 1))
940#define M_MASK M (0x3f, 1)
941
942/* An M form instruction with the ME field specified. */
943#define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))
944
945/* An M_MASK with the MB and ME fields fixed. */
946#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
947
948/* An M_MASK with the SH and ME fields fixed. */
949#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
950
951/* An MD form instruction. */
952#define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))
953#define MD_MASK MD (0x3f, 0x7, 1)
954
955/* An MD_MASK with the MB field fixed. */
956#define MDMB_MASK (MD_MASK | MB6_MASK)
957
958/* An MD_MASK with the SH field fixed. */
959#define MDSH_MASK (MD_MASK | SH6_MASK)
960
961/* An MDS form instruction. */
962#define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))
963#define MDS_MASK MDS (0x3f, 0xf, 1)
964
965/* An MDS_MASK with the MB field fixed. */
966#define MDSMB_MASK (MDS_MASK | MB6_MASK)
967
968/* An SC form instruction. */
969#define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))
970#define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)
971
972/* An X form instruction. */
973#define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
974
975/* An X form instruction with the RC bit specified. */
976#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
977
978/* The mask for an X form instruction. */
979#define X_MASK XRC (0x3f, 0x3ff, 1)
980
981/* An X_MASK with the RA field fixed. */
982#define XRA_MASK (X_MASK | RA_MASK)
983
984/* An X_MASK with the RB field fixed. */
985#define XRB_MASK (X_MASK | RB_MASK)
986
987/* An X_MASK with the RT field fixed. */
988#define XRT_MASK (X_MASK | RT_MASK)
989
990/* An X_MASK with the RA and RB fields fixed. */
991#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
992
993/* An X_MASK with the RT and RA fields fixed. */
994#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
995
996/* An X form comparison instruction. */
997#define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))
998
999/* The mask for an X form comparison instruction. */
1000#define XCMP_MASK (X_MASK | (1 << 22))
1001
1002/* The mask for an X form comparison instruction with the L field
1003 fixed. */
1004#define XCMPL_MASK (XCMP_MASK | (1 << 21))
1005
1006/* An X form trap instruction with the TO field specified. */
1007#define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))
1008#define XTO_MASK (X_MASK | TO_MASK)
1009
1010/* An XFL form instruction. */
1011#define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))
1012#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))
1013
1014/* An XL form instruction with the LK field set to 0. */
1015#define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))
1016
1017/* An XL form instruction which uses the LK field. */
1018#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1019
1020/* The mask for an XL form instruction. */
1021#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1022
1023/* An XL form instruction which explicitly sets the BO field. */
1024#define XLO(op, bo, xop, lk) \
1025 (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))
1026#define XLO_MASK (XL_MASK | BO_MASK)
1027
1028/* An XL form instruction which explicitly sets the y bit of the BO
1029 field. */
1030#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))
1031#define XLYLK_MASK (XL_MASK | Y_MASK)
1032
1033/* An XL form instruction which sets the BO field and the condition
1034 bits of the BI field. */
1035#define XLOCB(op, bo, cb, xop, lk) \
1036 (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))
1037#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1038
1039/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1040#define XLBB_MASK (XL_MASK | BB_MASK)
1041#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1042#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1043
1044/* An XL_MASK with the BO and BB fields fixed. */
1045#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1046
1047/* An XL_MASK with the BO, BI and BB fields fixed. */
1048#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1049
1050/* An XO form instruction. */
1051#define XO(op, xop, oe, rc) \
1052 (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))
1053#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1054
1055/* An XO_MASK with the RB field fixed. */
1056#define XORB_MASK (XO_MASK | RB_MASK)
1057
1058/* An XS form instruction. */
1059#define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))
1060#define XS_MASK XS (0x3f, 0x1ff, 1)
1061
1062/* A mask for the FXM version of an XFX form instruction. */
1063#define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))
1064
1065/* An XFX form instruction with the FXM field filled in. */
1066#define XFXM(op, xop, fxm) \
1067 (X ((op), (xop)) | (((fxm) & 0xff) << 12))
1068
1069/* An XFX form instruction with the SPR field filled in. */
1070#define XSPR(op, xop, spr) \
1071 (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))
1072#define XSPR_MASK (X_MASK | SPR_MASK)
1073
1074/* An XFX form instruction with the SPR field filled in except for the
1075 SPRBAT field. */
1076#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1077
1078/* An XFX form instruction with the SPR field filled in except for the
1079 SPRG field. */
1080#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1081
1082/* The BO encodings used in extended conditional branch mnemonics. */
1083#define BODNZF (0x0)
1084#define BODNZFP (0x1)
1085#define BODZF (0x2)
1086#define BODZFP (0x3)
1087#define BOF (0x4)
1088#define BOFP (0x5)
1089#define BODNZT (0x8)
1090#define BODNZTP (0x9)
1091#define BODZT (0xa)
1092#define BODZTP (0xb)
1093#define BOT (0xc)
1094#define BOTP (0xd)
1095#define BODNZ (0x10)
1096#define BODNZP (0x11)
1097#define BODZ (0x12)
1098#define BODZP (0x13)
1099#define BOU (0x14)
1100
1101/* The BI condition bit encodings used in extended conditional branch
1102 mnemonics. */
1103#define CBLT (0)
1104#define CBGT (1)
1105#define CBEQ (2)
1106#define CBSO (3)
1107
1108/* The TO encodings used in extended trap mnemonics. */
1109#define TOLGT (0x1)
1110#define TOLLT (0x2)
1111#define TOEQ (0x4)
1112#define TOLGE (0x5)
1113#define TOLNL (0x5)
1114#define TOLLE (0x6)
1115#define TOLNG (0x6)
1116#define TOGT (0x8)
1117#define TOGE (0xc)
1118#define TONL (0xc)
1119#define TOLT (0x10)
1120#define TOLE (0x14)
1121#define TONG (0x14)
1122#define TONE (0x18)
1123#define TOU (0x1f)
1124
1125/* Smaller names for the flags so each entry in the opcodes table will
1126 fit on a single line. */
1127#undef PPC
1128#define PPC PPC_OPCODE_PPC
1129#define POWER PPC_OPCODE_POWER
1130#define POWER2 PPC_OPCODE_POWER2
1131#define B32 PPC_OPCODE_32
1132#define B64 PPC_OPCODE_64
1133#define M601 PPC_OPCODE_601
1134
1135/* The opcode table.
1136
1137 The format of the opcode table is:
1138
1139 NAME OPCODE MASK FLAGS { OPERANDS }
1140
1141 NAME is the name of the instruction.
1142 OPCODE is the instruction opcode.
1143 MASK is the opcode mask; this is used to tell the disassembler
1144 which bits in the actual opcode must match OPCODE.
1145 FLAGS are flags indicated what processors support the instruction.
1146 OPERANDS is the list of operands.
1147
1148 The disassembler reads the table in order and prints the first
1149 instruction which matches, so this table is sorted to put more
1150 specific instructions before more general instructions. It is also
1151 sorted by major opcode. */
1152
1153const struct powerpc_opcode powerpc_opcodes[] = {
1154{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } },
1155{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } },
1156{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } },
1157{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } },
1158{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } },
1159{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } },
1160{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } },
1161{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } },
1162{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } },
1163{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } },
1164{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } },
1165{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } },
1166{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } },
1167{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } },
1168{ "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } },
1169
1170{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } },
1171{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } },
1172{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } },
1173{ "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } },
1174{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } },
1175{ "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } },
1176{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } },
1177{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } },
1178{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } },
1179{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } },
1180{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } },
1181{ "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } },
1182{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } },
1183{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } },
1184{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } },
1185{ "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } },
1186{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } },
1187{ "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } },
1188{ "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } },
1189{ "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } },
1190{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } },
1191{ "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } },
1192{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } },
1193{ "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } },
1194{ "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } },
1195{ "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } },
1196{ "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } },
1197{ "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } },
1198{ "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } },
1199{ "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } },
1200
1201{ "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } },
1202{ "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } },
1203
1204{ "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } },
1205{ "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } },
1206
1207{ "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } },
1208
1209{ "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } },
1210{ "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } },
1211{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
1212{ "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } },
1213
1214{ "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } },
1215{ "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } },
1216{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
1217{ "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } },
1218
1219{ "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } },
1220{ "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } },
1221{ "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } },
1222
1223{ "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } },
1224{ "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } },
1225{ "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } },
1226
1227{ "li", OP(14), DRA_MASK, PPC, { RT, SI } },
1228{ "lil", OP(14), DRA_MASK, POWER, { RT, SI } },
1229{ "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } },
1230{ "cal", OP(14), OP_MASK, POWER, { RT, D, RA } },
1231{ "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } },
1232{ "la", OP(14), OP_MASK, PPC, { RT, D, RA } },
1233
1234{ "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } },
1235{ "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } },
1236{ "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } },
1237{ "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } },
1238{ "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } },
1239
1240{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1241{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1242{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } },
1243{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } },
1244{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1245{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1246{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } },
1247{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } },
1248{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1249{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1250{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } },
1251{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } },
1252{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1253{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1254{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } },
1255{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } },
1256{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } },
1257{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } },
1258{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } },
1259{ "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } },
1260{ "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } },
1261{ "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } },
1262{ "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } },
1263{ "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } },
1264{ "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } },
1265{ "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } },
1266{ "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } },
1267{ "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } },
1268{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1269{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1270{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1271{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1272{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1273{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1274{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1275{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1276{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1277{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1278{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1279{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1280{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1281{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1282{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1283{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1284{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1285{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1286{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1287{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1288{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1289{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1290{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1291{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1292{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1293{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1294{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1295{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1296{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1297{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1298{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1299{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1300{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1301{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1302{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1303{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1304{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1305{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1306{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1307{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1308{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1309{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1310{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1311{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1312{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1313{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1314{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1315{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1316{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1317{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1318{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1319{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1320{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1321{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1322{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1323{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1324{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1325{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1326{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1327{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1328{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1329{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1330{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1331{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1332{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1333{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1334{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1335{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1336{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1337{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1338{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1339{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1340{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1341{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1342{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1343{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1344{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1345{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1346{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1347{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1348{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1349{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1350{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1351{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1352{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1353{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1354{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1355{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1356{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1357{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1358{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1359{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1360{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1361{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1362{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1363{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1364{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1365{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1366{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1367{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1368{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1369{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1370{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1371{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1372{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1373{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1374{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1375{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1376{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1377{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1378{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1379{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1380{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1381{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1382{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1383{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1384{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1385{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1386{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1387{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1388{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1389{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1390{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1391{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1392{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1393{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },
1394{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1395{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1396{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1397{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1398{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1399{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } },
1400{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } },
1401{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } },
1402{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } },
1403{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } },
1404{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } },
1405{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } },
1406{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } },
1407{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } },
1408{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } },
1409{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } },
1410{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } },
1411{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } },
1412{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1413{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1414{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1415{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1416{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1417{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1418{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1419{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1420{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1421{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1422{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1423{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1424{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1425{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1426{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1427{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1428{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1429{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1430{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1431{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1432{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1433{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1434{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1435{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1436{ "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1437{ "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1438{ "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } },
1439{ "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } },
1440{ "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1441{ "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1442{ "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } },
1443{ "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } },
1444{ "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1445{ "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1446{ "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1447{ "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } },
1448{ "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1449{ "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1450{ "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1451{ "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } },
1452{ "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1453{ "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1454{ "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } },
1455{ "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } },
1456{ "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1457{ "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1458{ "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } },
1459{ "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } },
1460{ "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1461{ "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1462{ "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1463{ "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } },
1464{ "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1465{ "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1466{ "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1467{ "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } },
1468{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } },
1469{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } },
1470{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } },
1471{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } },
1472{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } },
1473{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } },
1474{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1475{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1476{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } },
1477{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1478{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1479{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } },
1480{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } },
1481{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } },
1482{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } },
1483{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } },
1484{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } },
1485{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } },
1486{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } },
1487{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } },
1488{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } },
1489{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } },
1490{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } },
1491{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } },
1492{ "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } },
1493{ "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } },
1494{ "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } },
1495{ "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } },
1496{ "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } },
1497{ "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } },
1498{ "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } },
1499{ "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } },
1500{ "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } },
1501{ "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } },
1502{ "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } },
1503{ "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } },
1504
1505{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1506{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
1507{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
1508{ "svca", SC(17,1,0), SC_MASK, POWER, { SV } },
1509{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
1510
1511{ "b", B(18,0,0), B_MASK, PPC|POWER, { LI } },
1512{ "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } },
1513{ "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } },
1514{ "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } },
1515
1516{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
1517
1518{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1519{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } },
1520{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1521{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } },
1522{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1523{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1524{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1525{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1526{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1527{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1528{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1529{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1530{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } },
1531{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1532{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1533{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } },
1534{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1535{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1536{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1537{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1538{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1539{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1540{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1541{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1542{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1543{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1544{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1545{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1546{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1547{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1548{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1549{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1550{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1551{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1552{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1553{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1554{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1555{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1556{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1557{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1558{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1559{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1560{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1561{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1562{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1563{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1564{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1565{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1566{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1567{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1568{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1569{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1570{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1571{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1572{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1573{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1574{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1575{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1576{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1577{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1578{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1579{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1580{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1581{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1582{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1583{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1584{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1585{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1586{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1587{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1588{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1589{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1590{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1591{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1592{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1593{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1594{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1595{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1596{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1597{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1598{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1599{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } },
1600{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1601{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1602{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1603{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } },
1604{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1605{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1606{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1607{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } },
1608{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1609{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1610{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1611{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } },
1612{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1613{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1614{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1615{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } },
1616{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1617{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1618{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1619{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } },
1620{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1621{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1622{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1623{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1624{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1625{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1626{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1627{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } },
1628{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } },
1629{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } },
1630{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1631{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } },
1632{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } },
1633{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } },
1634{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1635{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } },
1636{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } },
1637{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } },
1638{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1639{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } },
1640{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } },
1641{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } },
1642{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1643{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } },
1644{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1645{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1646{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } },
1647{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1648{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1649{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } },
1650{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1651{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1652{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } },
1653{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1654{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1655{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } },
1656{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } },
1657{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1658{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } },
1659{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } },
1660{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1661{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } },
1662{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } },
1663{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1664{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } },
1665{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } },
1666{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } },
1667{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } },
1668{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1669{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1670{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1671{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1672{ "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } },
1673{ "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } },
1674
1675{ "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } },
1676{ "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } },
1677
1678{ "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } },
1679{ "rfci", XL(19,51), 0xffffffff, PPC, { 0 } },
1680
1681{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
1682
1683{ "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } },
1684
1685{ "isync", XL(19,150), 0xffffffff, PPC, { 0 } },
1686{ "ics", XL(19,150), 0xffffffff, POWER, { 0 } },
1687
1688{ "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } },
1689{ "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } },
1690
1691{ "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } },
1692
1693{ "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } },
1694
1695{ "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } },
1696{ "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } },
1697
1698{ "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } },
1699
1700{ "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } },
1701{ "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } },
1702
1703{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1704{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } },
1705{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1706{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1707{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1708{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1709{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1710{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1711{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1712{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1713{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1714{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1715{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1716{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1717{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1718{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1719{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1720{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1721{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1722{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1723{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1724{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1725{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1726{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1727{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1728{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1729{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1730{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1731{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1732{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1733{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1734{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1735{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1736{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1737{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1738{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1739{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1740{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1741{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1742{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1743{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1744{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1745{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1746{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1747{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1748{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1749{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1750{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1751{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1752{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1753{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1754{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1755{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } },
1756{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1757{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1758{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } },
1759{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1760{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1761{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } },
1762{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1763{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1764{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } },
1765{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1766{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1767{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1768{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1769{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1770{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1771{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1772{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1773{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } },
1774{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1775{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1776{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } },
1777{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1778{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } },
1779{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } },
1780{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1781{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } },
1782{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } },
1783{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1784{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } },
1785{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } },
1786{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1787{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } },
1788{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } },
1789{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } },
1790{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } },
1791{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } },
1792{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } },
1793{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } },
1794{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } },
1795{ "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } },
1796{ "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } },
1797
1798{ "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1799{ "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1800
1801{ "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1802{ "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1803
1804{ "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } },
1805{ "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } },
1806{ "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1807{ "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1808{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } },
1809{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } },
1810{ "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } },
1811{ "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } },
1812
1813{ "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
1814{ "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } },
1815
1816{ "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } },
1817{ "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
1818{ "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
1819{ "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } },
1820{ "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } },
1821{ "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } },
1822
1823{ "nop", OP(24), 0xffffffff, PPC, { 0 } },
1824{ "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } },
1825{ "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } },
1826
1827{ "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } },
1828{ "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } },
1829
1830{ "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } },
1831{ "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } },
1832
1833{ "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } },
1834{ "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } },
1835
1836{ "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } },
1837{ "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } },
1838
1839{ "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } },
1840{ "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } },
1841
1842{ "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1843{ "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1844{ "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1845{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } },
1846{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } },
1847{ "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1848
1849{ "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1850{ "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } },
1851
1852{ "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1853{ "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1854
1855{ "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1856{ "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } },
1857
1858{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1859{ "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1860{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } },
1861{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } },
1862
1863{ "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1864{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } },
1865
1866{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
1867{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
1868{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
1869{ "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } },
1870
1871{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } },
1872{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } },
1873{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } },
1874{ "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } },
1875{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } },
1876{ "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } },
1877{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } },
1878{ "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } },
1879{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } },
1880{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } },
1881{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } },
1882{ "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } },
1883{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } },
1884{ "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } },
1885{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } },
1886{ "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } },
1887{ "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } },
1888{ "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } },
1889{ "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } },
1890{ "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } },
1891{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } },
1892{ "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } },
1893{ "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } },
1894{ "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } },
1895{ "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } },
1896{ "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } },
1897{ "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } },
1898{ "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } },
1899{ "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } },
1900{ "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } },
1901{ "t", X(31,4), X_MASK, POWER, { TO, RA, RB } },
1902
1903{ "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } },
1904{ "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } },
1905{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
1906{ "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } },
1907{ "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } },
1908{ "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } },
1909{ "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } },
1910{ "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } },
1911{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
1912{ "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } },
1913{ "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } },
1914{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
1915
1916{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
1917{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
1918
1919{ "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } },
1920{ "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } },
1921{ "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } },
1922{ "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } },
1923{ "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } },
1924{ "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } },
1925{ "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } },
1926{ "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } },
1927
1928{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
1929{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
1930
1931{ "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } },
1932
1933{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
1934
1935{ "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } },
1936
1937{ "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } },
1938{ "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } },
1939
1940{ "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } },
1941{ "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } },
1942{ "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } },
1943{ "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } },
1944
1945{ "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } },
1946{ "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } },
1947{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } },
1948{ "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } },
1949
1950{ "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } },
1951{ "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } },
1952
1953{ "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } },
1954{ "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } },
1955
1956{ "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } },
1957{ "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } },
1958
1959{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } },
1960{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } },
1961{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
1962{ "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } },
1963
1964{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
1965{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
1966{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
1967{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
1968{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
1969{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
1970{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
1971{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
1972
1973{ "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } },
1974
1975{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
1976
1977{ "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } },
1978{ "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } },
1979
1980{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } },
1981{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } },
1982
1983{ "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } },
1984{ "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } },
1985
1986{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } },
1987{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } },
1988{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } },
1989{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } },
1990{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } },
1991{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } },
1992{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } },
1993{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } },
1994{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } },
1995{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } },
1996{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } },
1997{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } },
1998{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } },
1999{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } },
2000{ "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } },
2001
2002{ "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2003{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2004
2005{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2006{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2007
2008{ "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } },
2009
2010{ "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } },
2011
2012{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2013
2014{ "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } },
2015
2016{ "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } },
2017{ "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } },
2018{ "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } },
2019{ "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } },
2020
2021{ "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2022{ "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2023{ "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2024{ "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2025
2026{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
2027
2028{ "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } },
2029
2030{ "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2031{ "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2032{ "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2033{ "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2034
2035{ "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } },
2036{ "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } },
2037{ "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } },
2038{ "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } },
2039{ "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } },
2040{ "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } },
2041{ "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } },
2042{ "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } },
2043
2044{ "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } },
2045{ "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } },
2046{ "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } },
2047{ "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } },
2048{ "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } },
2049{ "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } },
2050{ "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } },
2051{ "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } },
2052
2053{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }},
2054{ "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } },
2055
2056{ "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } },
2057
2058{ "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } },
2059
2060{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2061
2062{ "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } },
2063{ "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } },
2064
2065{ "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } },
2066{ "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } },
2067
2068{ "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } },
2069{ "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } },
2070
2071{ "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } },
2072
2073{ "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } },
2074{ "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } },
2075
2076{ "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } },
2077{ "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } },
2078
2079{ "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } },
2080{ "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } },
2081{ "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } },
2082{ "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } },
2083{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } },
2084{ "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } },
2085{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } },
2086{ "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } },
2087
2088{ "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } },
2089{ "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } },
2090{ "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } },
2091{ "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } },
2092{ "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } },
2093{ "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } },
2094{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } },
2095{ "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } },
2096
2097{ "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } },
2098
2099{ "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } },
2100
2101{ "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } },
2102
2103{ "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } },
2104{ "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } },
2105
2106{ "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } },
2107{ "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } },
2108
2109{ "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } },
2110{ "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } },
2111{ "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } },
2112{ "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } },
2113{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } },
2114{ "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } },
2115{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } },
2116{ "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } },
2117
2118{ "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2119{ "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2120{ "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2121{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2122
2123{ "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } },
2124{ "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } },
2125{ "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } },
2126{ "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } },
2127{ "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } },
2128{ "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } },
2129{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } },
2130{ "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } },
2131
2132{ "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } },
2133{ "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } },
2134{ "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } },
2135{ "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } },
2136{ "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } },
2137{ "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } },
2138{ "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } },
2139{ "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } },
2140
2141{ "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } },
2142{ "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } },
2143
2144{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
2145
2146{ "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } },
2147
2148{ "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } },
2149{ "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } },
2150
2151{ "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2152{ "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2153{ "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2154{ "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2155
2156{ "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } },
2157{ "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } },
2158{ "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } },
2159{ "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } },
2160{ "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } },
2161{ "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } },
2162{ "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } },
2163{ "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } },
2164
2165{ "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } },
2166{ "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } },
2167
2168{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
2169
2170{ "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } },
2171
2172{ "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } },
2173
2174{ "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2175{ "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2176
2177{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
2178{ "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } },
2179
2180{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2181
2182{ "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } },
2183
2184{ "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2185{ "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2186
2187{ "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } },
2188
2189{ "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2190{ "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2191{ "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2192{ "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2193
2194{ "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } },
2195{ "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } },
2196{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } },
2197{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } },
2198{ "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } },
2199{ "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } },
2200{ "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } },
2201{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
2202{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } },
2203{ "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } },
2204{ "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } },
2205{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
2206{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } },
2207{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } },
2208{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } },
2209{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
2210{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } },
2211{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
2212{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
2213{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2214{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2215{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2216{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2217{ "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } },
2218
2219{ "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } },
2220
2221{ "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } },
2222
2223{ "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } },
2224
2225{ "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2226{ "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2227{ "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2228{ "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } },
2229
2230{ "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2231{ "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2232{ "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } },
2233{ "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } },
2234
2235{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2236
2237{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
2238{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2239
2240{ "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } },
2241
2242{ "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } },
2243
2244{ "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } },
2245
2246{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
2247
2248{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
2249
2250{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
2251
2252{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
2253
2254{ "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2255{ "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2256
2257{ "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2258{ "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } },
2259
2260{ "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } },
2261
2262{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2263
2264{ "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } },
2265
2266{ "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } },
2267{ "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2268{ "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } },
2269{ "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2270
2271{ "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } },
2272
2273{ "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2274{ "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2275{ "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2276{ "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2277
2278{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
2279{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
2280{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
2281{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
2282
2283{ "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } },
2284{ "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } },
2285{ "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } },
2286{ "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } },
2287{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
2288{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } },
2289{ "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } },
2290{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } },
2291{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } },
2292{ "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } },
2293{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
2294{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } },
2295{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } },
2296{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } },
2297{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
2298{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } },
2299{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
2300{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
2301{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
2302{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2303{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2304{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2305{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2306{ "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } },
2307
2308{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
2309
2310{ "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } },
2311{ "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } },
2312
2313{ "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } },
2314{ "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } },
2315{ "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } },
2316{ "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } },
2317
2318{ "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2319{ "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2320{ "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } },
2321{ "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } },
2322
2323{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
2324{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
2325{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
2326{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
2327
2328{ "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } },
2329
2330{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
2331
2332{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } },
2333
2334{ "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } },
2335
2336{ "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } },
2337{ "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } },
2338
2339{ "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } },
2340{ "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } },
2341
2342{ "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } },
2343
2344{ "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } },
2345{ "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } },
2346{ "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } },
2347{ "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } },
2348
2349{ "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } },
2350{ "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } },
2351
2352{ "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } },
2353{ "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } },
2354
2355{ "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } },
2356{ "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } },
2357
2358{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
2359
2360{ "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2361
2362{ "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } },
2363
2364{ "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } },
2365{ "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } },
2366
2367{ "sync", X(31,598), 0xffffffff, PPC, { 0 } },
2368{ "dcs", X(31,598), 0xffffffff, POWER, { 0 } },
2369
2370{ "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } },
2371
2372{ "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } },
2373
2374{ "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } },
2375
2376{ "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } },
2377
2378{ "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } },
2379
2380{ "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } },
2381{ "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } },
2382
2383{ "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } },
2384{ "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } },
2385
2386{ "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } },
2387
2388{ "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } },
2389{ "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } },
2390
2391{ "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } },
2392{ "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } },
2393
2394{ "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2395
2396{ "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } },
2397{ "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } },
2398
2399{ "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } },
2400{ "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } },
2401
2402{ "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } },
2403
2404{ "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } },
2405{ "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } },
2406
2407{ "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } },
2408{ "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } },
2409
2410{ "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } },
2411
2412{ "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } },
2413{ "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } },
2414
2415{ "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } },
2416
2417{ "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } },
2418{ "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } },
2419{ "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } },
2420{ "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } },
2421
2422{ "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } },
2423{ "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } },
2424
2425{ "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } },
2426
2427{ "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } },
2428{ "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } },
2429{ "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } },
2430{ "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } },
2431
2432{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
2433
2434{ "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } },
2435
2436{ "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } },
2437{ "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } },
2438
2439{ "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } },
2440{ "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } },
2441
2442{ "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } },
2443{ "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } },
2444{ "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } },
2445{ "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } },
2446
2447{ "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } },
2448{ "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } },
2449
2450{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
2451{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
2452
2453{ "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } },
2454
2455{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
2456
2457{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
2458
2459{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
2460{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
2461
2462{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2463{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
2464
2465{ "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } },
2466{ "l", OP(32), OP_MASK, POWER, { RT, D, RA } },
2467
2468{ "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } },
2469{ "lu", OP(33), OP_MASK, POWER, { RT, D, RA } },
2470
2471{ "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } },
2472
2473{ "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } },
2474
2475{ "stw", OP(36), OP_MASK, PPC, { RS, D, RA } },
2476{ "st", OP(36), OP_MASK, POWER, { RS, D, RA } },
2477
2478{ "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } },
2479{ "stu", OP(37), OP_MASK, POWER, { RS, D, RA } },
2480
2481{ "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } },
2482
2483{ "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } },
2484
2485{ "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } },
2486
2487{ "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } },
2488
2489{ "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } },
2490
2491{ "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } },
2492
2493{ "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } },
2494
2495{ "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } },
2496
2497{ "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } },
2498{ "lm", OP(46), OP_MASK, POWER, { RT, D, RA } },
2499
2500{ "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } },
2501{ "stm", OP(47), OP_MASK, POWER, { RS, D, RA } },
2502
2503{ "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } },
2504
2505{ "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } },
2506
2507{ "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } },
2508
2509{ "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } },
2510
2511{ "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } },
2512
2513{ "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } },
2514
2515{ "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } },
2516
2517{ "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } },
2518
2519{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
2520
2521{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
2522
2523{ "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } },
2524
2525{ "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } },
2526
2527{ "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } },
2528
2529{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2530{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2531
2532{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2533{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2534
2535{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2536{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2537
2538{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2539{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2540
2541{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2542{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2543
2544{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2545{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2546
2547{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2548{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2549
2550{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2551{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2552
2553{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2554{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2555
2556{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2557{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2558
2559{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
2560
2561{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
2562
2563{ "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } },
2564
2565{ "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } },
2566
2567{ "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2568
2569{ "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2570{ "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2571
2572{ "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } },
2573{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
2574{ "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } },
2575{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
2576
2577{ "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } },
2578{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
2579{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } },
2580{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
2581
2582{ "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2583{ "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2584{ "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2585{ "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2586
2587{ "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2588{ "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2589{ "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2590{ "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2591
2592{ "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2593{ "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2594{ "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
2595{ "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } },
2596
2597{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2598{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } },
2599
2600{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2601{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2602
2603{ "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2604{ "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2605{ "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
2606{ "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } },
2607
2608{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
2609{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
2610
2611{ "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2612{ "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2613{ "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2614{ "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2615
2616{ "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2617{ "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2618{ "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2619{ "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2620
2621{ "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2622{ "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2623{ "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2624{ "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2625
2626{ "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2627{ "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2628{ "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
2629{ "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } },
2630
2631{ "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } },
2632
2633{ "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } },
2634{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } },
2635
2636{ "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2637{ "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2638
2639{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } },
2640
2641{ "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } },
2642{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } },
2643
2644{ "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2645{ "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2646
2647{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2648{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } },
2649
2650{ "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2651{ "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2652
2653{ "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } },
2654{ "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } },
2655
2656{ "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } },
2657{ "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } },
2658
2659{ "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } },
2660{ "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } },
2661
2662{ "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2663{ "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2664
2665{ "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2666{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2667
2668{ "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } },
2669{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } },
2670
2671};
2672
2673const int powerpc_num_opcodes = ARRAY_SIZE(powerpc_opcodes);
2674
2675/* The macro table. This is only used by the assembler. */
2676
2677const struct powerpc_macro powerpc_macros[] = {
2678{ "extldi", 4, PPC|B64, "rldicr %0,%1,%3,(%2)-1" },
2679{ "extldi.", 4, PPC|B64, "rldicr. %0,%1,%3,(%2)-1" },
2680{ "extrdi", 4, PPC|B64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
2681{ "extrdi.", 4, PPC|B64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
2682{ "insrdi", 4, PPC|B64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
2683{ "insrdi.", 4, PPC|B64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
2684{ "rotrdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),0" },
2685{ "rotrdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),0" },
2686{ "sldi", 3, PPC|B64, "rldicr %0,%1,%2,63-(%2)" },
2687{ "sldi.", 3, PPC|B64, "rldicr. %0,%1,%2,63-(%2)" },
2688{ "srdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),%2" },
2689{ "srdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),%2" },
2690{ "clrrdi", 3, PPC|B64, "rldicr %0,%1,0,63-(%2)" },
2691{ "clrrdi.", 3, PPC|B64, "rldicr. %0,%1,0,63-(%2)" },
2692{ "clrlsldi",4, PPC|B64, "rldic %0,%1,%3,(%2)-(%3)" },
2693{ "clrlsldi.",4, PPC|B64, "rldic. %0,%1,%3,(%2)-(%3)" },
2694
2695{ "extlwi", 4, PPC, "rlwinm %0,%1,%3,0,(%2)-1" },
2696{ "extlwi.", 4, PPC, "rlwinm. %0,%1,%3,0,(%2)-1" },
2697{ "extrwi", 4, PPC, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
2698{ "extrwi.", 4, PPC, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
2699{ "inslwi", 4, PPC, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2700{ "inslwi.", 4, PPC, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" },
2701{ "insrwi", 4, PPC, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
2702{ "insrwi.", 4, PPC, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
2703{ "rotrwi", 3, PPC, "rlwinm %0,%1,32-(%2),0,31" },
2704{ "rotrwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),0,31" },
2705{ "slwi", 3, PPC, "rlwinm %0,%1,%2,0,31-(%2)" },
2706{ "sli", 3, POWER, "rlinm %0,%1,%2,0,31-(%2)" },
2707{ "slwi.", 3, PPC, "rlwinm. %0,%1,%2,0,31-(%2)" },
2708{ "sli.", 3, POWER, "rlinm. %0,%1,%2,0,31-(%2)" },
2709{ "srwi", 3, PPC, "rlwinm %0,%1,32-(%2),%2,31" },
2710{ "sri", 3, POWER, "rlinm %0,%1,32-(%2),%2,31" },
2711{ "srwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),%2,31" },
2712{ "sri.", 3, POWER, "rlinm. %0,%1,32-(%2),%2,31" },
2713{ "clrrwi", 3, PPC, "rlwinm %0,%1,0,0,31-(%2)" },
2714{ "clrrwi.", 3, PPC, "rlwinm. %0,%1,0,0,31-(%2)" },
2715{ "clrlslwi",4, PPC, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
2716{ "clrlslwi.",4, PPC, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
2717
2718};
2719
2720const int powerpc_num_macros = ARRAY_SIZE(powerpc_macros);
diff --git a/arch/ppc/xmon/ppc.h b/arch/ppc/xmon/ppc.h
deleted file mode 100644
index 2345ecba1fe9..000000000000
--- a/arch/ppc/xmon/ppc.h
+++ /dev/null
@@ -1,240 +0,0 @@
1/* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
101, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#ifndef PPC_H
22#define PPC_H
23
24/* The opcode table is an array of struct powerpc_opcode. */
25
26struct powerpc_opcode
27{
28 /* The opcode name. */
29 const char *name;
30
31 /* The opcode itself. Those bits which will be filled in with
32 operands are zeroes. */
33 unsigned long opcode;
34
35 /* The opcode mask. This is used by the disassembler. This is a
36 mask containing ones indicating those bits which must match the
37 opcode field, and zeroes indicating those bits which need not
38 match (and are presumably filled in by operands). */
39 unsigned long mask;
40
41 /* One bit flags for the opcode. These are used to indicate which
42 specific processors support the instructions. The defined values
43 are listed below. */
44 unsigned long flags;
45
46 /* An array of operand codes. Each code is an index into the
47 operand table. They appear in the order which the operands must
48 appear in assembly code, and are terminated by a zero. */
49 unsigned char operands[8];
50};
51
52/* The table itself is sorted by major opcode number, and is otherwise
53 in the order in which the disassembler should consider
54 instructions. */
55extern const struct powerpc_opcode powerpc_opcodes[];
56extern const int powerpc_num_opcodes;
57
58/* Values defined for the flags field of a struct powerpc_opcode. */
59
60/* Opcode is defined for the PowerPC architecture. */
61#define PPC_OPCODE_PPC (01)
62
63/* Opcode is defined for the POWER (RS/6000) architecture. */
64#define PPC_OPCODE_POWER (02)
65
66/* Opcode is defined for the POWER2 (Rios 2) architecture. */
67#define PPC_OPCODE_POWER2 (04)
68
69/* Opcode is only defined on 32 bit architectures. */
70#define PPC_OPCODE_32 (010)
71
72/* Opcode is only defined on 64 bit architectures. */
73#define PPC_OPCODE_64 (020)
74
75/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
76 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
77 but it also supports many additional POWER instructions. */
78#define PPC_OPCODE_601 (040)
79
80/* A macro to extract the major opcode from an instruction. */
81#define PPC_OP(i) (((i) >> 26) & 0x3f)
82
83/* The operands table is an array of struct powerpc_operand. */
84
85struct powerpc_operand
86{
87 /* The number of bits in the operand. */
88 int bits;
89
90 /* How far the operand is left shifted in the instruction. */
91 int shift;
92
93 /* Insertion function. This is used by the assembler. To insert an
94 operand value into an instruction, check this field.
95
96 If it is NULL, execute
97 i |= (op & ((1 << o->bits) - 1)) << o->shift;
98 (i is the instruction which we are filling in, o is a pointer to
99 this structure, and op is the opcode value; this assumes twos
100 complement arithmetic).
101
102 If this field is not NULL, then simply call it with the
103 instruction and the operand value. It will return the new value
104 of the instruction. If the ERRMSG argument is not NULL, then if
105 the operand value is illegal, *ERRMSG will be set to a warning
106 string (the operand will be inserted in any case). If the
107 operand value is legal, *ERRMSG will be unchanged (most operands
108 can accept any value). */
109 unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
110 const char **errmsg));
111
112 /* Extraction function. This is used by the disassembler. To
113 extract this operand type from an instruction, check this field.
114
115 If it is NULL, compute
116 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
117 if ((o->flags & PPC_OPERAND_SIGNED) != 0
118 && (op & (1 << (o->bits - 1))) != 0)
119 op -= 1 << o->bits;
120 (i is the instruction, o is a pointer to this structure, and op
121 is the result; this assumes twos complement arithmetic).
122
123 If this field is not NULL, then simply call it with the
124 instruction value. It will return the value of the operand. If
125 the INVALID argument is not NULL, *INVALID will be set to
126 non-zero if this operand type can not actually be extracted from
127 this operand (i.e., the instruction does not match). If the
128 operand is valid, *INVALID will not be changed. */
129 long (*extract) PARAMS ((unsigned long instruction, int *invalid));
130
131 /* One bit syntax flags. */
132 unsigned long flags;
133};
134
135/* Elements in the table are retrieved by indexing with values from
136 the operands field of the powerpc_opcodes table. */
137
138extern const struct powerpc_operand powerpc_operands[];
139
140/* Values defined for the flags field of a struct powerpc_operand. */
141
142/* This operand takes signed values. */
143#define PPC_OPERAND_SIGNED (01)
144
145/* This operand takes signed values, but also accepts a full positive
146 range of values when running in 32 bit mode. That is, if bits is
147 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
148 this flag is ignored. */
149#define PPC_OPERAND_SIGNOPT (02)
150
151/* This operand does not actually exist in the assembler input. This
152 is used to support extended mnemonics such as mr, for which two
153 operands fields are identical. The assembler should call the
154 insert function with any op value. The disassembler should call
155 the extract function, ignore the return value, and check the value
156 placed in the valid argument. */
157#define PPC_OPERAND_FAKE (04)
158
159/* The next operand should be wrapped in parentheses rather than
160 separated from this one by a comma. This is used for the load and
161 store instructions which want their operands to look like
162 reg,displacement(reg)
163 */
164#define PPC_OPERAND_PARENS (010)
165
166/* This operand may use the symbolic names for the CR fields, which
167 are
168 lt 0 gt 1 eq 2 so 3 un 3
169 cr0 0 cr1 1 cr2 2 cr3 3
170 cr4 4 cr5 5 cr6 6 cr7 7
171 These may be combined arithmetically, as in cr2*4+gt. These are
172 only supported on the PowerPC, not the POWER. */
173#define PPC_OPERAND_CR (020)
174
175/* This operand names a register. The disassembler uses this to print
176 register names with a leading 'r'. */
177#define PPC_OPERAND_GPR (040)
178
179/* This operand names a floating point register. The disassembler
180 prints these with a leading 'f'. */
181#define PPC_OPERAND_FPR (0100)
182
183/* This operand is a relative branch displacement. The disassembler
184 prints these symbolically if possible. */
185#define PPC_OPERAND_RELATIVE (0200)
186
187/* This operand is an absolute branch address. The disassembler
188 prints these symbolically if possible. */
189#define PPC_OPERAND_ABSOLUTE (0400)
190
191/* This operand is optional, and is zero if omitted. This is used for
192 the optional BF and L fields in the comparison instructions. The
193 assembler must count the number of operands remaining on the line,
194 and the number of operands remaining for the opcode, and decide
195 whether this operand is present or not. The disassembler should
196 print this operand out only if it is not zero. */
197#define PPC_OPERAND_OPTIONAL (01000)
198
199/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
200 is omitted, then for the next operand use this operand value plus
201 1, ignoring the next operand field for the opcode. This wretched
202 hack is needed because the Power rotate instructions can take
203 either 4 or 5 operands. The disassembler should print this operand
204 out regardless of the PPC_OPERAND_OPTIONAL field. */
205#define PPC_OPERAND_NEXT (02000)
206
207/* This operand should be regarded as a negative number for the
208 purposes of overflow checking (i.e., the normal most negative
209 number is disallowed and one more than the normal most positive
210 number is allowed). This flag will only be set for a signed
211 operand. */
212#define PPC_OPERAND_NEGATIVE (04000)
213
214/* The POWER and PowerPC assemblers use a few macros. We keep them
215 with the operands table for simplicity. The macro table is an
216 array of struct powerpc_macro. */
217
218struct powerpc_macro
219{
220 /* The macro name. */
221 const char *name;
222
223 /* The number of operands the macro takes. */
224 unsigned int operands;
225
226 /* One bit flags for the opcode. These are used to indicate which
227 specific processors support the instructions. The values are the
228 same as those for the struct powerpc_opcode flags field. */
229 unsigned long flags;
230
231 /* A format string to turn the macro into a normal instruction.
232 Each %N in the string is replaced with operand number N (zero
233 based). */
234 const char *format;
235};
236
237extern const struct powerpc_macro powerpc_macros[];
238extern const int powerpc_num_macros;
239
240#endif /* PPC_H */
diff --git a/arch/ppc/xmon/privinst.h b/arch/ppc/xmon/privinst.h
deleted file mode 100644
index c492a35687bd..000000000000
--- a/arch/ppc/xmon/privinst.h
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * Copyright (C) 1996 Paul Mackerras.
3 */
4
5#define GETREG(reg) \
6 static inline int get_ ## reg (void) \
7 { int ret; asm volatile ("mf" #reg " %0" : "=r" (ret) :); return ret; }
8
9#define SETREG(reg) \
10 static inline void set_ ## reg (int val) \
11 { asm volatile ("mt" #reg " %0" : : "r" (val)); }
12
13GETREG(msr)
14SETREG(msr)
15GETREG(cr)
16
17#define GSETSPR(n, name) \
18 static inline int get_ ## name (void) \
19 { int ret; asm volatile ("mfspr %0," #n : "=r" (ret) : ); return ret; } \
20 static inline void set_ ## name (int val) \
21 { asm volatile ("mtspr " #n ",%0" : : "r" (val)); }
22
23GSETSPR(0, mq)
24GSETSPR(1, xer)
25GSETSPR(4, rtcu)
26GSETSPR(5, rtcl)
27GSETSPR(8, lr)
28GSETSPR(9, ctr)
29GSETSPR(18, dsisr)
30GSETSPR(19, dar)
31GSETSPR(22, dec)
32GSETSPR(25, sdr1)
33GSETSPR(26, srr0)
34GSETSPR(27, srr1)
35GSETSPR(272, sprg0)
36GSETSPR(273, sprg1)
37GSETSPR(274, sprg2)
38GSETSPR(275, sprg3)
39GSETSPR(282, ear)
40GSETSPR(287, pvr)
41#ifndef CONFIG_8xx
42GSETSPR(528, bat0u)
43GSETSPR(529, bat0l)
44GSETSPR(530, bat1u)
45GSETSPR(531, bat1l)
46GSETSPR(532, bat2u)
47GSETSPR(533, bat2l)
48GSETSPR(534, bat3u)
49GSETSPR(535, bat3l)
50GSETSPR(1008, hid0)
51GSETSPR(1009, hid1)
52GSETSPR(1010, iabr)
53GSETSPR(1013, dabr)
54GSETSPR(1023, pir)
55#else
56GSETSPR(144, cmpa)
57GSETSPR(145, cmpb)
58GSETSPR(146, cmpc)
59GSETSPR(147, cmpd)
60GSETSPR(158, ictrl)
61#endif
62
63static inline int get_sr(int n)
64{
65 int ret;
66
67 asm (" mfsrin %0,%1" : "=r" (ret) : "r" (n << 28));
68 return ret;
69}
70
71static inline void set_sr(int n, int val)
72{
73 asm ("mtsrin %0,%1" : : "r" (val), "r" (n << 28));
74}
75
76static inline void store_inst(void *p)
77{
78 asm volatile ("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r" (p));
79}
80
81static inline void cflush(void *p)
82{
83 asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p));
84}
85
86static inline void cinval(void *p)
87{
88 asm volatile ("dcbi 0,%0; icbi 0,%0" : : "r" (p));
89}
90
diff --git a/arch/ppc/xmon/setjmp.c b/arch/ppc/xmon/setjmp.c
deleted file mode 100644
index 28352bac2ae6..000000000000
--- a/arch/ppc/xmon/setjmp.c
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (C) 1996 Paul Mackerras.
3 *
4 * NB this file must be compiled with -O2.
5 */
6
7int
8xmon_setjmp(long *buf)
9{
10 asm ("mflr 0; stw 0,0(%0);"
11 "stw 1,4(%0); stw 2,8(%0);"
12 "mfcr 0; stw 0,12(%0);"
13 "stmw 13,16(%0)"
14 : : "r" (buf));
15 /* XXX should save fp regs as well */
16 return 0;
17}
18
19void
20xmon_longjmp(long *buf, int val)
21{
22 if (val == 0)
23 val = 1;
24 asm ("lmw 13,16(%0);"
25 "lwz 0,12(%0); mtcrf 0x38,0;"
26 "lwz 0,0(%0); lwz 1,4(%0); lwz 2,8(%0);"
27 "mtlr 0; mr 3,%1"
28 : : "r" (buf), "r" (val));
29}
diff --git a/arch/ppc/xmon/start.c b/arch/ppc/xmon/start.c
deleted file mode 100644
index 9056fe58aaa1..000000000000
--- a/arch/ppc/xmon/start.c
+++ /dev/null
@@ -1,342 +0,0 @@
1/*
2 * Copyright (C) 1996 Paul Mackerras.
3 */
4#include <linux/string.h>
5#include <asm/machdep.h>
6#include <asm/io.h>
7#include <asm/page.h>
8#include <linux/kernel.h>
9#include <linux/errno.h>
10#include <linux/sysrq.h>
11#include <linux/bitops.h>
12#include <asm/xmon.h>
13#include <asm/errno.h>
14#include <asm/processor.h>
15#include <asm/delay.h>
16#include <asm/btext.h>
17#include <asm/ibm4xx.h>
18
19static volatile unsigned char *sccc, *sccd;
20unsigned int TXRDY, RXRDY, DLAB;
21static int xmon_expect(const char *str, unsigned int timeout);
22
23static int via_modem;
24
25#define TB_SPEED 25000000
26
27static inline unsigned int readtb(void)
28{
29 unsigned int ret;
30
31 asm volatile("mftb %0" : "=r" (ret) :);
32 return ret;
33}
34
35void buf_access(void)
36{
37 if (DLAB)
38 sccd[3] &= ~DLAB; /* reset DLAB */
39}
40
41
42#ifdef CONFIG_MAGIC_SYSRQ
43static void sysrq_handle_xmon(int key, struct pt_regs *regs,
44 struct tty_struct *tty)
45{
46 xmon(regs);
47}
48
49static struct sysrq_key_op sysrq_xmon_op =
50{
51 .handler = sysrq_handle_xmon,
52 .help_msg = "Xmon",
53 .action_msg = "Entering xmon",
54};
55#endif
56
57void
58xmon_map_scc(void)
59{
60#if defined(CONFIG_405GP)
61 sccd = (volatile unsigned char *)0xef600300;
62#elif defined(CONFIG_440EP)
63 sccd = (volatile unsigned char *) ioremap(PPC440EP_UART0_ADDR, 8);
64#elif defined(CONFIG_440SP)
65 sccd = (volatile unsigned char *) ioremap64(PPC440SP_UART0_ADDR, 8);
66#elif defined(CONFIG_440SPE)
67 sccd = (volatile unsigned char *) ioremap64(PPC440SPE_UART0_ADDR, 8);
68#elif defined(CONFIG_44x)
69 /* This is the default for 44x platforms. Any boards that have a
70 different UART address need to be put in cases before this or the
71 port will be mapped incorrectly */
72 sccd = (volatile unsigned char *) ioremap64(PPC440GP_UART0_ADDR, 8);
73#endif /* platform */
74
75#ifndef CONFIG_PPC_PREP
76 sccc = sccd + 5;
77 TXRDY = 0x20;
78 RXRDY = 1;
79 DLAB = 0x80;
80#endif
81
82 register_sysrq_key('x', &sysrq_xmon_op);
83}
84
85static int scc_initialized;
86
87void xmon_init_scc(void);
88
89int
90xmon_write(void *handle, void *ptr, int nb)
91{
92 char *p = ptr;
93 int i, c, ct;
94
95#ifdef CONFIG_SMP
96 static unsigned long xmon_write_lock;
97 int lock_wait = 1000000;
98 int locked;
99
100 while ((locked = test_and_set_bit(0, &xmon_write_lock)) != 0)
101 if (--lock_wait == 0)
102 break;
103#endif
104
105 if (!scc_initialized)
106 xmon_init_scc();
107 ct = 0;
108 for (i = 0; i < nb; ++i) {
109 while ((*sccc & TXRDY) == 0)
110 ;
111 c = p[i];
112 if (c == '\n' && !ct) {
113 c = '\r';
114 ct = 1;
115 --i;
116 } else {
117 ct = 0;
118 }
119 buf_access();
120 *sccd = c;
121 eieio();
122 }
123
124#ifdef CONFIG_SMP
125 if (!locked)
126 clear_bit(0, &xmon_write_lock);
127#endif
128 return nb;
129}
130
131int xmon_wants_key;
132
133
134int
135xmon_read(void *handle, void *ptr, int nb)
136{
137 char *p = ptr;
138 int i;
139
140 if (!scc_initialized)
141 xmon_init_scc();
142 for (i = 0; i < nb; ++i) {
143 while ((*sccc & RXRDY) == 0)
144 ;
145 buf_access();
146 *p++ = *sccd;
147 }
148 return i;
149}
150
151int
152xmon_read_poll(void)
153{
154 if ((*sccc & RXRDY) == 0) {
155 ;
156 return -1;
157 }
158 buf_access();
159 return *sccd;
160}
161
162void
163xmon_init_scc(void)
164{
165 scc_initialized = 1;
166 if (via_modem) {
167 for (;;) {
168 xmon_write(NULL, "ATE1V1\r", 7);
169 if (xmon_expect("OK", 5)) {
170 xmon_write(NULL, "ATA\r", 4);
171 if (xmon_expect("CONNECT", 40))
172 break;
173 }
174 xmon_write(NULL, "+++", 3);
175 xmon_expect("OK", 3);
176 }
177 }
178}
179
180
181void *xmon_stdin;
182void *xmon_stdout;
183void *xmon_stderr;
184
185void
186xmon_init(int arg)
187{
188 xmon_map_scc();
189}
190
191int
192xmon_putc(int c, void *f)
193{
194 char ch = c;
195
196 if (c == '\n')
197 xmon_putc('\r', f);
198 return xmon_write(f, &ch, 1) == 1? c: -1;
199}
200
201int
202xmon_putchar(int c)
203{
204 return xmon_putc(c, xmon_stdout);
205}
206
207int
208xmon_fputs(char *str, void *f)
209{
210 int n = strlen(str);
211
212 return xmon_write(f, str, n) == n? 0: -1;
213}
214
215int
216xmon_readchar(void)
217{
218 char ch;
219
220 for (;;) {
221 switch (xmon_read(xmon_stdin, &ch, 1)) {
222 case 1:
223 return ch;
224 case -1:
225 xmon_printf("read(stdin) returned -1\r\n", 0, 0);
226 return -1;
227 }
228 }
229}
230
231static char line[256];
232static char *lineptr;
233static int lineleft;
234
235int xmon_expect(const char *str, unsigned int timeout)
236{
237 int c;
238 unsigned int t0;
239
240 timeout *= TB_SPEED;
241 t0 = readtb();
242 do {
243 lineptr = line;
244 for (;;) {
245 c = xmon_read_poll();
246 if (c == -1) {
247 if (readtb() - t0 > timeout)
248 return 0;
249 continue;
250 }
251 if (c == '\n')
252 break;
253 if (c != '\r' && lineptr < &line[sizeof(line) - 1])
254 *lineptr++ = c;
255 }
256 *lineptr = 0;
257 } while (strstr(line, str) == NULL);
258 return 1;
259}
260
261int
262xmon_getchar(void)
263{
264 int c;
265
266 if (lineleft == 0) {
267 lineptr = line;
268 for (;;) {
269 c = xmon_readchar();
270 if (c == -1 || c == 4)
271 break;
272 if (c == '\r' || c == '\n') {
273 *lineptr++ = '\n';
274 xmon_putchar('\n');
275 break;
276 }
277 switch (c) {
278 case 0177:
279 case '\b':
280 if (lineptr > line) {
281 xmon_putchar('\b');
282 xmon_putchar(' ');
283 xmon_putchar('\b');
284 --lineptr;
285 }
286 break;
287 case 'U' & 0x1F:
288 while (lineptr > line) {
289 xmon_putchar('\b');
290 xmon_putchar(' ');
291 xmon_putchar('\b');
292 --lineptr;
293 }
294 break;
295 default:
296 if (lineptr >= &line[sizeof(line) - 1])
297 xmon_putchar('\a');
298 else {
299 xmon_putchar(c);
300 *lineptr++ = c;
301 }
302 }
303 }
304 lineleft = lineptr - line;
305 lineptr = line;
306 }
307 if (lineleft == 0)
308 return -1;
309 --lineleft;
310 return *lineptr++;
311}
312
313char *
314xmon_fgets(char *str, int nb, void *f)
315{
316 char *p;
317 int c;
318
319 for (p = str; p < str + nb - 1; ) {
320 c = xmon_getchar();
321 if (c == -1) {
322 if (p == str)
323 return NULL;
324 break;
325 }
326 *p++ = c;
327 if (c == '\n')
328 break;
329 }
330 *p = 0;
331 return str;
332}
333
334void
335xmon_enter(void)
336{
337}
338
339void
340xmon_leave(void)
341{
342}
diff --git a/arch/ppc/xmon/start_8xx.c b/arch/ppc/xmon/start_8xx.c
deleted file mode 100644
index 30974068c223..000000000000
--- a/arch/ppc/xmon/start_8xx.c
+++ /dev/null
@@ -1,287 +0,0 @@
1/*
2 * Copyright (C) 1996 Paul Mackerras.
3 * Copyright (C) 2000 Dan Malek.
4 * Quick hack of Paul's code to make XMON work on 8xx processors. Lots
5 * of assumptions, like the SMC1 is used, it has been initialized by the
6 * loader at some point, and we can just stuff and suck bytes.
7 * We rely upon the 8xx uart driver to support us, as the interface
8 * changes between boot up and operational phases of the kernel.
9 */
10#include <linux/string.h>
11#include <asm/machdep.h>
12#include <asm/io.h>
13#include <asm/page.h>
14#include <linux/kernel.h>
15#include <asm/8xx_immap.h>
16#include <asm/mpc8xx.h>
17#include <asm/cpm1.h>
18
19extern void xmon_printf(const char *fmt, ...);
20extern int xmon_8xx_write(char *str, int nb);
21extern int xmon_8xx_read_poll(void);
22extern int xmon_8xx_read_char(void);
23void prom_drawhex(uint);
24void prom_drawstring(const char *str);
25
26static int use_screen = 1; /* default */
27
28#define TB_SPEED 25000000
29
30static inline unsigned int readtb(void)
31{
32 unsigned int ret;
33
34 asm volatile("mftb %0" : "=r" (ret) :);
35 return ret;
36}
37
38void buf_access(void)
39{
40}
41
42void
43xmon_map_scc(void)
44{
45
46 cpmp = (cpm8xx_t *)&(((immap_t *)IMAP_ADDR)->im_cpm);
47 use_screen = 0;
48
49 prom_drawstring("xmon uses serial port\n");
50}
51
52static int scc_initialized = 0;
53
54void xmon_init_scc(void);
55
56int
57xmon_write(void *handle, void *ptr, int nb)
58{
59 char *p = ptr;
60 int i, c, ct;
61
62 if (!scc_initialized)
63 xmon_init_scc();
64
65 return(xmon_8xx_write(ptr, nb));
66}
67
68int xmon_wants_key;
69
70int
71xmon_read(void *handle, void *ptr, int nb)
72{
73 char *p = ptr;
74 int i;
75
76 if (!scc_initialized)
77 xmon_init_scc();
78
79 for (i = 0; i < nb; ++i) {
80 *p++ = xmon_8xx_read_char();
81 }
82 return i;
83}
84
85int
86xmon_read_poll(void)
87{
88 return(xmon_8xx_read_poll());
89}
90
91void
92xmon_init_scc()
93{
94 scc_initialized = 1;
95}
96
97#if 0
98extern int (*prom_entry)(void *);
99
100int
101xmon_exit(void)
102{
103 struct prom_args {
104 char *service;
105 } args;
106
107 for (;;) {
108 args.service = "exit";
109 (*prom_entry)(&args);
110 }
111}
112#endif
113
114void *xmon_stdin;
115void *xmon_stdout;
116void *xmon_stderr;
117
118void
119xmon_init(void)
120{
121}
122
123int
124xmon_putc(int c, void *f)
125{
126 char ch = c;
127
128 if (c == '\n')
129 xmon_putc('\r', f);
130 return xmon_write(f, &ch, 1) == 1? c: -1;
131}
132
133int
134xmon_putchar(int c)
135{
136 return xmon_putc(c, xmon_stdout);
137}
138
139int
140xmon_fputs(char *str, void *f)
141{
142 int n = strlen(str);
143
144 return xmon_write(f, str, n) == n? 0: -1;
145}
146
147int
148xmon_readchar(void)
149{
150 char ch;
151
152 for (;;) {
153 switch (xmon_read(xmon_stdin, &ch, 1)) {
154 case 1:
155 return ch;
156 case -1:
157 xmon_printf("read(stdin) returned -1\r\n", 0, 0);
158 return -1;
159 }
160 }
161}
162
163static char line[256];
164static char *lineptr;
165static int lineleft;
166
167#if 0
168int xmon_expect(const char *str, unsigned int timeout)
169{
170 int c;
171 unsigned int t0;
172
173 timeout *= TB_SPEED;
174 t0 = readtb();
175 do {
176 lineptr = line;
177 for (;;) {
178 c = xmon_read_poll();
179 if (c == -1) {
180 if (readtb() - t0 > timeout)
181 return 0;
182 continue;
183 }
184 if (c == '\n')
185 break;
186 if (c != '\r' && lineptr < &line[sizeof(line) - 1])
187 *lineptr++ = c;
188 }
189 *lineptr = 0;
190 } while (strstr(line, str) == NULL);
191 return 1;
192}
193#endif
194
195int
196xmon_getchar(void)
197{
198 int c;
199
200 if (lineleft == 0) {
201 lineptr = line;
202 for (;;) {
203 c = xmon_readchar();
204 if (c == -1 || c == 4)
205 break;
206 if (c == '\r' || c == '\n') {
207 *lineptr++ = '\n';
208 xmon_putchar('\n');
209 break;
210 }
211 switch (c) {
212 case 0177:
213 case '\b':
214 if (lineptr > line) {
215 xmon_putchar('\b');
216 xmon_putchar(' ');
217 xmon_putchar('\b');
218 --lineptr;
219 }
220 break;
221 case 'U' & 0x1F:
222 while (lineptr > line) {
223 xmon_putchar('\b');
224 xmon_putchar(' ');
225 xmon_putchar('\b');
226 --lineptr;
227 }
228 break;
229 default:
230 if (lineptr >= &line[sizeof(line) - 1])
231 xmon_putchar('\a');
232 else {
233 xmon_putchar(c);
234 *lineptr++ = c;
235 }
236 }
237 }
238 lineleft = lineptr - line;
239 lineptr = line;
240 }
241 if (lineleft == 0)
242 return -1;
243 --lineleft;
244 return *lineptr++;
245}
246
247char *
248xmon_fgets(char *str, int nb, void *f)
249{
250 char *p;
251 int c;
252
253 for (p = str; p < str + nb - 1; ) {
254 c = xmon_getchar();
255 if (c == -1) {
256 if (p == str)
257 return 0;
258 break;
259 }
260 *p++ = c;
261 if (c == '\n')
262 break;
263 }
264 *p = 0;
265 return str;
266}
267
268void
269prom_drawhex(uint val)
270{
271 unsigned char buf[10];
272
273 int i;
274 for (i = 7; i >= 0; i--)
275 {
276 buf[i] = "0123456789abcdef"[val & 0x0f];
277 val >>= 4;
278 }
279 buf[8] = '\0';
280 xmon_fputs(buf, xmon_stdout);
281}
282
283void
284prom_drawstring(const char *str)
285{
286 xmon_fputs(str, xmon_stdout);
287}
diff --git a/arch/ppc/xmon/subr_prf.c b/arch/ppc/xmon/subr_prf.c
deleted file mode 100644
index 126624f3f2ed..000000000000
--- a/arch/ppc/xmon/subr_prf.c
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Written by Cort Dougan to replace the version originally used
3 * by Paul Mackerras, which came from NetBSD and thus had copyright
4 * conflicts with Linux.
5 *
6 * This file makes liberal use of the standard linux utility
7 * routines to reduce the size of the binary. We assume we can
8 * trust some parts of Linux inside the debugger.
9 * -- Cort (cort@cs.nmt.edu)
10 *
11 * Copyright (C) 1999 Cort Dougan.
12 */
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <stdarg.h>
17#include "nonstdio.h"
18
19extern int xmon_write(void *, void *, int);
20
21void
22xmon_vfprintf(void *f, const char *fmt, va_list ap)
23{
24 static char xmon_buf[2048];
25 int n;
26
27 n = vsprintf(xmon_buf, fmt, ap);
28 xmon_write(f, xmon_buf, n);
29}
30
31void
32xmon_printf(const char *fmt, ...)
33{
34 va_list ap;
35
36 va_start(ap, fmt);
37 xmon_vfprintf(stdout, fmt, ap);
38 va_end(ap);
39}
40
41void
42xmon_fprintf(void *f, const char *fmt, ...)
43{
44 va_list ap;
45
46 va_start(ap, fmt);
47 xmon_vfprintf(f, fmt, ap);
48 va_end(ap);
49}
50
51void
52xmon_puts(char *s)
53{
54 xmon_write(stdout, s, strlen(s));
55}
diff --git a/arch/ppc/xmon/xmon.c b/arch/ppc/xmon/xmon.c
deleted file mode 100644
index b1a91744fd2d..000000000000
--- a/arch/ppc/xmon/xmon.c
+++ /dev/null
@@ -1,1780 +0,0 @@
1/*
2 * Routines providing a simple monitor for use on the PowerMac.
3 *
4 * Copyright (C) 1996 Paul Mackerras.
5 */
6#include <linux/errno.h>
7#include <linux/sched.h>
8#include <linux/smp.h>
9#include <linux/interrupt.h>
10#include <linux/bitops.h>
11#include <linux/kallsyms.h>
12#include <asm/ptrace.h>
13#include <asm/string.h>
14#include <asm/machdep.h>
15#include <asm/xmon.h>
16#include "nonstdio.h"
17#include "privinst.h"
18
19#define scanhex xmon_scanhex
20#define skipbl xmon_skipbl
21
22#ifdef CONFIG_SMP
23static unsigned long cpus_in_xmon = 0;
24static unsigned long got_xmon = 0;
25static volatile int take_xmon = -1;
26#endif /* CONFIG_SMP */
27
28static unsigned adrs;
29static int size = 1;
30static unsigned ndump = 64;
31static unsigned nidump = 16;
32static unsigned ncsum = 4096;
33static int termch;
34
35static u_int bus_error_jmp[100];
36#define setjmp xmon_setjmp
37#define longjmp xmon_longjmp
38
39/* Breakpoint stuff */
40struct bpt {
41 unsigned address;
42 unsigned instr;
43 unsigned count;
44 unsigned char enabled;
45};
46
47#define NBPTS 16
48static struct bpt bpts[NBPTS];
49static struct bpt dabr;
50static struct bpt iabr;
51static unsigned bpinstr = 0x7fe00008; /* trap */
52
53/* Prototypes */
54extern void (*debugger_fault_handler)(struct pt_regs *);
55static int cmds(struct pt_regs *);
56static int mread(unsigned, void *, int);
57static int mwrite(unsigned, void *, int);
58static void handle_fault(struct pt_regs *);
59static void byterev(unsigned char *, int);
60static void memex(void);
61static int bsesc(void);
62static void dump(void);
63static void prdump(unsigned, int);
64#ifdef __MWERKS__
65static void prndump(unsigned, int);
66static int nvreadb(unsigned);
67#endif
68static int ppc_inst_dump(unsigned, int);
69void print_address(unsigned);
70static int getsp(void);
71static void dump_hash_table(void);
72static void backtrace(struct pt_regs *);
73static void excprint(struct pt_regs *);
74static void prregs(struct pt_regs *);
75static void memops(int);
76static void memlocate(void);
77static void memzcan(void);
78static void memdiffs(unsigned char *, unsigned char *, unsigned, unsigned);
79int skipbl(void);
80int scanhex(unsigned *valp);
81static void scannl(void);
82static int hexdigit(int);
83void getstring(char *, int);
84static void flush_input(void);
85static int inchar(void);
86static void take_input(char *);
87/* static void openforth(void); */
88static unsigned read_spr(int);
89static void write_spr(int, unsigned);
90static void super_regs(void);
91static void symbol_lookup(void);
92static void remove_bpts(void);
93static void insert_bpts(void);
94static struct bpt *at_breakpoint(unsigned pc);
95static void bpt_cmds(void);
96void cacheflush(void);
97#ifdef CONFIG_SMP
98static void cpu_cmd(void);
99#endif /* CONFIG_SMP */
100static void csum(void);
101static void bootcmds(void);
102static void proccall(void);
103static void printtime(void);
104
105extern int print_insn_big_powerpc(FILE *, unsigned long, unsigned);
106extern void printf(const char *fmt, ...);
107extern int putchar(int ch);
108extern int setjmp(u_int *);
109extern void longjmp(u_int *, int);
110
111extern void xmon_enter(void);
112extern void xmon_leave(void);
113
114static unsigned start_tb[NR_CPUS][2];
115static unsigned stop_tb[NR_CPUS][2];
116
117#define GETWORD(v) (((v)[0] << 24) + ((v)[1] << 16) + ((v)[2] << 8) + (v)[3])
118
119#define isxdigit(c) (('0' <= (c) && (c) <= '9') \
120 || ('a' <= (c) && (c) <= 'f') \
121 || ('A' <= (c) && (c) <= 'F'))
122#define isalnum(c) (('0' <= (c) && (c) <= '9') \
123 || ('a' <= (c) && (c) <= 'z') \
124 || ('A' <= (c) && (c) <= 'Z'))
125#define isspace(c) (c == ' ' || c == '\t' || c == 10 || c == 13 || c == 0)
126
127static char *help_string = "\
128Commands:\n\
129 d dump bytes\n\
130 di dump instructions\n\
131 df dump float values\n\
132 dd dump double values\n\
133 e print exception information\n\
134 h dump hash table\n\
135 m examine/change memory\n\
136 mm move a block of memory\n\
137 ms set a block of memory\n\
138 md compare two blocks of memory\n\
139 r print registers\n\
140 S print special registers\n\
141 t print backtrace\n\
142 la lookup address\n\
143 ls lookup symbol\n\
144 C checksum\n\
145 p call function with arguments\n\
146 T print time\n\
147 x exit monitor\n\
148 zr reboot\n\
149 zh halt\n\
150";
151
152static int xmon_trace[NR_CPUS];
153#define SSTEP 1 /* stepping because of 's' command */
154#define BRSTEP 2 /* stepping over breakpoint */
155
156#ifdef CONFIG_4xx
157#define MSR_SSTEP_ENABLE 0x200
158#else
159#define MSR_SSTEP_ENABLE 0x400
160#endif
161
162static struct pt_regs *xmon_regs[NR_CPUS];
163
164extern inline void sync(void)
165{
166 asm volatile("sync; isync");
167}
168
169extern inline void __delay(unsigned int loops)
170{
171 if (loops != 0)
172 __asm__ __volatile__("mtctr %0; 1: bdnz 1b" : :
173 "r" (loops) : "ctr");
174}
175
176/* Print an address in numeric and symbolic form (if possible) */
177static void xmon_print_symbol(unsigned long address, const char *mid,
178 const char *after)
179{
180 char *modname;
181 const char *name = NULL;
182 unsigned long offset, size;
183 static char tmpstr[128];
184
185 printf("%.8lx", address);
186 if (setjmp(bus_error_jmp) == 0) {
187 debugger_fault_handler = handle_fault;
188 sync();
189 name = kallsyms_lookup(address, &size, &offset, &modname,
190 tmpstr);
191 sync();
192 /* wait a little while to see if we get a machine check */
193 __delay(200);
194 }
195 debugger_fault_handler = NULL;
196
197 if (name) {
198 printf("%s%s+%#lx/%#lx", mid, name, offset, size);
199 if (modname)
200 printf(" [%s]", modname);
201 }
202 printf("%s", after);
203}
204
205static void get_tb(unsigned *p)
206{
207 unsigned hi, lo, hiagain;
208
209 if ((get_pvr() >> 16) == 1)
210 return;
211
212 do {
213 asm volatile("mftbu %0; mftb %1; mftbu %2"
214 : "=r" (hi), "=r" (lo), "=r" (hiagain));
215 } while (hi != hiagain);
216 p[0] = hi;
217 p[1] = lo;
218}
219
220static inline void xmon_enable_sstep(struct pt_regs *regs)
221{
222 regs->msr |= MSR_SSTEP_ENABLE;
223#ifdef CONFIG_4xx
224 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
225#endif
226}
227
228int xmon(struct pt_regs *excp)
229{
230 struct pt_regs regs;
231 int msr, cmd;
232
233 get_tb(stop_tb[smp_processor_id()]);
234 if (excp == NULL) {
235 asm volatile ("stw 0,0(%0)\n\
236 lwz 0,0(1)\n\
237 stw 0,4(%0)\n\
238 stmw 2,8(%0)" : : "b" (&regs));
239 regs.nip = regs.link = ((unsigned long *)regs.gpr[1])[1];
240 regs.msr = get_msr();
241 regs.ctr = get_ctr();
242 regs.xer = get_xer();
243 regs.ccr = get_cr();
244 regs.trap = 0;
245 excp = &regs;
246 }
247
248 msr = get_msr();
249 set_msr(msr & ~0x8000); /* disable interrupts */
250 xmon_regs[smp_processor_id()] = excp;
251 xmon_enter();
252 excprint(excp);
253#ifdef CONFIG_SMP
254 if (test_and_set_bit(smp_processor_id(), &cpus_in_xmon))
255 for (;;)
256 ;
257 while (test_and_set_bit(0, &got_xmon)) {
258 if (take_xmon == smp_processor_id()) {
259 take_xmon = -1;
260 break;
261 }
262 }
263 /*
264 * XXX: breakpoints are removed while any cpu is in xmon
265 */
266#endif /* CONFIG_SMP */
267 remove_bpts();
268 cmd = cmds(excp);
269 if (cmd == 's') {
270 xmon_trace[smp_processor_id()] = SSTEP;
271 xmon_enable_sstep(excp);
272 } else if (at_breakpoint(excp->nip)) {
273 xmon_trace[smp_processor_id()] = BRSTEP;
274 xmon_enable_sstep(excp);
275 } else {
276 xmon_trace[smp_processor_id()] = 0;
277 insert_bpts();
278 }
279 xmon_leave();
280 xmon_regs[smp_processor_id()] = NULL;
281#ifdef CONFIG_SMP
282 clear_bit(0, &got_xmon);
283 clear_bit(smp_processor_id(), &cpus_in_xmon);
284#endif /* CONFIG_SMP */
285 set_msr(msr); /* restore interrupt enable */
286 get_tb(start_tb[smp_processor_id()]);
287
288 return cmd != 'X';
289}
290
291irqreturn_t
292xmon_irq(int irq, void *d, struct pt_regs *regs)
293{
294 unsigned long flags;
295 local_irq_save(flags);
296 printf("Keyboard interrupt\n");
297 xmon(regs);
298 local_irq_restore(flags);
299 return IRQ_HANDLED;
300}
301
302int
303xmon_bpt(struct pt_regs *regs)
304{
305 struct bpt *bp;
306
307 bp = at_breakpoint(regs->nip);
308 if (!bp)
309 return 0;
310 if (bp->count) {
311 --bp->count;
312 remove_bpts();
313 excprint(regs);
314 xmon_trace[smp_processor_id()] = BRSTEP;
315 xmon_enable_sstep(regs);
316 } else {
317 xmon(regs);
318 }
319 return 1;
320}
321
322int
323xmon_sstep(struct pt_regs *regs)
324{
325 if (!xmon_trace[smp_processor_id()])
326 return 0;
327 if (xmon_trace[smp_processor_id()] == BRSTEP) {
328 xmon_trace[smp_processor_id()] = 0;
329 insert_bpts();
330 } else {
331 xmon(regs);
332 }
333 return 1;
334}
335
336int
337xmon_dabr_match(struct pt_regs *regs)
338{
339 if (dabr.enabled && dabr.count) {
340 --dabr.count;
341 remove_bpts();
342 excprint(regs);
343 xmon_trace[smp_processor_id()] = BRSTEP;
344 regs->msr |= 0x400;
345 } else {
346 dabr.instr = regs->nip;
347 xmon(regs);
348 }
349 return 1;
350}
351
352int
353xmon_iabr_match(struct pt_regs *regs)
354{
355 if (iabr.enabled && iabr.count) {
356 --iabr.count;
357 remove_bpts();
358 excprint(regs);
359 xmon_trace[smp_processor_id()] = BRSTEP;
360 regs->msr |= 0x400;
361 } else {
362 xmon(regs);
363 }
364 return 1;
365}
366
367static struct bpt *
368at_breakpoint(unsigned pc)
369{
370 int i;
371 struct bpt *bp;
372
373 if (dabr.enabled && pc == dabr.instr)
374 return &dabr;
375 if (iabr.enabled && pc == iabr.address)
376 return &iabr;
377 bp = bpts;
378 for (i = 0; i < NBPTS; ++i, ++bp)
379 if (bp->enabled && pc == bp->address)
380 return bp;
381 return NULL;
382}
383
384static void
385insert_bpts(void)
386{
387 int i;
388 struct bpt *bp;
389
390 bp = bpts;
391 for (i = 0; i < NBPTS; ++i, ++bp) {
392 if (!bp->enabled)
393 continue;
394 if (mread(bp->address, &bp->instr, 4) != 4
395 || mwrite(bp->address, &bpinstr, 4) != 4) {
396 printf("Couldn't insert breakpoint at %x, disabling\n",
397 bp->address);
398 bp->enabled = 0;
399 }
400 store_inst((void *) bp->address);
401 }
402#if ! (defined(CONFIG_8xx) || defined(CONFIG_4xx))
403 if (dabr.enabled)
404 set_dabr(dabr.address);
405 if (iabr.enabled)
406 set_iabr(iabr.address);
407#endif
408}
409
410static void
411remove_bpts(void)
412{
413 int i;
414 struct bpt *bp;
415 unsigned instr;
416
417#if ! (defined(CONFIG_8xx) || defined(CONFIG_4xx))
418 set_dabr(0);
419 set_iabr(0);
420#endif
421 bp = bpts;
422 for (i = 0; i < NBPTS; ++i, ++bp) {
423 if (!bp->enabled)
424 continue;
425 if (mread(bp->address, &instr, 4) == 4
426 && instr == bpinstr
427 && mwrite(bp->address, &bp->instr, 4) != 4)
428 printf("Couldn't remove breakpoint at %x\n",
429 bp->address);
430 store_inst((void *) bp->address);
431 }
432}
433
434static char *last_cmd;
435
436/* Command interpreting routine */
437static int
438cmds(struct pt_regs *excp)
439{
440 int cmd;
441
442 last_cmd = NULL;
443 for(;;) {
444#ifdef CONFIG_SMP
445 printf("%d:", smp_processor_id());
446#endif /* CONFIG_SMP */
447 printf("mon> ");
448 fflush(stdout);
449 flush_input();
450 termch = 0;
451 cmd = skipbl();
452 if( cmd == '\n' ) {
453 if (last_cmd == NULL)
454 continue;
455 take_input(last_cmd);
456 last_cmd = NULL;
457 cmd = inchar();
458 }
459 switch (cmd) {
460 case 'm':
461 cmd = inchar();
462 switch (cmd) {
463 case 'm':
464 case 's':
465 case 'd':
466 memops(cmd);
467 break;
468 case 'l':
469 memlocate();
470 break;
471 case 'z':
472 memzcan();
473 break;
474 default:
475 termch = cmd;
476 memex();
477 }
478 break;
479 case 'd':
480 dump();
481 break;
482 case 'l':
483 symbol_lookup();
484 break;
485 case 'r':
486 if (excp != NULL)
487 prregs(excp); /* print regs */
488 break;
489 case 'e':
490 if (excp == NULL)
491 printf("No exception information\n");
492 else
493 excprint(excp);
494 break;
495 case 'S':
496 super_regs();
497 break;
498 case 't':
499 backtrace(excp);
500 break;
501 case 'f':
502 cacheflush();
503 break;
504 case 'h':
505 dump_hash_table();
506 break;
507 case 's':
508 case 'x':
509 case EOF:
510 return cmd;
511 case '?':
512 printf(help_string);
513 break;
514 default:
515 printf("Unrecognized command: ");
516 if( ' ' < cmd && cmd <= '~' )
517 putchar(cmd);
518 else
519 printf("\\x%x", cmd);
520 printf(" (type ? for help)\n");
521 break;
522 case 'b':
523 bpt_cmds();
524 break;
525 case 'C':
526 csum();
527 break;
528#ifdef CONFIG_SMP
529 case 'c':
530 cpu_cmd();
531 break;
532#endif /* CONFIG_SMP */
533 case 'z':
534 bootcmds();
535 break;
536 case 'p':
537 proccall();
538 break;
539 case 'T':
540 printtime();
541 break;
542 }
543 }
544}
545
546extern unsigned tb_to_us;
547
548#define mulhwu(x,y) \
549({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
550
551static void printtime(void)
552{
553 unsigned int delta;
554
555 delta = stop_tb[smp_processor_id()][1]
556 - start_tb[smp_processor_id()][1];
557 delta = mulhwu(tb_to_us, delta);
558 printf("%u.%06u seconds\n", delta / 1000000, delta % 1000000);
559}
560
561static void bootcmds(void)
562{
563 int cmd;
564
565 cmd = inchar();
566 if (cmd == 'r')
567 ppc_md.restart(NULL);
568 else if (cmd == 'h')
569 ppc_md.halt();
570 else if (cmd == 'p')
571 ppc_md.power_off();
572}
573
574#ifdef CONFIG_SMP
575static void cpu_cmd(void)
576{
577 unsigned cpu;
578 int timeout;
579 int cmd;
580
581 cmd = inchar();
582 if (cmd == 'i') {
583 /* interrupt other cpu(s) */
584 cpu = MSG_ALL_BUT_SELF;
585 if (scanhex(&cpu))
586 smp_send_xmon_break(cpu);
587 return;
588 }
589 termch = cmd;
590 if (!scanhex(&cpu)) {
591 /* print cpus waiting or in xmon */
592 printf("cpus stopped:");
593 for (cpu = 0; cpu < NR_CPUS; ++cpu) {
594 if (test_bit(cpu, &cpus_in_xmon)) {
595 printf(" %d", cpu);
596 if (cpu == smp_processor_id())
597 printf("*", cpu);
598 }
599 }
600 printf("\n");
601 return;
602 }
603 /* try to switch to cpu specified */
604 take_xmon = cpu;
605 timeout = 10000000;
606 while (take_xmon >= 0) {
607 if (--timeout == 0) {
608 /* yes there's a race here */
609 take_xmon = -1;
610 printf("cpu %u didn't take control\n", cpu);
611 return;
612 }
613 }
614 /* now have to wait to be given control back */
615 while (test_and_set_bit(0, &got_xmon)) {
616 if (take_xmon == smp_processor_id()) {
617 take_xmon = -1;
618 break;
619 }
620 }
621}
622#endif /* CONFIG_SMP */
623
624
625static unsigned short fcstab[256] = {
626 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
627 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
628 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
629 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
630 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
631 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
632 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
633 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
634 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
635 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
636 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
637 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
638 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
639 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
640 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
641 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
642 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
643 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
644 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
645 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
646 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
647 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
648 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
649 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
650 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
651 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
652 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
653 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
654 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
655 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
656 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
657 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
658};
659
660#define FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
661
662static void
663csum(void)
664{
665 unsigned int i;
666 unsigned short fcs;
667 unsigned char v;
668
669 if (!scanhex(&adrs))
670 return;
671 if (!scanhex(&ncsum))
672 return;
673 fcs = 0xffff;
674 for (i = 0; i < ncsum; ++i) {
675 if (mread(adrs+i, &v, 1) == 0) {
676 printf("csum stopped at %x\n", adrs+i);
677 break;
678 }
679 fcs = FCS(fcs, v);
680 }
681 printf("%x\n", fcs);
682}
683
684static void
685bpt_cmds(void)
686{
687 int cmd;
688 unsigned a;
689 int mode, i;
690 struct bpt *bp;
691
692 cmd = inchar();
693 switch (cmd) {
694#if ! (defined(CONFIG_8xx) || defined(CONFIG_4xx))
695 case 'd':
696 mode = 7;
697 cmd = inchar();
698 if (cmd == 'r')
699 mode = 5;
700 else if (cmd == 'w')
701 mode = 6;
702 else
703 termch = cmd;
704 cmd = inchar();
705 if (cmd == 'p')
706 mode &= ~4;
707 else
708 termch = cmd;
709 dabr.address = 0;
710 dabr.count = 0;
711 dabr.enabled = scanhex(&dabr.address);
712 scanhex(&dabr.count);
713 if (dabr.enabled)
714 dabr.address = (dabr.address & ~7) | mode;
715 break;
716 case 'i':
717 cmd = inchar();
718 if (cmd == 'p')
719 mode = 2;
720 else
721 mode = 3;
722 iabr.address = 0;
723 iabr.count = 0;
724 iabr.enabled = scanhex(&iabr.address);
725 if (iabr.enabled)
726 iabr.address |= mode;
727 scanhex(&iabr.count);
728 break;
729#endif
730 case 'c':
731 if (!scanhex(&a)) {
732 /* clear all breakpoints */
733 for (i = 0; i < NBPTS; ++i)
734 bpts[i].enabled = 0;
735 iabr.enabled = 0;
736 dabr.enabled = 0;
737 printf("All breakpoints cleared\n");
738 } else {
739 bp = at_breakpoint(a);
740 if (bp == 0) {
741 printf("No breakpoint at %x\n", a);
742 } else {
743 bp->enabled = 0;
744 }
745 }
746 break;
747 default:
748 termch = cmd;
749 if (!scanhex(&a)) {
750 /* print all breakpoints */
751 printf("type address count\n");
752 if (dabr.enabled) {
753 printf("data %.8x %8x [", dabr.address & ~7,
754 dabr.count);
755 if (dabr.address & 1)
756 printf("r");
757 if (dabr.address & 2)
758 printf("w");
759 if (!(dabr.address & 4))
760 printf("p");
761 printf("]\n");
762 }
763 if (iabr.enabled)
764 printf("inst %.8x %8x\n", iabr.address & ~3,
765 iabr.count);
766 for (bp = bpts; bp < &bpts[NBPTS]; ++bp)
767 if (bp->enabled)
768 printf("trap %.8x %8x\n", bp->address,
769 bp->count);
770 break;
771 }
772 bp = at_breakpoint(a);
773 if (bp == 0) {
774 for (bp = bpts; bp < &bpts[NBPTS]; ++bp)
775 if (!bp->enabled)
776 break;
777 if (bp >= &bpts[NBPTS]) {
778 printf("Sorry, no free breakpoints\n");
779 break;
780 }
781 }
782 bp->enabled = 1;
783 bp->address = a;
784 bp->count = 0;
785 scanhex(&bp->count);
786 break;
787 }
788}
789
790static void
791backtrace(struct pt_regs *excp)
792{
793 unsigned sp;
794 unsigned stack[2];
795 struct pt_regs regs;
796 extern char ret_from_except, ret_from_except_full, ret_from_syscall;
797
798 printf("backtrace:\n");
799
800 if (excp != NULL)
801 sp = excp->gpr[1];
802 else
803 sp = getsp();
804 scanhex(&sp);
805 scannl();
806 for (; sp != 0; sp = stack[0]) {
807 if (mread(sp, stack, sizeof(stack)) != sizeof(stack))
808 break;
809 printf("[%.8lx] ", stack[0]);
810 xmon_print_symbol(stack[1], " ", "\n");
811 if (stack[1] == (unsigned) &ret_from_except
812 || stack[1] == (unsigned) &ret_from_except_full
813 || stack[1] == (unsigned) &ret_from_syscall) {
814 if (mread(sp+16, &regs, sizeof(regs)) != sizeof(regs))
815 break;
816 printf("exception:%x [%x] %x\n", regs.trap, sp+16,
817 regs.nip);
818 sp = regs.gpr[1];
819 if (mread(sp, stack, sizeof(stack)) != sizeof(stack))
820 break;
821 }
822 }
823}
824
825int
826getsp(void)
827{
828 int x;
829
830 asm("mr %0,1" : "=r" (x) :);
831 return x;
832}
833
834void
835excprint(struct pt_regs *fp)
836{
837 int trap;
838
839#ifdef CONFIG_SMP
840 printf("cpu %d: ", smp_processor_id());
841#endif /* CONFIG_SMP */
842 printf("vector: %x at pc=", fp->trap);
843 xmon_print_symbol(fp->nip, ": ", ", lr=");
844 xmon_print_symbol(fp->link, ": ", "\n");
845 printf("msr = %x, sp = %x [%x]\n", fp->msr, fp->gpr[1], fp);
846 trap = TRAP(fp);
847 if (trap == 0x300 || trap == 0x600)
848 printf("dar = %x, dsisr = %x\n", fp->dar, fp->dsisr);
849 if (current)
850 printf("current = %x, pid = %d, comm = %s\n",
851 current, current->pid, current->comm);
852}
853
854void
855prregs(struct pt_regs *fp)
856{
857 int n;
858 unsigned base;
859
860 if (scanhex(&base))
861 fp = (struct pt_regs *) base;
862 for (n = 0; n < 32; ++n) {
863 printf("R%.2d = %.8x%s", n, fp->gpr[n],
864 (n & 3) == 3? "\n": " ");
865 if (n == 12 && !FULL_REGS(fp)) {
866 printf("\n");
867 break;
868 }
869 }
870 printf("pc = %.8x msr = %.8x lr = %.8x cr = %.8x\n",
871 fp->nip, fp->msr, fp->link, fp->ccr);
872 printf("ctr = %.8x xer = %.8x trap = %4x\n",
873 fp->ctr, fp->xer, fp->trap);
874}
875
876void
877cacheflush(void)
878{
879 int cmd;
880 unsigned nflush;
881
882 cmd = inchar();
883 if (cmd != 'i')
884 termch = cmd;
885 scanhex(&adrs);
886 if (termch != '\n')
887 termch = 0;
888 nflush = 1;
889 scanhex(&nflush);
890 nflush = (nflush + 31) / 32;
891 if (cmd != 'i') {
892 for (; nflush > 0; --nflush, adrs += 0x20)
893 cflush((void *) adrs);
894 } else {
895 for (; nflush > 0; --nflush, adrs += 0x20)
896 cinval((void *) adrs);
897 }
898}
899
900unsigned int
901read_spr(int n)
902{
903 unsigned int instrs[2];
904 int (*code)(void);
905
906 instrs[0] = 0x7c6002a6 + ((n & 0x1F) << 16) + ((n & 0x3e0) << 6);
907 instrs[1] = 0x4e800020;
908 store_inst(instrs);
909 store_inst(instrs+1);
910 code = (int (*)(void)) instrs;
911 return code();
912}
913
914void
915write_spr(int n, unsigned int val)
916{
917 unsigned int instrs[2];
918 int (*code)(unsigned int);
919
920 instrs[0] = 0x7c6003a6 + ((n & 0x1F) << 16) + ((n & 0x3e0) << 6);
921 instrs[1] = 0x4e800020;
922 store_inst(instrs);
923 store_inst(instrs+1);
924 code = (int (*)(unsigned int)) instrs;
925 code(val);
926}
927
928static unsigned int regno;
929extern char exc_prolog;
930extern char dec_exc;
931
932void
933super_regs(void)
934{
935 int i, cmd;
936 unsigned val;
937
938 cmd = skipbl();
939 if (cmd == '\n') {
940 printf("msr = %x, pvr = %x\n", get_msr(), get_pvr());
941 printf("sprg0-3 = %x %x %x %x\n", get_sprg0(), get_sprg1(),
942 get_sprg2(), get_sprg3());
943 printf("srr0 = %x, srr1 = %x\n", get_srr0(), get_srr1());
944#ifdef CONFIG_PPC_STD_MMU
945 printf("sr0-15 =");
946 for (i = 0; i < 16; ++i)
947 printf(" %x", get_sr(i));
948 printf("\n");
949#endif
950 asm("mr %0,1" : "=r" (i) :);
951 printf("sp = %x ", i);
952 asm("mr %0,2" : "=r" (i) :);
953 printf("toc = %x\n", i);
954 return;
955 }
956
957 scanhex(&regno);
958 switch (cmd) {
959 case 'w':
960 val = read_spr(regno);
961 scanhex(&val);
962 write_spr(regno, val);
963 /* fall through */
964 case 'r':
965 printf("spr %x = %x\n", regno, read_spr(regno));
966 break;
967 case 's':
968 val = get_sr(regno);
969 scanhex(&val);
970 set_sr(regno, val);
971 break;
972 case 'm':
973 val = get_msr();
974 scanhex(&val);
975 set_msr(val);
976 break;
977 }
978 scannl();
979}
980
981#ifndef CONFIG_PPC_STD_MMU
982static void
983dump_hash_table(void)
984{
985 printf("This CPU doesn't have a hash table.\n");
986}
987#else
988
989static void
990dump_hash_table_seg(unsigned seg, unsigned start, unsigned end)
991{
992 extern void *Hash;
993 extern unsigned long Hash_size;
994 unsigned *htab = Hash;
995 unsigned hsize = Hash_size;
996 unsigned v, hmask, va, last_va = 0;
997 int found, last_found, i;
998 unsigned *hg, w1, last_w2 = 0, last_va0 = 0;
999
1000 last_found = 0;
1001 hmask = hsize / 64 - 1;
1002 va = start;
1003 start = (start >> 12) & 0xffff;
1004 end = (end >> 12) & 0xffff;
1005 for (v = start; v < end; ++v) {
1006 found = 0;
1007 hg = htab + (((v ^ seg) & hmask) * 16);
1008 w1 = 0x80000000 | (seg << 7) | (v >> 10);
1009 for (i = 0; i < 8; ++i, hg += 2) {
1010 if (*hg == w1) {
1011 found = 1;
1012 break;
1013 }
1014 }
1015 if (!found) {
1016 w1 ^= 0x40;
1017 hg = htab + ((~(v ^ seg) & hmask) * 16);
1018 for (i = 0; i < 8; ++i, hg += 2) {
1019 if (*hg == w1) {
1020 found = 1;
1021 break;
1022 }
1023 }
1024 }
1025 if (!(last_found && found && (hg[1] & ~0x180) == last_w2 + 4096)) {
1026 if (last_found) {
1027 if (last_va != last_va0)
1028 printf(" ... %x", last_va);
1029 printf("\n");
1030 }
1031 if (found) {
1032 printf("%x to %x", va, hg[1]);
1033 last_va0 = va;
1034 }
1035 last_found = found;
1036 }
1037 if (found) {
1038 last_w2 = hg[1] & ~0x180;
1039 last_va = va;
1040 }
1041 va += 4096;
1042 }
1043 if (last_found)
1044 printf(" ... %x\n", last_va);
1045}
1046
1047static unsigned hash_ctx;
1048static unsigned hash_start;
1049static unsigned hash_end;
1050
1051static void
1052dump_hash_table(void)
1053{
1054 int seg;
1055 unsigned seg_start, seg_end;
1056
1057 hash_ctx = 0;
1058 hash_start = 0;
1059 hash_end = 0xfffff000;
1060 scanhex(&hash_ctx);
1061 scanhex(&hash_start);
1062 scanhex(&hash_end);
1063 printf("Mappings for context %x\n", hash_ctx);
1064 seg_start = hash_start;
1065 for (seg = hash_start >> 28; seg <= hash_end >> 28; ++seg) {
1066 seg_end = (seg << 28) | 0x0ffff000;
1067 if (seg_end > hash_end)
1068 seg_end = hash_end;
1069 dump_hash_table_seg((hash_ctx << 4) + (seg * 0x111),
1070 seg_start, seg_end);
1071 seg_start = seg_end + 0x1000;
1072 }
1073}
1074#endif /* CONFIG_PPC_STD_MMU */
1075
1076/*
1077 * Stuff for reading and writing memory safely
1078 */
1079
1080int
1081mread(unsigned adrs, void *buf, int size)
1082{
1083 volatile int n;
1084 char *p, *q;
1085
1086 n = 0;
1087 if( setjmp(bus_error_jmp) == 0 ){
1088 debugger_fault_handler = handle_fault;
1089 sync();
1090 p = (char *) adrs;
1091 q = (char *) buf;
1092 switch (size) {
1093 case 2: *(short *)q = *(short *)p; break;
1094 case 4: *(int *)q = *(int *)p; break;
1095 default:
1096 for( ; n < size; ++n ) {
1097 *q++ = *p++;
1098 sync();
1099 }
1100 }
1101 sync();
1102 /* wait a little while to see if we get a machine check */
1103 __delay(200);
1104 n = size;
1105 }
1106 debugger_fault_handler = NULL;
1107 return n;
1108}
1109
1110int
1111mwrite(unsigned adrs, void *buf, int size)
1112{
1113 volatile int n;
1114 char *p, *q;
1115
1116 n = 0;
1117 if( setjmp(bus_error_jmp) == 0 ){
1118 debugger_fault_handler = handle_fault;
1119 sync();
1120 p = (char *) adrs;
1121 q = (char *) buf;
1122 switch (size) {
1123 case 2: *(short *)p = *(short *)q; break;
1124 case 4: *(int *)p = *(int *)q; break;
1125 default:
1126 for( ; n < size; ++n ) {
1127 *p++ = *q++;
1128 sync();
1129 }
1130 }
1131 sync();
1132 n = size;
1133 } else {
1134 printf("*** Error writing address %x\n", adrs + n);
1135 }
1136 debugger_fault_handler = NULL;
1137 return n;
1138}
1139
1140static int fault_type;
1141static int fault_except;
1142static char *fault_chars[] = { "--", "**", "##" };
1143
1144static void
1145handle_fault(struct pt_regs *regs)
1146{
1147 fault_except = TRAP(regs);
1148 fault_type = TRAP(regs) == 0x200? 0: TRAP(regs) == 0x300? 1: 2;
1149 longjmp(bus_error_jmp, 1);
1150}
1151
1152#define SWAP(a, b, t) ((t) = (a), (a) = (b), (b) = (t))
1153
1154void
1155byterev(unsigned char *val, int size)
1156{
1157 int t;
1158
1159 switch (size) {
1160 case 2:
1161 SWAP(val[0], val[1], t);
1162 break;
1163 case 4:
1164 SWAP(val[0], val[3], t);
1165 SWAP(val[1], val[2], t);
1166 break;
1167 }
1168}
1169
1170static int brev;
1171static int mnoread;
1172
1173void
1174memex(void)
1175{
1176 int cmd, inc, i, nslash;
1177 unsigned n;
1178 unsigned char val[4];
1179
1180 last_cmd = "m\n";
1181 scanhex(&adrs);
1182 while ((cmd = skipbl()) != '\n') {
1183 switch( cmd ){
1184 case 'b': size = 1; break;
1185 case 'w': size = 2; break;
1186 case 'l': size = 4; break;
1187 case 'r': brev = !brev; break;
1188 case 'n': mnoread = 1; break;
1189 case '.': mnoread = 0; break;
1190 }
1191 }
1192 if( size <= 0 )
1193 size = 1;
1194 else if( size > 4 )
1195 size = 4;
1196 for(;;){
1197 if (!mnoread)
1198 n = mread(adrs, val, size);
1199 printf("%.8x%c", adrs, brev? 'r': ' ');
1200 if (!mnoread) {
1201 if (brev)
1202 byterev(val, size);
1203 putchar(' ');
1204 for (i = 0; i < n; ++i)
1205 printf("%.2x", val[i]);
1206 for (; i < size; ++i)
1207 printf("%s", fault_chars[fault_type]);
1208 }
1209 putchar(' ');
1210 inc = size;
1211 nslash = 0;
1212 for(;;){
1213 if( scanhex(&n) ){
1214 for (i = 0; i < size; ++i)
1215 val[i] = n >> (i * 8);
1216 if (!brev)
1217 byterev(val, size);
1218 mwrite(adrs, val, size);
1219 inc = size;
1220 }
1221 cmd = skipbl();
1222 if (cmd == '\n')
1223 break;
1224 inc = 0;
1225 switch (cmd) {
1226 case '\'':
1227 for(;;){
1228 n = inchar();
1229 if( n == '\\' )
1230 n = bsesc();
1231 else if( n == '\'' )
1232 break;
1233 for (i = 0; i < size; ++i)
1234 val[i] = n >> (i * 8);
1235 if (!brev)
1236 byterev(val, size);
1237 mwrite(adrs, val, size);
1238 adrs += size;
1239 }
1240 adrs -= size;
1241 inc = size;
1242 break;
1243 case ',':
1244 adrs += size;
1245 break;
1246 case '.':
1247 mnoread = 0;
1248 break;
1249 case ';':
1250 break;
1251 case 'x':
1252 case EOF:
1253 scannl();
1254 return;
1255 case 'b':
1256 case 'v':
1257 size = 1;
1258 break;
1259 case 'w':
1260 size = 2;
1261 break;
1262 case 'l':
1263 size = 4;
1264 break;
1265 case '^':
1266 adrs -= size;
1267 break;
1268 break;
1269 case '/':
1270 if (nslash > 0)
1271 adrs -= 1 << nslash;
1272 else
1273 nslash = 0;
1274 nslash += 4;
1275 adrs += 1 << nslash;
1276 break;
1277 case '\\':
1278 if (nslash < 0)
1279 adrs += 1 << -nslash;
1280 else
1281 nslash = 0;
1282 nslash -= 4;
1283 adrs -= 1 << -nslash;
1284 break;
1285 case 'm':
1286 scanhex(&adrs);
1287 break;
1288 case 'n':
1289 mnoread = 1;
1290 break;
1291 case 'r':
1292 brev = !brev;
1293 break;
1294 case '<':
1295 n = size;
1296 scanhex(&n);
1297 adrs -= n;
1298 break;
1299 case '>':
1300 n = size;
1301 scanhex(&n);
1302 adrs += n;
1303 break;
1304 }
1305 }
1306 adrs += inc;
1307 }
1308}
1309
1310int
1311bsesc(void)
1312{
1313 int c;
1314
1315 c = inchar();
1316 switch( c ){
1317 case 'n': c = '\n'; break;
1318 case 'r': c = '\r'; break;
1319 case 'b': c = '\b'; break;
1320 case 't': c = '\t'; break;
1321 }
1322 return c;
1323}
1324
1325void
1326dump(void)
1327{
1328 int c;
1329
1330 c = inchar();
1331 if ((isxdigit(c) && c != 'f' && c != 'd') || c == '\n')
1332 termch = c;
1333 scanhex(&adrs);
1334 if( termch != '\n')
1335 termch = 0;
1336 if( c == 'i' ){
1337 scanhex(&nidump);
1338 if( nidump == 0 )
1339 nidump = 16;
1340 adrs += ppc_inst_dump(adrs, nidump);
1341 last_cmd = "di\n";
1342 } else {
1343 scanhex(&ndump);
1344 if( ndump == 0 )
1345 ndump = 64;
1346 prdump(adrs, ndump);
1347 adrs += ndump;
1348 last_cmd = "d\n";
1349 }
1350}
1351
1352void
1353prdump(unsigned adrs, int ndump)
1354{
1355 register int n, m, c, r, nr;
1356 unsigned char temp[16];
1357
1358 for( n = ndump; n > 0; ){
1359 printf("%.8x", adrs);
1360 putchar(' ');
1361 r = n < 16? n: 16;
1362 nr = mread(adrs, temp, r);
1363 adrs += nr;
1364 for( m = 0; m < r; ++m ){
1365 putchar((m & 3) == 0 && m > 0? '.': ' ');
1366 if( m < nr )
1367 printf("%.2x", temp[m]);
1368 else
1369 printf("%s", fault_chars[fault_type]);
1370 }
1371 for(; m < 16; ++m )
1372 printf(" ");
1373 printf(" |");
1374 for( m = 0; m < r; ++m ){
1375 if( m < nr ){
1376 c = temp[m];
1377 putchar(' ' <= c && c <= '~'? c: '.');
1378 } else
1379 putchar(' ');
1380 }
1381 n -= r;
1382 for(; m < 16; ++m )
1383 putchar(' ');
1384 printf("|\n");
1385 if( nr < r )
1386 break;
1387 }
1388}
1389
1390int
1391ppc_inst_dump(unsigned adr, int count)
1392{
1393 int nr, dotted;
1394 unsigned first_adr;
1395 unsigned long inst, last_inst = 0;
1396 unsigned char val[4];
1397
1398 dotted = 0;
1399 for (first_adr = adr; count > 0; --count, adr += 4){
1400 nr = mread(adr, val, 4);
1401 if( nr == 0 ){
1402 const char *x = fault_chars[fault_type];
1403 printf("%.8x %s%s%s%s\n", adr, x, x, x, x);
1404 break;
1405 }
1406 inst = GETWORD(val);
1407 if (adr > first_adr && inst == last_inst) {
1408 if (!dotted) {
1409 printf(" ...\n");
1410 dotted = 1;
1411 }
1412 continue;
1413 }
1414 dotted = 0;
1415 last_inst = inst;
1416 printf("%.8x ", adr);
1417 printf("%.8x\t", inst);
1418 print_insn_big_powerpc(stdout, inst, adr); /* always returns 4 */
1419 printf("\n");
1420 }
1421 return adr - first_adr;
1422}
1423
1424void
1425print_address(unsigned addr)
1426{
1427 printf("0x%x", addr);
1428}
1429
1430/*
1431 * Memory operations - move, set, print differences
1432 */
1433static unsigned mdest; /* destination address */
1434static unsigned msrc; /* source address */
1435static unsigned mval; /* byte value to set memory to */
1436static unsigned mcount; /* # bytes to affect */
1437static unsigned mdiffs; /* max # differences to print */
1438
1439void
1440memops(int cmd)
1441{
1442 scanhex(&mdest);
1443 if( termch != '\n' )
1444 termch = 0;
1445 scanhex(cmd == 's'? &mval: &msrc);
1446 if( termch != '\n' )
1447 termch = 0;
1448 scanhex(&mcount);
1449 switch( cmd ){
1450 case 'm':
1451 memmove((void *)mdest, (void *)msrc, mcount);
1452 break;
1453 case 's':
1454 memset((void *)mdest, mval, mcount);
1455 break;
1456 case 'd':
1457 if( termch != '\n' )
1458 termch = 0;
1459 scanhex(&mdiffs);
1460 memdiffs((unsigned char *)mdest, (unsigned char *)msrc, mcount, mdiffs);
1461 break;
1462 }
1463}
1464
1465void
1466memdiffs(unsigned char *p1, unsigned char *p2, unsigned nb, unsigned maxpr)
1467{
1468 unsigned n, prt;
1469
1470 prt = 0;
1471 for( n = nb; n > 0; --n )
1472 if( *p1++ != *p2++ )
1473 if( ++prt <= maxpr )
1474 printf("%.8x %.2x # %.8x %.2x\n", (unsigned)p1 - 1,
1475 p1[-1], (unsigned)p2 - 1, p2[-1]);
1476 if( prt > maxpr )
1477 printf("Total of %d differences\n", prt);
1478}
1479
1480static unsigned mend;
1481static unsigned mask;
1482
1483void
1484memlocate(void)
1485{
1486 unsigned a, n;
1487 unsigned char val[4];
1488
1489 last_cmd = "ml";
1490 scanhex(&mdest);
1491 if (termch != '\n') {
1492 termch = 0;
1493 scanhex(&mend);
1494 if (termch != '\n') {
1495 termch = 0;
1496 scanhex(&mval);
1497 mask = ~0;
1498 if (termch != '\n') termch = 0;
1499 scanhex(&mask);
1500 }
1501 }
1502 n = 0;
1503 for (a = mdest; a < mend; a += 4) {
1504 if (mread(a, val, 4) == 4
1505 && ((GETWORD(val) ^ mval) & mask) == 0) {
1506 printf("%.8x: %.8x\n", a, GETWORD(val));
1507 if (++n >= 10)
1508 break;
1509 }
1510 }
1511}
1512
1513static unsigned mskip = 0x1000;
1514static unsigned mlim = 0xffffffff;
1515
1516void
1517memzcan(void)
1518{
1519 unsigned char v;
1520 unsigned a;
1521 int ok, ook;
1522
1523 scanhex(&mdest);
1524 if (termch != '\n') termch = 0;
1525 scanhex(&mskip);
1526 if (termch != '\n') termch = 0;
1527 scanhex(&mlim);
1528 ook = 0;
1529 for (a = mdest; a < mlim; a += mskip) {
1530 ok = mread(a, &v, 1);
1531 if (ok && !ook) {
1532 printf("%.8x .. ", a);
1533 fflush(stdout);
1534 } else if (!ok && ook)
1535 printf("%.8x\n", a - mskip);
1536 ook = ok;
1537 if (a + mskip < a)
1538 break;
1539 }
1540 if (ook)
1541 printf("%.8x\n", a - mskip);
1542}
1543
1544void proccall(void)
1545{
1546 unsigned int args[8];
1547 unsigned int ret;
1548 int i;
1549 typedef unsigned int (*callfunc_t)(unsigned int, unsigned int,
1550 unsigned int, unsigned int, unsigned int,
1551 unsigned int, unsigned int, unsigned int);
1552 callfunc_t func;
1553
1554 scanhex(&adrs);
1555 if (termch != '\n')
1556 termch = 0;
1557 for (i = 0; i < 8; ++i)
1558 args[i] = 0;
1559 for (i = 0; i < 8; ++i) {
1560 if (!scanhex(&args[i]) || termch == '\n')
1561 break;
1562 termch = 0;
1563 }
1564 func = (callfunc_t) adrs;
1565 ret = 0;
1566 if (setjmp(bus_error_jmp) == 0) {
1567 debugger_fault_handler = handle_fault;
1568 sync();
1569 ret = func(args[0], args[1], args[2], args[3],
1570 args[4], args[5], args[6], args[7]);
1571 sync();
1572 printf("return value is %x\n", ret);
1573 } else {
1574 printf("*** %x exception occurred\n", fault_except);
1575 }
1576 debugger_fault_handler = NULL;
1577}
1578
1579/* Input scanning routines */
1580int
1581skipbl(void)
1582{
1583 int c;
1584
1585 if( termch != 0 ){
1586 c = termch;
1587 termch = 0;
1588 } else
1589 c = inchar();
1590 while( c == ' ' || c == '\t' )
1591 c = inchar();
1592 return c;
1593}
1594
1595#define N_PTREGS 44
1596static char *regnames[N_PTREGS] = {
1597 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1598 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1599 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1600 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1601 "pc", "msr", "or3", "ctr", "lr", "xer", "ccr", "mq",
1602 "trap", "dar", "dsisr", "res"
1603};
1604
1605int
1606scanhex(unsigned *vp)
1607{
1608 int c, d;
1609 unsigned v;
1610
1611 c = skipbl();
1612 if (c == '%') {
1613 /* parse register name */
1614 char regname[8];
1615 int i;
1616
1617 for (i = 0; i < sizeof(regname) - 1; ++i) {
1618 c = inchar();
1619 if (!isalnum(c)) {
1620 termch = c;
1621 break;
1622 }
1623 regname[i] = c;
1624 }
1625 regname[i] = 0;
1626 for (i = 0; i < N_PTREGS; ++i) {
1627 if (strcmp(regnames[i], regname) == 0) {
1628 unsigned *rp = (unsigned *)
1629 xmon_regs[smp_processor_id()];
1630 if (rp == NULL) {
1631 printf("regs not available\n");
1632 return 0;
1633 }
1634 *vp = rp[i];
1635 return 1;
1636 }
1637 }
1638 printf("invalid register name '%%%s'\n", regname);
1639 return 0;
1640 } else if (c == '$') {
1641 static char symname[128];
1642 int i;
1643 for (i=0; i<63; i++) {
1644 c = inchar();
1645 if (isspace(c)) {
1646 termch = c;
1647 break;
1648 }
1649 symname[i] = c;
1650 }
1651 symname[i++] = 0;
1652 *vp = 0;
1653 if (setjmp(bus_error_jmp) == 0) {
1654 debugger_fault_handler = handle_fault;
1655 sync();
1656 *vp = kallsyms_lookup_name(symname);
1657 sync();
1658 }
1659 debugger_fault_handler = NULL;
1660 if (!(*vp)) {
1661 printf("unknown symbol\n");
1662 return 0;
1663 }
1664 return 1;
1665 }
1666
1667 d = hexdigit(c);
1668 if( d == EOF ){
1669 termch = c;
1670 return 0;
1671 }
1672 v = 0;
1673 do {
1674 v = (v << 4) + d;
1675 c = inchar();
1676 d = hexdigit(c);
1677 } while( d != EOF );
1678 termch = c;
1679 *vp = v;
1680 return 1;
1681}
1682
1683void
1684scannl(void)
1685{
1686 int c;
1687
1688 c = termch;
1689 termch = 0;
1690 while( c != '\n' )
1691 c = inchar();
1692}
1693
1694int hexdigit(int c)
1695{
1696 if( '0' <= c && c <= '9' )
1697 return c - '0';
1698 if( 'A' <= c && c <= 'F' )
1699 return c - ('A' - 10);
1700 if( 'a' <= c && c <= 'f' )
1701 return c - ('a' - 10);
1702 return EOF;
1703}
1704
1705void
1706getstring(char *s, int size)
1707{
1708 int c;
1709
1710 c = skipbl();
1711 do {
1712 if( size > 1 ){
1713 *s++ = c;
1714 --size;
1715 }
1716 c = inchar();
1717 } while( c != ' ' && c != '\t' && c != '\n' );
1718 termch = c;
1719 *s = 0;
1720}
1721
1722static char line[256];
1723static char *lineptr;
1724
1725void
1726flush_input(void)
1727{
1728 lineptr = NULL;
1729}
1730
1731int
1732inchar(void)
1733{
1734 if (lineptr == NULL || *lineptr == 0) {
1735 if (fgets(line, sizeof(line), stdin) == NULL) {
1736 lineptr = NULL;
1737 return EOF;
1738 }
1739 lineptr = line;
1740 }
1741 return *lineptr++;
1742}
1743
1744void
1745take_input(char *str)
1746{
1747 lineptr = str;
1748}
1749
1750static void
1751symbol_lookup(void)
1752{
1753 int type = inchar();
1754 unsigned addr;
1755 static char tmp[128];
1756
1757 switch (type) {
1758 case 'a':
1759 if (scanhex(&addr))
1760 xmon_print_symbol(addr, ": ", "\n");
1761 termch = 0;
1762 break;
1763 case 's':
1764 getstring(tmp, 64);
1765 if (setjmp(bus_error_jmp) == 0) {
1766 debugger_fault_handler = handle_fault;
1767 sync();
1768 addr = kallsyms_lookup_name(tmp);
1769 if (addr)
1770 printf("%s: %lx\n", tmp, addr);
1771 else
1772 printf("Symbol '%s' not found.\n", tmp);
1773 sync();
1774 }
1775 debugger_fault_handler = NULL;
1776 termch = 0;
1777 break;
1778 }
1779}
1780
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 06:19:58 -0500