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authorKumar Gala <galak@kernel.crashing.org>2008-01-27 15:06:14 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 09:33:10 -0500
commitc42f3ad7f1bf17f31c3febdc71034ed6d793d40f (patch)
tree5a56c44717cf8fe4a5f402370506e5fbb78368e4 /arch/ppc/syslib
parent3155f7f23f7865e64f7eb14e226a2dff8197e51f (diff)
[PPC] Remove 85xx from arch/ppc
85xx exists in arch/powerpc as well as cuImage support to boot from a u-boot that doesn't support device trees. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/ppc/syslib')
-rw-r--r--arch/ppc/syslib/Makefile8
-rw-r--r--arch/ppc/syslib/mpc85xx_devices.c826
-rw-r--r--arch/ppc/syslib/mpc85xx_sys.c233
-rw-r--r--arch/ppc/syslib/ocp.c2
-rw-r--r--arch/ppc/syslib/open_pic.c2
-rw-r--r--arch/ppc/syslib/ppc85xx_common.c38
-rw-r--r--arch/ppc/syslib/ppc85xx_common.h22
-rw-r--r--arch/ppc/syslib/ppc85xx_setup.c367
-rw-r--r--arch/ppc/syslib/ppc85xx_setup.h56
9 files changed, 2 insertions, 1552 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 4d158f3bd474..52ddebe6c6d1 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -87,14 +87,6 @@ endif
87obj-$(CONFIG_BOOTX_TEXT) += btext.o 87obj-$(CONFIG_BOOTX_TEXT) += btext.o
88obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o ppc_sys.o 88obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o ppc_sys.o
89obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o 89obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o
90obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \
91 ppc_sys.o mpc85xx_sys.o \
92 mpc85xx_devices.o
93ifeq ($(CONFIG_85xx),y)
94obj-$(CONFIG_PCI) += pci_auto.o
95endif
96obj-$(CONFIG_MPC8548_CDS) += todc_time.o
97obj-$(CONFIG_MPC8555_CDS) += todc_time.o
98obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ 90obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \
99 mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o 91 mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o
100ifeq ($(CONFIG_PPC_MPC52xx),y) 92ifeq ($(CONFIG_PPC_MPC52xx),y)
diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c
deleted file mode 100644
index 325136e5aee0..000000000000
--- a/arch/ppc/syslib/mpc85xx_devices.c
+++ /dev/null
@@ -1,826 +0,0 @@
1/*
2 * MPC85xx Device descriptions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/serial_8250.h>
18#include <linux/fsl_devices.h>
19#include <linux/fs_enet_pd.h>
20#include <asm/mpc85xx.h>
21#include <asm/irq.h>
22#include <asm/ppc_sys.h>
23#include <asm/cpm2.h>
24
25/* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
27 */
28struct gianfar_mdio_data mpc85xx_mdio_pdata = {
29};
30
31static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
32 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
33 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
34 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
35};
36
37static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
38 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
39 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
40 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
41};
42
43static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49};
50
51static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
52 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
53 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
54 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
55 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
56 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
57};
58
59static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
60 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
61 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
62 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
63 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
64 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
65};
66
67static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
68 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
69 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
70 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
71 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
72 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
73};
74
75static struct gianfar_platform_data mpc85xx_fec_pdata = {
76 .device_flags = 0,
77};
78
79static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
80 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
81};
82
83static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
85};
86
87static struct fs_platform_info mpc85xx_fcc1_pdata = {
88 .fs_no = fsid_fcc1,
89 .cp_page = CPM_CR_FCC1_PAGE,
90 .cp_block = CPM_CR_FCC1_SBLOCK,
91
92 .rx_ring = 32,
93 .tx_ring = 32,
94 .rx_copybreak = 240,
95 .use_napi = 0,
96 .napi_weight = 17,
97
98 .clk_mask = CMX1_CLK_MASK,
99 .clk_route = CMX1_CLK_ROUTE,
100 .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
101
102 .mem_offset = FCC1_MEM_OFFSET,
103};
104
105static struct fs_platform_info mpc85xx_fcc2_pdata = {
106 .fs_no = fsid_fcc2,
107 .cp_page = CPM_CR_FCC2_PAGE,
108 .cp_block = CPM_CR_FCC2_SBLOCK,
109
110 .rx_ring = 32,
111 .tx_ring = 32,
112 .rx_copybreak = 240,
113 .use_napi = 0,
114 .napi_weight = 17,
115
116 .clk_mask = CMX2_CLK_MASK,
117 .clk_route = CMX2_CLK_ROUTE,
118 .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
119
120 .mem_offset = FCC2_MEM_OFFSET,
121};
122
123static struct fs_platform_info mpc85xx_fcc3_pdata = {
124 .fs_no = fsid_fcc3,
125 .cp_page = CPM_CR_FCC3_PAGE,
126 .cp_block = CPM_CR_FCC3_SBLOCK,
127
128 .rx_ring = 32,
129 .tx_ring = 32,
130 .rx_copybreak = 240,
131 .use_napi = 0,
132 .napi_weight = 17,
133
134 .clk_mask = CMX3_CLK_MASK,
135 .clk_route = CMX3_CLK_ROUTE,
136 .clk_trx = (PC_F3RXCLK | PC_F3TXCLK),
137
138 .mem_offset = FCC3_MEM_OFFSET,
139};
140
141static struct plat_serial8250_port serial_platform_data[] = {
142 [0] = {
143 .mapbase = 0x4500,
144 .irq = MPC85xx_IRQ_DUART,
145 .iotype = UPIO_MEM,
146 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
147 },
148 [1] = {
149 .mapbase = 0x4600,
150 .irq = MPC85xx_IRQ_DUART,
151 .iotype = UPIO_MEM,
152 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
153 },
154 { },
155};
156
157struct platform_device ppc_sys_platform_devices[] = {
158 [MPC85xx_TSEC1] = {
159 .name = "fsl-gianfar",
160 .id = 1,
161 .dev.platform_data = &mpc85xx_tsec1_pdata,
162 .num_resources = 4,
163 .resource = (struct resource[]) {
164 {
165 .start = MPC85xx_ENET1_OFFSET,
166 .end = MPC85xx_ENET1_OFFSET +
167 MPC85xx_ENET1_SIZE - 1,
168 .flags = IORESOURCE_MEM,
169 },
170 {
171 .name = "tx",
172 .start = MPC85xx_IRQ_TSEC1_TX,
173 .end = MPC85xx_IRQ_TSEC1_TX,
174 .flags = IORESOURCE_IRQ,
175 },
176 {
177 .name = "rx",
178 .start = MPC85xx_IRQ_TSEC1_RX,
179 .end = MPC85xx_IRQ_TSEC1_RX,
180 .flags = IORESOURCE_IRQ,
181 },
182 {
183 .name = "error",
184 .start = MPC85xx_IRQ_TSEC1_ERROR,
185 .end = MPC85xx_IRQ_TSEC1_ERROR,
186 .flags = IORESOURCE_IRQ,
187 },
188 },
189 },
190 [MPC85xx_TSEC2] = {
191 .name = "fsl-gianfar",
192 .id = 2,
193 .dev.platform_data = &mpc85xx_tsec2_pdata,
194 .num_resources = 4,
195 .resource = (struct resource[]) {
196 {
197 .start = MPC85xx_ENET2_OFFSET,
198 .end = MPC85xx_ENET2_OFFSET +
199 MPC85xx_ENET2_SIZE - 1,
200 .flags = IORESOURCE_MEM,
201 },
202 {
203 .name = "tx",
204 .start = MPC85xx_IRQ_TSEC2_TX,
205 .end = MPC85xx_IRQ_TSEC2_TX,
206 .flags = IORESOURCE_IRQ,
207 },
208 {
209 .name = "rx",
210 .start = MPC85xx_IRQ_TSEC2_RX,
211 .end = MPC85xx_IRQ_TSEC2_RX,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .name = "error",
216 .start = MPC85xx_IRQ_TSEC2_ERROR,
217 .end = MPC85xx_IRQ_TSEC2_ERROR,
218 .flags = IORESOURCE_IRQ,
219 },
220 },
221 },
222 [MPC85xx_FEC] = {
223 .name = "fsl-gianfar",
224 .id = 3,
225 .dev.platform_data = &mpc85xx_fec_pdata,
226 .num_resources = 2,
227 .resource = (struct resource[]) {
228 {
229 .start = MPC85xx_ENET3_OFFSET,
230 .end = MPC85xx_ENET3_OFFSET +
231 MPC85xx_ENET3_SIZE - 1,
232 .flags = IORESOURCE_MEM,
233
234 },
235 {
236 .start = MPC85xx_IRQ_FEC,
237 .end = MPC85xx_IRQ_FEC,
238 .flags = IORESOURCE_IRQ,
239 },
240 },
241 },
242 [MPC85xx_IIC1] = {
243 .name = "fsl-i2c",
244 .id = 1,
245 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
246 .num_resources = 2,
247 .resource = (struct resource[]) {
248 {
249 .start = MPC85xx_IIC1_OFFSET,
250 .end = MPC85xx_IIC1_OFFSET +
251 MPC85xx_IIC1_SIZE - 1,
252 .flags = IORESOURCE_MEM,
253 },
254 {
255 .start = MPC85xx_IRQ_IIC1,
256 .end = MPC85xx_IRQ_IIC1,
257 .flags = IORESOURCE_IRQ,
258 },
259 },
260 },
261 [MPC85xx_DMA0] = {
262 .name = "fsl-dma",
263 .id = 0,
264 .num_resources = 2,
265 .resource = (struct resource[]) {
266 {
267 .start = MPC85xx_DMA0_OFFSET,
268 .end = MPC85xx_DMA0_OFFSET +
269 MPC85xx_DMA0_SIZE - 1,
270 .flags = IORESOURCE_MEM,
271 },
272 {
273 .start = MPC85xx_IRQ_DMA0,
274 .end = MPC85xx_IRQ_DMA0,
275 .flags = IORESOURCE_IRQ,
276 },
277 },
278 },
279 [MPC85xx_DMA1] = {
280 .name = "fsl-dma",
281 .id = 1,
282 .num_resources = 2,
283 .resource = (struct resource[]) {
284 {
285 .start = MPC85xx_DMA1_OFFSET,
286 .end = MPC85xx_DMA1_OFFSET +
287 MPC85xx_DMA1_SIZE - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 {
291 .start = MPC85xx_IRQ_DMA1,
292 .end = MPC85xx_IRQ_DMA1,
293 .flags = IORESOURCE_IRQ,
294 },
295 },
296 },
297 [MPC85xx_DMA2] = {
298 .name = "fsl-dma",
299 .id = 2,
300 .num_resources = 2,
301 .resource = (struct resource[]) {
302 {
303 .start = MPC85xx_DMA2_OFFSET,
304 .end = MPC85xx_DMA2_OFFSET +
305 MPC85xx_DMA2_SIZE - 1,
306 .flags = IORESOURCE_MEM,
307 },
308 {
309 .start = MPC85xx_IRQ_DMA2,
310 .end = MPC85xx_IRQ_DMA2,
311 .flags = IORESOURCE_IRQ,
312 },
313 },
314 },
315 [MPC85xx_DMA3] = {
316 .name = "fsl-dma",
317 .id = 3,
318 .num_resources = 2,
319 .resource = (struct resource[]) {
320 {
321 .start = MPC85xx_DMA3_OFFSET,
322 .end = MPC85xx_DMA3_OFFSET +
323 MPC85xx_DMA3_SIZE - 1,
324 .flags = IORESOURCE_MEM,
325 },
326 {
327 .start = MPC85xx_IRQ_DMA3,
328 .end = MPC85xx_IRQ_DMA3,
329 .flags = IORESOURCE_IRQ,
330 },
331 },
332 },
333 [MPC85xx_DUART] = {
334 .name = "serial8250",
335 .id = PLAT8250_DEV_PLATFORM,
336 .dev.platform_data = serial_platform_data,
337 },
338 [MPC85xx_PERFMON] = {
339 .name = "fsl-perfmon",
340 .id = 1,
341 .num_resources = 2,
342 .resource = (struct resource[]) {
343 {
344 .start = MPC85xx_PERFMON_OFFSET,
345 .end = MPC85xx_PERFMON_OFFSET +
346 MPC85xx_PERFMON_SIZE - 1,
347 .flags = IORESOURCE_MEM,
348 },
349 {
350 .start = MPC85xx_IRQ_PERFMON,
351 .end = MPC85xx_IRQ_PERFMON,
352 .flags = IORESOURCE_IRQ,
353 },
354 },
355 },
356 [MPC85xx_SEC2] = {
357 .name = "fsl-sec2",
358 .id = 1,
359 .num_resources = 2,
360 .resource = (struct resource[]) {
361 {
362 .start = MPC85xx_SEC2_OFFSET,
363 .end = MPC85xx_SEC2_OFFSET +
364 MPC85xx_SEC2_SIZE - 1,
365 .flags = IORESOURCE_MEM,
366 },
367 {
368 .start = MPC85xx_IRQ_SEC2,
369 .end = MPC85xx_IRQ_SEC2,
370 .flags = IORESOURCE_IRQ,
371 },
372 },
373 },
374 [MPC85xx_CPM_FCC1] = {
375 .name = "fsl-cpm-fcc",
376 .id = 1,
377 .num_resources = 4,
378 .dev.platform_data = &mpc85xx_fcc1_pdata,
379 .resource = (struct resource[]) {
380 {
381 .name = "fcc_regs",
382 .start = 0x91300,
383 .end = 0x9131F,
384 .flags = IORESOURCE_MEM,
385 },
386 {
387 .name = "fcc_regs_c",
388 .start = 0x91380,
389 .end = 0x9139F,
390 .flags = IORESOURCE_MEM,
391 },
392 {
393 .name = "fcc_pram",
394 .start = 0x88400,
395 .end = 0x884ff,
396 .flags = IORESOURCE_MEM,
397 },
398 {
399 .start = SIU_INT_FCC1,
400 .end = SIU_INT_FCC1,
401 .flags = IORESOURCE_IRQ,
402 },
403 },
404 },
405 [MPC85xx_CPM_FCC2] = {
406 .name = "fsl-cpm-fcc",
407 .id = 2,
408 .num_resources = 4,
409 .dev.platform_data = &mpc85xx_fcc2_pdata,
410 .resource = (struct resource[]) {
411 {
412 .name = "fcc_regs",
413 .start = 0x91320,
414 .end = 0x9133F,
415 .flags = IORESOURCE_MEM,
416 },
417 {
418 .name = "fcc_regs_c",
419 .start = 0x913A0,
420 .end = 0x913CF,
421 .flags = IORESOURCE_MEM,
422 },
423 {
424 .name = "fcc_pram",
425 .start = 0x88500,
426 .end = 0x885ff,
427 .flags = IORESOURCE_MEM,
428 },
429 {
430 .start = SIU_INT_FCC2,
431 .end = SIU_INT_FCC2,
432 .flags = IORESOURCE_IRQ,
433 },
434 },
435 },
436 [MPC85xx_CPM_FCC3] = {
437 .name = "fsl-cpm-fcc",
438 .id = 3,
439 .num_resources = 4,
440 .dev.platform_data = &mpc85xx_fcc3_pdata,
441 .resource = (struct resource[]) {
442 {
443 .name = "fcc_regs",
444 .start = 0x91340,
445 .end = 0x9135F,
446 .flags = IORESOURCE_MEM,
447 },
448 {
449 .name = "fcc_regs_c",
450 .start = 0x913D0,
451 .end = 0x913FF,
452 .flags = IORESOURCE_MEM,
453 },
454 {
455 .name = "fcc_pram",
456 .start = 0x88600,
457 .end = 0x886ff,
458 .flags = IORESOURCE_MEM,
459 },
460 {
461 .start = SIU_INT_FCC3,
462 .end = SIU_INT_FCC3,
463 .flags = IORESOURCE_IRQ,
464 },
465 },
466 },
467 [MPC85xx_CPM_I2C] = {
468 .name = "fsl-cpm-i2c",
469 .id = 1,
470 .num_resources = 2,
471 .resource = (struct resource[]) {
472 {
473 .start = 0x91860,
474 .end = 0x918BF,
475 .flags = IORESOURCE_MEM,
476 },
477 {
478 .start = SIU_INT_I2C,
479 .end = SIU_INT_I2C,
480 .flags = IORESOURCE_IRQ,
481 },
482 },
483 },
484 [MPC85xx_CPM_SCC1] = {
485 .name = "fsl-cpm-scc",
486 .id = 1,
487 .num_resources = 2,
488 .resource = (struct resource[]) {
489 {
490 .start = 0x91A00,
491 .end = 0x91A1F,
492 .flags = IORESOURCE_MEM,
493 },
494 {
495 .start = SIU_INT_SCC1,
496 .end = SIU_INT_SCC1,
497 .flags = IORESOURCE_IRQ,
498 },
499 },
500 },
501 [MPC85xx_CPM_SCC2] = {
502 .name = "fsl-cpm-scc",
503 .id = 2,
504 .num_resources = 2,
505 .resource = (struct resource[]) {
506 {
507 .start = 0x91A20,
508 .end = 0x91A3F,
509 .flags = IORESOURCE_MEM,
510 },
511 {
512 .start = SIU_INT_SCC2,
513 .end = SIU_INT_SCC2,
514 .flags = IORESOURCE_IRQ,
515 },
516 },
517 },
518 [MPC85xx_CPM_SCC3] = {
519 .name = "fsl-cpm-scc",
520 .id = 3,
521 .num_resources = 2,
522 .resource = (struct resource[]) {
523 {
524 .start = 0x91A40,
525 .end = 0x91A5F,
526 .flags = IORESOURCE_MEM,
527 },
528 {
529 .start = SIU_INT_SCC3,
530 .end = SIU_INT_SCC3,
531 .flags = IORESOURCE_IRQ,
532 },
533 },
534 },
535 [MPC85xx_CPM_SCC4] = {
536 .name = "fsl-cpm-scc",
537 .id = 4,
538 .num_resources = 2,
539 .resource = (struct resource[]) {
540 {
541 .start = 0x91A60,
542 .end = 0x91A7F,
543 .flags = IORESOURCE_MEM,
544 },
545 {
546 .start = SIU_INT_SCC4,
547 .end = SIU_INT_SCC4,
548 .flags = IORESOURCE_IRQ,
549 },
550 },
551 },
552 [MPC85xx_CPM_SPI] = {
553 .name = "fsl-cpm-spi",
554 .id = 1,
555 .num_resources = 2,
556 .resource = (struct resource[]) {
557 {
558 .start = 0x91AA0,
559 .end = 0x91AFF,
560 .flags = IORESOURCE_MEM,
561 },
562 {
563 .start = SIU_INT_SPI,
564 .end = SIU_INT_SPI,
565 .flags = IORESOURCE_IRQ,
566 },
567 },
568 },
569 [MPC85xx_CPM_MCC1] = {
570 .name = "fsl-cpm-mcc",
571 .id = 1,
572 .num_resources = 2,
573 .resource = (struct resource[]) {
574 {
575 .start = 0x91B30,
576 .end = 0x91B3F,
577 .flags = IORESOURCE_MEM,
578 },
579 {
580 .start = SIU_INT_MCC1,
581 .end = SIU_INT_MCC1,
582 .flags = IORESOURCE_IRQ,
583 },
584 },
585 },
586 [MPC85xx_CPM_MCC2] = {
587 .name = "fsl-cpm-mcc",
588 .id = 2,
589 .num_resources = 2,
590 .resource = (struct resource[]) {
591 {
592 .start = 0x91B50,
593 .end = 0x91B5F,
594 .flags = IORESOURCE_MEM,
595 },
596 {
597 .start = SIU_INT_MCC2,
598 .end = SIU_INT_MCC2,
599 .flags = IORESOURCE_IRQ,
600 },
601 },
602 },
603 [MPC85xx_CPM_SMC1] = {
604 .name = "fsl-cpm-smc",
605 .id = 1,
606 .num_resources = 2,
607 .resource = (struct resource[]) {
608 {
609 .start = 0x91A80,
610 .end = 0x91A8F,
611 .flags = IORESOURCE_MEM,
612 },
613 {
614 .start = SIU_INT_SMC1,
615 .end = SIU_INT_SMC1,
616 .flags = IORESOURCE_IRQ,
617 },
618 },
619 },
620 [MPC85xx_CPM_SMC2] = {
621 .name = "fsl-cpm-smc",
622 .id = 2,
623 .num_resources = 2,
624 .resource = (struct resource[]) {
625 {
626 .start = 0x91A90,
627 .end = 0x91A9F,
628 .flags = IORESOURCE_MEM,
629 },
630 {
631 .start = SIU_INT_SMC2,
632 .end = SIU_INT_SMC2,
633 .flags = IORESOURCE_IRQ,
634 },
635 },
636 },
637 [MPC85xx_CPM_USB] = {
638 .name = "fsl-cpm-usb",
639 .id = 2,
640 .num_resources = 2,
641 .resource = (struct resource[]) {
642 {
643 .start = 0x91B60,
644 .end = 0x91B7F,
645 .flags = IORESOURCE_MEM,
646 },
647 {
648 .start = SIU_INT_USB,
649 .end = SIU_INT_USB,
650 .flags = IORESOURCE_IRQ,
651 },
652 },
653 },
654 [MPC85xx_eTSEC1] = {
655 .name = "fsl-gianfar",
656 .id = 1,
657 .dev.platform_data = &mpc85xx_etsec1_pdata,
658 .num_resources = 4,
659 .resource = (struct resource[]) {
660 {
661 .start = MPC85xx_ENET1_OFFSET,
662 .end = MPC85xx_ENET1_OFFSET +
663 MPC85xx_ENET1_SIZE - 1,
664 .flags = IORESOURCE_MEM,
665 },
666 {
667 .name = "tx",
668 .start = MPC85xx_IRQ_TSEC1_TX,
669 .end = MPC85xx_IRQ_TSEC1_TX,
670 .flags = IORESOURCE_IRQ,
671 },
672 {
673 .name = "rx",
674 .start = MPC85xx_IRQ_TSEC1_RX,
675 .end = MPC85xx_IRQ_TSEC1_RX,
676 .flags = IORESOURCE_IRQ,
677 },
678 {
679 .name = "error",
680 .start = MPC85xx_IRQ_TSEC1_ERROR,
681 .end = MPC85xx_IRQ_TSEC1_ERROR,
682 .flags = IORESOURCE_IRQ,
683 },
684 },
685 },
686 [MPC85xx_eTSEC2] = {
687 .name = "fsl-gianfar",
688 .id = 2,
689 .dev.platform_data = &mpc85xx_etsec2_pdata,
690 .num_resources = 4,
691 .resource = (struct resource[]) {
692 {
693 .start = MPC85xx_ENET2_OFFSET,
694 .end = MPC85xx_ENET2_OFFSET +
695 MPC85xx_ENET2_SIZE - 1,
696 .flags = IORESOURCE_MEM,
697 },
698 {
699 .name = "tx",
700 .start = MPC85xx_IRQ_TSEC2_TX,
701 .end = MPC85xx_IRQ_TSEC2_TX,
702 .flags = IORESOURCE_IRQ,
703 },
704 {
705 .name = "rx",
706 .start = MPC85xx_IRQ_TSEC2_RX,
707 .end = MPC85xx_IRQ_TSEC2_RX,
708 .flags = IORESOURCE_IRQ,
709 },
710 {
711 .name = "error",
712 .start = MPC85xx_IRQ_TSEC2_ERROR,
713 .end = MPC85xx_IRQ_TSEC2_ERROR,
714 .flags = IORESOURCE_IRQ,
715 },
716 },
717 },
718 [MPC85xx_eTSEC3] = {
719 .name = "fsl-gianfar",
720 .id = 3,
721 .dev.platform_data = &mpc85xx_etsec3_pdata,
722 .num_resources = 4,
723 .resource = (struct resource[]) {
724 {
725 .start = MPC85xx_ENET3_OFFSET,
726 .end = MPC85xx_ENET3_OFFSET +
727 MPC85xx_ENET3_SIZE - 1,
728 .flags = IORESOURCE_MEM,
729 },
730 {
731 .name = "tx",
732 .start = MPC85xx_IRQ_TSEC3_TX,
733 .end = MPC85xx_IRQ_TSEC3_TX,
734 .flags = IORESOURCE_IRQ,
735 },
736 {
737 .name = "rx",
738 .start = MPC85xx_IRQ_TSEC3_RX,
739 .end = MPC85xx_IRQ_TSEC3_RX,
740 .flags = IORESOURCE_IRQ,
741 },
742 {
743 .name = "error",
744 .start = MPC85xx_IRQ_TSEC3_ERROR,
745 .end = MPC85xx_IRQ_TSEC3_ERROR,
746 .flags = IORESOURCE_IRQ,
747 },
748 },
749 },
750 [MPC85xx_eTSEC4] = {
751 .name = "fsl-gianfar",
752 .id = 4,
753 .dev.platform_data = &mpc85xx_etsec4_pdata,
754 .num_resources = 4,
755 .resource = (struct resource[]) {
756 {
757 .start = 0x27000,
758 .end = 0x27fff,
759 .flags = IORESOURCE_MEM,
760 },
761 {
762 .name = "tx",
763 .start = MPC85xx_IRQ_TSEC4_TX,
764 .end = MPC85xx_IRQ_TSEC4_TX,
765 .flags = IORESOURCE_IRQ,
766 },
767 {
768 .name = "rx",
769 .start = MPC85xx_IRQ_TSEC4_RX,
770 .end = MPC85xx_IRQ_TSEC4_RX,
771 .flags = IORESOURCE_IRQ,
772 },
773 {
774 .name = "error",
775 .start = MPC85xx_IRQ_TSEC4_ERROR,
776 .end = MPC85xx_IRQ_TSEC4_ERROR,
777 .flags = IORESOURCE_IRQ,
778 },
779 },
780 },
781 [MPC85xx_IIC2] = {
782 .name = "fsl-i2c",
783 .id = 2,
784 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
785 .num_resources = 2,
786 .resource = (struct resource[]) {
787 {
788 .start = 0x03100,
789 .end = 0x031ff,
790 .flags = IORESOURCE_MEM,
791 },
792 {
793 .start = MPC85xx_IRQ_IIC1,
794 .end = MPC85xx_IRQ_IIC1,
795 .flags = IORESOURCE_IRQ,
796 },
797 },
798 },
799 [MPC85xx_MDIO] = {
800 .name = "fsl-gianfar_mdio",
801 .id = 0,
802 .dev.platform_data = &mpc85xx_mdio_pdata,
803 .num_resources = 1,
804 .resource = (struct resource[]) {
805 {
806 .start = 0x24520,
807 .end = 0x2453f,
808 .flags = IORESOURCE_MEM,
809 },
810 },
811 },
812};
813
814static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
815{
816 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
817 return 0;
818}
819
820static int __init mach_mpc85xx_init(void)
821{
822 ppc_sys_device_fixup = mach_mpc85xx_fixup;
823 return 0;
824}
825
826postcore_initcall(mach_mpc85xx_init);
diff --git a/arch/ppc/syslib/mpc85xx_sys.c b/arch/ppc/syslib/mpc85xx_sys.c
deleted file mode 100644
index d96a93dbcb5a..000000000000
--- a/arch/ppc/syslib/mpc85xx_sys.c
+++ /dev/null
@@ -1,233 +0,0 @@
1/*
2 * MPC85xx System descriptions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <asm/ppc_sys.h>
18
19struct ppc_sys_spec *cur_ppc_sys_spec;
20struct ppc_sys_spec ppc_sys_specs[] = {
21 {
22 .ppc_sys_name = "8540",
23 .mask = 0xFFFF0000,
24 .value = 0x80300000,
25 .num_devices = 11,
26 .device_list = (enum ppc_sys_devices[])
27 {
28 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_FEC, MPC85xx_IIC1,
29 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
30 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_MDIO,
31 },
32 },
33 {
34 .ppc_sys_name = "8560",
35 .mask = 0xFFFF0000,
36 .value = 0x80700000,
37 .num_devices = 20,
38 .device_list = (enum ppc_sys_devices[])
39 {
40 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
41 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
42 MPC85xx_PERFMON,
43 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
44 MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3, MPC85xx_CPM_SCC4,
45 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3,
46 MPC85xx_CPM_MCC1, MPC85xx_CPM_MCC2, MPC85xx_MDIO,
47 },
48 },
49 {
50 .ppc_sys_name = "8541",
51 .mask = 0xFFFF0000,
52 .value = 0x80720000,
53 .num_devices = 14,
54 .device_list = (enum ppc_sys_devices[])
55 {
56 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
57 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
58 MPC85xx_PERFMON, MPC85xx_DUART,
59 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C,
60 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
61 MPC85xx_MDIO,
62 },
63 },
64 {
65 .ppc_sys_name = "8541E",
66 .mask = 0xFFFF0000,
67 .value = 0x807A0000,
68 .num_devices = 15,
69 .device_list = (enum ppc_sys_devices[])
70 {
71 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
72 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
73 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
74 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C,
75 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
76 MPC85xx_MDIO,
77 },
78 },
79 {
80 .ppc_sys_name = "8555",
81 .mask = 0xFFFF0000,
82 .value = 0x80710000,
83 .num_devices = 20,
84 .device_list = (enum ppc_sys_devices[])
85 {
86 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
87 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
88 MPC85xx_PERFMON, MPC85xx_DUART,
89 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
90 MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3,
91 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
92 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
93 MPC85xx_CPM_USB,
94 MPC85xx_MDIO,
95 },
96 },
97 {
98 .ppc_sys_name = "8555E",
99 .mask = 0xFFFF0000,
100 .value = 0x80790000,
101 .num_devices = 21,
102 .device_list = (enum ppc_sys_devices[])
103 {
104 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
105 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
106 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
107 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
108 MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3,
109 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
110 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
111 MPC85xx_CPM_USB,
112 MPC85xx_MDIO,
113 },
114 },
115 /* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */
116 {
117 .ppc_sys_name = "8548E",
118 .mask = 0xFFFF00F0,
119 .value = 0x80390010,
120 .num_devices = 14,
121 .device_list = (enum ppc_sys_devices[])
122 {
123 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
124 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
125 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
126 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
127 MPC85xx_MDIO,
128 },
129 },
130 {
131 .ppc_sys_name = "8548",
132 .mask = 0xFFFF00F0,
133 .value = 0x80310010,
134 .num_devices = 13,
135 .device_list = (enum ppc_sys_devices[])
136 {
137 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
138 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
139 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
140 MPC85xx_PERFMON, MPC85xx_DUART,
141 MPC85xx_MDIO,
142 },
143 },
144 {
145 .ppc_sys_name = "8547E",
146 .mask = 0xFFFF00F0,
147 .value = 0x80390010,
148 .num_devices = 14,
149 .device_list = (enum ppc_sys_devices[])
150 {
151 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
152 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
153 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
154 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
155 MPC85xx_MDIO,
156 },
157 },
158 {
159 .ppc_sys_name = "8547",
160 .mask = 0xFFFF00F0,
161 .value = 0x80310010,
162 .num_devices = 13,
163 .device_list = (enum ppc_sys_devices[])
164 {
165 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
166 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
167 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
168 MPC85xx_PERFMON, MPC85xx_DUART,
169 MPC85xx_MDIO,
170 },
171 },
172 {
173 .ppc_sys_name = "8545E",
174 .mask = 0xFFFF00F0,
175 .value = 0x80390010,
176 .num_devices = 12,
177 .device_list = (enum ppc_sys_devices[])
178 {
179 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
180 MPC85xx_IIC1, MPC85xx_IIC2,
181 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
182 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
183 MPC85xx_MDIO,
184 },
185 },
186 {
187 .ppc_sys_name = "8545",
188 .mask = 0xFFFF00F0,
189 .value = 0x80310010,
190 .num_devices = 11,
191 .device_list = (enum ppc_sys_devices[])
192 {
193 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
194 MPC85xx_IIC1, MPC85xx_IIC2,
195 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
196 MPC85xx_PERFMON, MPC85xx_DUART,
197 MPC85xx_MDIO,
198 },
199 },
200 {
201 .ppc_sys_name = "8543E",
202 .mask = 0xFFFF00F0,
203 .value = 0x803A0010,
204 .num_devices = 12,
205 .device_list = (enum ppc_sys_devices[])
206 {
207 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
208 MPC85xx_IIC1, MPC85xx_IIC2,
209 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
210 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
211 MPC85xx_MDIO,
212 },
213 },
214 {
215 .ppc_sys_name = "8543",
216 .mask = 0xFFFF00F0,
217 .value = 0x80320010,
218 .num_devices = 11,
219 .device_list = (enum ppc_sys_devices[])
220 {
221 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
222 MPC85xx_IIC1, MPC85xx_IIC2,
223 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
224 MPC85xx_PERFMON, MPC85xx_DUART,
225 MPC85xx_MDIO,
226 },
227 },
228 { /* default match */
229 .ppc_sys_name = "",
230 .mask = 0x00000000,
231 .value = 0x00000000,
232 },
233};
diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c
index d42d4085dc81..ac80370ed2f7 100644
--- a/arch/ppc/syslib/ocp.c
+++ b/arch/ppc/syslib/ocp.c
@@ -20,7 +20,7 @@
20 * of peripherals are found on embedded SoC (System On a Chip) 20 * of peripherals are found on embedded SoC (System On a Chip)
21 * processors or highly integrated system controllers that have 21 * processors or highly integrated system controllers that have
22 * a host bridge and many peripherals. Common examples where 22 * a host bridge and many peripherals. Common examples where
23 * this is already used include the PPC4xx, PPC85xx, MPC52xx, 23 * this is already used include the PPC4xx, MPC52xx,
24 * and MV64xxx parts. 24 * and MV64xxx parts.
25 * 25 *
26 * This subsystem creates a standard OCP bus type within the 26 * This subsystem creates a standard OCP bus type within the
diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c
index 18ec94733293..780a3b9b4fe9 100644
--- a/arch/ppc/syslib/open_pic.c
+++ b/arch/ppc/syslib/open_pic.c
@@ -24,7 +24,7 @@
24 24
25#include "open_pic_defs.h" 25#include "open_pic_defs.h"
26 26
27#if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx) 27#if defined(CONFIG_PRPMC800)
28#define OPENPIC_BIG_ENDIAN 28#define OPENPIC_BIG_ENDIAN
29#endif 29#endif
30 30
diff --git a/arch/ppc/syslib/ppc85xx_common.c b/arch/ppc/syslib/ppc85xx_common.c
deleted file mode 100644
index e5ac699e7316..000000000000
--- a/arch/ppc/syslib/ppc85xx_common.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * MPC85xx support routines
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/types.h>
15#include <linux/module.h>
16#include <linux/init.h>
17
18#include <asm/mpc85xx.h>
19#include <asm/mmu.h>
20
21/* ************************************************************************ */
22/* Return the value of CCSRBAR for the current board */
23
24phys_addr_t
25get_ccsrbar(void)
26{
27 return BOARD_CCSRBAR;
28}
29
30EXPORT_SYMBOL(get_ccsrbar);
31
32/* For now this is a pass through */
33phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
34{
35 return addr;
36};
37EXPORT_SYMBOL(fixup_bigphys_addr);
38
diff --git a/arch/ppc/syslib/ppc85xx_common.h b/arch/ppc/syslib/ppc85xx_common.h
deleted file mode 100644
index 4fc405425113..000000000000
--- a/arch/ppc/syslib/ppc85xx_common.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * MPC85xx support routines
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifndef __PPC_SYSLIB_PPC85XX_COMMON_H
15#define __PPC_SYSLIB_PPC85XX_COMMON_H
16
17#include <linux/init.h>
18
19/* Provide access to ccsrbar for any modules, etc */
20phys_addr_t get_ccsrbar(void);
21
22#endif /* __PPC_SYSLIB_PPC85XX_COMMON_H */
diff --git a/arch/ppc/syslib/ppc85xx_setup.c b/arch/ppc/syslib/ppc85xx_setup.c
deleted file mode 100644
index 2475ec6600fe..000000000000
--- a/arch/ppc/syslib/ppc85xx_setup.c
+++ /dev/null
@@ -1,367 +0,0 @@
1/*
2 * MPC85XX common board code
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/types.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/pci.h>
18#include <linux/serial.h>
19#include <linux/tty.h> /* for linux/serial_core.h */
20#include <linux/serial_core.h>
21#include <linux/serial_8250.h>
22
23#include <asm/time.h>
24#include <asm/mpc85xx.h>
25#include <asm/immap_85xx.h>
26#include <asm/mmu.h>
27#include <asm/ppc_sys.h>
28#include <asm/kgdb.h>
29#include <asm/machdep.h>
30
31#include <syslib/ppc85xx_setup.h>
32
33extern void abort(void);
34
35/* Return the amount of memory */
36unsigned long __init
37mpc85xx_find_end_of_memory(void)
38{
39 bd_t *binfo;
40
41 binfo = (bd_t *) __res;
42
43 return binfo->bi_memsize;
44}
45
46/* The decrementer counts at the system (internal) clock freq divided by 8 */
47void __init
48mpc85xx_calibrate_decr(void)
49{
50 bd_t *binfo = (bd_t *) __res;
51 unsigned int freq, divisor;
52
53 /* get the core frequency */
54 freq = binfo->bi_busfreq;
55
56 /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
57 divisor = 8;
58 tb_ticks_per_jiffy = freq / divisor / HZ;
59 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
60
61 /* Set the time base to zero */
62 mtspr(SPRN_TBWL, 0);
63 mtspr(SPRN_TBWU, 0);
64
65 /* Clear any pending timer interrupts */
66 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
67
68 /* Enable decrementer interrupt */
69 mtspr(SPRN_TCR, TCR_DIE);
70}
71
72#ifdef CONFIG_SERIAL_8250
73void __init
74mpc85xx_early_serial_map(void)
75{
76#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
77 struct uart_port serial_req;
78#endif
79 struct plat_serial8250_port *pdata;
80 bd_t *binfo = (bd_t *) __res;
81 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC85xx_DUART);
82
83 /* Setup serial port access */
84 pdata[0].uartclk = binfo->bi_busfreq;
85 pdata[0].mapbase += binfo->bi_immr_base;
86 pdata[0].membase = ioremap(pdata[0].mapbase, MPC85xx_UART0_SIZE);
87
88#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
89 memset(&serial_req, 0, sizeof (serial_req));
90 serial_req.iotype = UPIO_MEM;
91 serial_req.mapbase = pdata[0].mapbase;
92 serial_req.membase = pdata[0].membase;
93 serial_req.regshift = 0;
94
95 gen550_init(0, &serial_req);
96#endif
97
98 pdata[1].uartclk = binfo->bi_busfreq;
99 pdata[1].mapbase += binfo->bi_immr_base;
100 pdata[1].membase = ioremap(pdata[1].mapbase, MPC85xx_UART0_SIZE);
101
102#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
103 /* Assume gen550_init() doesn't modify serial_req */
104 serial_req.mapbase = pdata[1].mapbase;
105 serial_req.membase = pdata[1].membase;
106
107 gen550_init(1, &serial_req);
108#endif
109}
110#endif
111
112void
113mpc85xx_restart(char *cmd)
114{
115 local_irq_disable();
116 abort();
117}
118
119void
120mpc85xx_power_off(void)
121{
122 local_irq_disable();
123 for(;;);
124}
125
126void
127mpc85xx_halt(void)
128{
129 local_irq_disable();
130 for(;;);
131}
132
133#ifdef CONFIG_PCI
134
135#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
136extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
137extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
138#endif
139
140static void __init
141mpc85xx_setup_pci1(struct pci_controller *hose)
142{
143 volatile struct ccsr_pci *pci;
144 volatile struct ccsr_guts *guts;
145 unsigned short temps;
146 bd_t *binfo = (bd_t *) __res;
147
148 pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
149 MPC85xx_PCI1_SIZE);
150
151 guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
152 MPC85xx_GUTS_SIZE);
153
154 early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
155 temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
156 early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
157
158#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
159 if (guts->pordevsr & PORDEVSR_PCI) {
160 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
161 } else {
162 /* PCI-X init */
163 temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
164 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
165 early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
166 }
167
168 /* Disable all windows (except powar0 since its ignored) */
169 pci->powar1 = 0;
170 pci->powar2 = 0;
171 pci->powar3 = 0;
172 pci->powar4 = 0;
173 pci->piwar1 = 0;
174 pci->piwar2 = 0;
175 pci->piwar3 = 0;
176
177 /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */
178 pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
179 pci->potear1 = 0x00000000;
180 pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
181 /* Enable, Mem R/W */
182 pci->powar1 = 0x80044000 |
183 (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
184
185 /* Setup outbound IO windows @ MPC85XX_PCI1_IO_BASE */
186 pci->potar2 = (MPC85XX_PCI1_LOWER_IO >> 12) & 0x000fffff;
187 pci->potear2 = 0x00000000;
188 pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
189 /* Enable, IO R/W */
190 pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
191
192 /* Setup 2G inbound Memory Window @ 0 */
193 pci->pitar1 = 0x00000000;
194 pci->piwbar1 = 0x00000000;
195 pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
196 Mem, Snoop R/W, 2G */
197}
198
199
200extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin);
201extern int mpc85xx_exclude_device(u_char bus, u_char devfn);
202
203#ifdef CONFIG_85xx_PCI2
204static void __init
205mpc85xx_setup_pci2(struct pci_controller *hose)
206{
207 volatile struct ccsr_pci *pci;
208 unsigned short temps;
209 bd_t *binfo = (bd_t *) __res;
210
211 pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
212 MPC85xx_PCI2_SIZE);
213
214 early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps);
215 temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
216 early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps);
217 early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80);
218
219 /* Disable all windows (except powar0 since its ignored) */
220 pci->powar1 = 0;
221 pci->powar2 = 0;
222 pci->powar3 = 0;
223 pci->powar4 = 0;
224 pci->piwar1 = 0;
225 pci->piwar2 = 0;
226 pci->piwar3 = 0;
227
228 /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */
229 pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
230 pci->potear1 = 0x00000000;
231 pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
232 /* Enable, Mem R/W */
233 pci->powar1 = 0x80044000 |
234 (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1);
235
236 /* Setup outbound IO windows @ MPC85XX_PCI2_IO_BASE */
237 pci->potar2 = (MPC85XX_PCI2_LOWER_IO >> 12) & 0x000fffff;
238 pci->potear2 = 0x00000000;
239 pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
240 /* Enable, IO R/W */
241 pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1);
242
243 /* Setup 2G inbound Memory Window @ 0 */
244 pci->pitar1 = 0x00000000;
245 pci->piwbar1 = 0x00000000;
246 pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
247 Mem, Snoop R/W, 2G */
248}
249#endif /* CONFIG_85xx_PCI2 */
250
251int mpc85xx_pci1_last_busno = 0;
252
253void __init
254mpc85xx_setup_hose(void)
255{
256 struct pci_controller *hose_a;
257#ifdef CONFIG_85xx_PCI2
258 struct pci_controller *hose_b;
259#endif
260 bd_t *binfo = (bd_t *) __res;
261
262 hose_a = pcibios_alloc_controller();
263
264 if (!hose_a)
265 return;
266
267 ppc_md.pci_swizzle = common_swizzle;
268 ppc_md.pci_map_irq = mpc85xx_map_irq;
269
270 hose_a->first_busno = 0;
271 hose_a->bus_offset = 0;
272 hose_a->last_busno = 0xff;
273
274 setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
275 binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
276 hose_a->set_cfg_type = 1;
277
278 mpc85xx_setup_pci1(hose_a);
279
280 hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
281 hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
282 hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
283
284 hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
285 hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
286 hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
287#ifdef CONFIG_85xx_PCI2
288 hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
289 MPC85XX_PCI1_IO_SIZE +
290 MPC85XX_PCI2_IO_SIZE);
291#else
292 hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
293 MPC85XX_PCI1_IO_SIZE);
294#endif
295 isa_io_base = (unsigned long)hose_a->io_base_virt;
296
297 /* setup resources */
298 pci_init_resource(&hose_a->mem_resources[0],
299 MPC85XX_PCI1_LOWER_MEM,
300 MPC85XX_PCI1_UPPER_MEM,
301 IORESOURCE_MEM, "PCI1 host bridge");
302
303 pci_init_resource(&hose_a->io_resource,
304 MPC85XX_PCI1_LOWER_IO,
305 MPC85XX_PCI1_UPPER_IO,
306 IORESOURCE_IO, "PCI1 host bridge");
307
308 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
309
310#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
311 /* Pre pciauto_bus_scan VIA init */
312 mpc85xx_cds_enable_via(hose_a);
313#endif
314
315 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
316
317#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
318 /* Post pciauto_bus_scan VIA fixup */
319 mpc85xx_cds_fixup_via(hose_a);
320#endif
321
322#ifdef CONFIG_85xx_PCI2
323 hose_b = pcibios_alloc_controller();
324
325 if (!hose_b)
326 return;
327
328 hose_b->bus_offset = hose_a->last_busno + 1;
329 hose_b->first_busno = hose_a->last_busno + 1;
330 hose_b->last_busno = 0xff;
331
332 setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
333 binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
334 hose_b->set_cfg_type = 1;
335
336 mpc85xx_setup_pci2(hose_b);
337
338 hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
339 hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
340 hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
341
342 hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
343 hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
344 hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
345 hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE;
346
347 /* setup resources */
348 pci_init_resource(&hose_b->mem_resources[0],
349 MPC85XX_PCI2_LOWER_MEM,
350 MPC85XX_PCI2_UPPER_MEM,
351 IORESOURCE_MEM, "PCI2 host bridge");
352
353 pci_init_resource(&hose_b->io_resource,
354 MPC85XX_PCI2_LOWER_IO,
355 MPC85XX_PCI2_UPPER_IO,
356 IORESOURCE_IO, "PCI2 host bridge");
357
358 hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
359
360 /* let board code know what the last bus number was on PCI1 */
361 mpc85xx_pci1_last_busno = hose_a->last_busno;
362#endif
363 return;
364}
365#endif /* CONFIG_PCI */
366
367
diff --git a/arch/ppc/syslib/ppc85xx_setup.h b/arch/ppc/syslib/ppc85xx_setup.h
deleted file mode 100644
index 6ff79995210b..000000000000
--- a/arch/ppc/syslib/ppc85xx_setup.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * MPC85XX common board definitions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __PPC_SYSLIB_PPC85XX_SETUP_H
16#define __PPC_SYSLIB_PPC85XX_SETUP_H
17
18#include <linux/init.h>
19#include <asm/ppcboot.h>
20
21extern unsigned long mpc85xx_find_end_of_memory(void) __init;
22extern void mpc85xx_calibrate_decr(void) __init;
23extern void mpc85xx_early_serial_map(void) __init;
24extern void mpc85xx_restart(char *cmd);
25extern void mpc85xx_power_off(void);
26extern void mpc85xx_halt(void);
27extern void mpc85xx_setup_hose(void) __init;
28
29/* PCI config */
30#define PCI1_CFG_ADDR_OFFSET (0x8000)
31#define PCI1_CFG_DATA_OFFSET (0x8004)
32
33#define PCI2_CFG_ADDR_OFFSET (0x9000)
34#define PCI2_CFG_DATA_OFFSET (0x9004)
35
36/* Additional register for PCI-X configuration */
37#define PCIX_NEXT_CAP 0x60
38#define PCIX_CAP_ID 0x61
39#define PCIX_COMMAND 0x62
40#define PCIX_STATUS 0x64
41
42/* Serial Config */
43#ifdef CONFIG_SERIAL_MANY_PORTS
44#define RS_TABLE_SIZE 64
45#else
46#define RS_TABLE_SIZE 2
47#endif
48
49#ifndef BASE_BAUD
50#define BASE_BAUD 115200
51#endif
52
53/* Offset of CPM register space */
54#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
55
56#endif /* __PPC_SYSLIB_PPC85XX_SETUP_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 13:42:09 -0500