diff options
author | Kumar Gala <galak@kernel.crashing.org> | 2008-04-19 11:41:43 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2008-04-21 11:19:09 -0400 |
commit | 546be91915a17e4faa9df91caa3ace0c92efa3ab (patch) | |
tree | f82c9c3fb841825f39b71808f6b58cc9e239668e /arch/ppc/syslib | |
parent | 14b3ca4022f050f8622ed282b734ddf445464583 (diff) |
[PPC] Remove mpc8272 ads board from arch/ppc
We have a board port in arch/powerpc so we dont need this one anymore.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/ppc/syslib')
-rw-r--r-- | arch/ppc/syslib/m8260_setup.c | 6 | ||||
-rw-r--r-- | arch/ppc/syslib/m82xx_pci.c | 38 |
2 files changed, 0 insertions, 44 deletions
diff --git a/arch/ppc/syslib/m8260_setup.c b/arch/ppc/syslib/m8260_setup.c index 46588fa94381..b40583724de3 100644 --- a/arch/ppc/syslib/m8260_setup.c +++ b/arch/ppc/syslib/m8260_setup.c | |||
@@ -175,12 +175,6 @@ m8260_init_IRQ(void) | |||
175 | * in case the boot rom changed something on us. | 175 | * in case the boot rom changed something on us. |
176 | */ | 176 | */ |
177 | cpm2_immr->im_intctl.ic_siprr = 0x05309770; | 177 | cpm2_immr->im_intctl.ic_siprr = 0x05309770; |
178 | |||
179 | #if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS)) | ||
180 | /* Initialize stuff for the 82xx CPLD IC and install demux */ | ||
181 | pq2pci_init_irq(); | ||
182 | #endif | ||
183 | |||
184 | } | 178 | } |
185 | 179 | ||
186 | /* | 180 | /* |
diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c index fe860d52e2e4..657a1c25a2ab 100644 --- a/arch/ppc/syslib/m82xx_pci.c +++ b/arch/ppc/syslib/m82xx_pci.c | |||
@@ -150,14 +150,6 @@ pq2pci_init_irq(void) | |||
150 | { | 150 | { |
151 | int irq; | 151 | int irq; |
152 | volatile cpm2_map_t *immap = cpm2_immr; | 152 | volatile cpm2_map_t *immap = cpm2_immr; |
153 | #if defined CONFIG_ADS8272 | ||
154 | /* configure chip select for PCI interrupt controller */ | ||
155 | immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801; | ||
156 | immap->im_memctl.memc_or3 = 0xffff8010; | ||
157 | #elif defined CONFIG_PQ2FADS | ||
158 | immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801; | ||
159 | immap->im_memctl.memc_or8 = 0xffff8010; | ||
160 | #endif | ||
161 | for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++) | 153 | for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++) |
162 | irq_desc[irq].chip = &pq2pci_ic; | 154 | irq_desc[irq].chip = &pq2pci_ic; |
163 | 155 | ||
@@ -222,26 +214,6 @@ pq2ads_setup_pci(struct pci_controller *hose) | |||
222 | immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE; | 214 | immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE; |
223 | #endif | 215 | #endif |
224 | 216 | ||
225 | #if defined CONFIG_ADS8272 | ||
226 | immap->im_siu_conf.siu_82xx.sc_siumcr = | ||
227 | (immap->im_siu_conf.siu_82xx.sc_siumcr & | ||
228 | ~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE | | ||
229 | SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 | | ||
230 | SIUMCR_LBPC11 | SIUMCR_APPC11 | | ||
231 | SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) | | ||
232 | SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 | | ||
233 | SIUMCR_APPC10 | SIUMCR_CS10PC00 | | ||
234 | SIUMCR_BCTLC00 | SIUMCR_MMR11 ; | ||
235 | |||
236 | #elif defined CONFIG_PQ2FADS | ||
237 | /* | ||
238 | * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), | ||
239 | * and local bus for PCI (SIUMCR [LBPC]). | ||
240 | */ | ||
241 | immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr & | ||
242 | ~(SIUMCR_L2CPC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) | | ||
243 | SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10); | ||
244 | #endif | ||
245 | /* Enable PCI */ | 217 | /* Enable PCI */ |
246 | immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN); | 218 | immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN); |
247 | 219 | ||
@@ -284,12 +256,6 @@ pq2ads_setup_pci(struct pci_controller *hose) | |||
284 | immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT); | 256 | immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT); |
285 | immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT); | 257 | immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT); |
286 | 258 | ||
287 | #if defined CONFIG_ADS8272 | ||
288 | /* PCI int highest prio */ | ||
289 | immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745; | ||
290 | #elif defined CONFIG_PQ2FADS | ||
291 | immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567; | ||
292 | #endif | ||
293 | /* park bus on PCI */ | 259 | /* park bus on PCI */ |
294 | immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; | 260 | immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; |
295 | 261 | ||
@@ -320,10 +286,6 @@ void __init pq2_find_bridges(void) | |||
320 | hose->bus_offset = 0; | 286 | hose->bus_offset = 0; |
321 | hose->last_busno = 0xff; | 287 | hose->last_busno = 0xff; |
322 | 288 | ||
323 | #ifdef CONFIG_ADS8272 | ||
324 | hose->set_cfg_type = 1; | ||
325 | #endif | ||
326 | |||
327 | setup_m8260_indirect_pci(hose, | 289 | setup_m8260_indirect_pci(hose, |
328 | (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr, | 290 | (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr, |
329 | (unsigned long)&cpm2_immr->im_pci.pci_cfg_data); | 291 | (unsigned long)&cpm2_immr->im_pci.pci_cfg_data); |