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authorKumar Gala <galak@kernel.crashing.org>2008-01-25 16:41:00 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 09:33:09 -0500
commit3155f7f23f7865e64f7eb14e226a2dff8197e51f (patch)
tree1ab72855399616a248c967a15b6a2801a751f2d5 /arch/ppc/syslib
parent80f4ec7f5b81e7e238acfaf50ac82489b5fcee6f (diff)
[PPC] Remove 83xx from arch/ppc
83xx exists in arch/powerpc as well as cuImage support to boot from a u-boot that doesn't support device trees. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/ppc/syslib')
-rw-r--r--arch/ppc/syslib/Makefile5
-rw-r--r--arch/ppc/syslib/ipic.c646
-rw-r--r--arch/ppc/syslib/ipic.h47
-rw-r--r--arch/ppc/syslib/mpc83xx_devices.c251
-rw-r--r--arch/ppc/syslib/mpc83xx_sys.c122
-rw-r--r--arch/ppc/syslib/ppc83xx_pci.h151
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.c410
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.h55
8 files changed, 0 insertions, 1687 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 5e16228f7645..4d158f3bd474 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -93,11 +93,6 @@ obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \
93ifeq ($(CONFIG_85xx),y) 93ifeq ($(CONFIG_85xx),y)
94obj-$(CONFIG_PCI) += pci_auto.o 94obj-$(CONFIG_PCI) += pci_auto.o
95endif 95endif
96obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \
97 mpc83xx_sys.o mpc83xx_devices.o ipic.o
98ifeq ($(CONFIG_83xx),y)
99obj-$(CONFIG_PCI) += pci_auto.o
100endif
101obj-$(CONFIG_MPC8548_CDS) += todc_time.o 96obj-$(CONFIG_MPC8548_CDS) += todc_time.o
102obj-$(CONFIG_MPC8555_CDS) += todc_time.o 97obj-$(CONFIG_MPC8555_CDS) += todc_time.o
103obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ 98obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c
deleted file mode 100644
index 9192777d0f78..000000000000
--- a/arch/ppc/syslib/ipic.c
+++ /dev/null
@@ -1,646 +0,0 @@
1/*
2 * arch/ppc/syslib/ipic.c
3 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
21#include <linux/sysdev.h>
22#include <asm/irq.h>
23#include <asm/io.h>
24#include <asm/ipic.h>
25#include <asm/mpc83xx.h>
26
27#include "ipic.h"
28
29static struct ipic p_ipic;
30static struct ipic * primary_ipic;
31
32static struct ipic_info ipic_info[] = {
33 [9] = {
34 .pend = IPIC_SIPNR_H,
35 .mask = IPIC_SIMSR_H,
36 .prio = IPIC_SIPRR_D,
37 .force = IPIC_SIFCR_H,
38 .bit = 24,
39 .prio_mask = 0,
40 },
41 [10] = {
42 .pend = IPIC_SIPNR_H,
43 .mask = IPIC_SIMSR_H,
44 .prio = IPIC_SIPRR_D,
45 .force = IPIC_SIFCR_H,
46 .bit = 25,
47 .prio_mask = 1,
48 },
49 [11] = {
50 .pend = IPIC_SIPNR_H,
51 .mask = IPIC_SIMSR_H,
52 .prio = IPIC_SIPRR_D,
53 .force = IPIC_SIFCR_H,
54 .bit = 26,
55 .prio_mask = 2,
56 },
57 [14] = {
58 .pend = IPIC_SIPNR_H,
59 .mask = IPIC_SIMSR_H,
60 .prio = IPIC_SIPRR_D,
61 .force = IPIC_SIFCR_H,
62 .bit = 29,
63 .prio_mask = 5,
64 },
65 [15] = {
66 .pend = IPIC_SIPNR_H,
67 .mask = IPIC_SIMSR_H,
68 .prio = IPIC_SIPRR_D,
69 .force = IPIC_SIFCR_H,
70 .bit = 30,
71 .prio_mask = 6,
72 },
73 [16] = {
74 .pend = IPIC_SIPNR_H,
75 .mask = IPIC_SIMSR_H,
76 .prio = IPIC_SIPRR_D,
77 .force = IPIC_SIFCR_H,
78 .bit = 31,
79 .prio_mask = 7,
80 },
81 [17] = {
82 .pend = IPIC_SEPNR,
83 .mask = IPIC_SEMSR,
84 .prio = IPIC_SMPRR_A,
85 .force = IPIC_SEFCR,
86 .bit = 1,
87 .prio_mask = 5,
88 },
89 [18] = {
90 .pend = IPIC_SEPNR,
91 .mask = IPIC_SEMSR,
92 .prio = IPIC_SMPRR_A,
93 .force = IPIC_SEFCR,
94 .bit = 2,
95 .prio_mask = 6,
96 },
97 [19] = {
98 .pend = IPIC_SEPNR,
99 .mask = IPIC_SEMSR,
100 .prio = IPIC_SMPRR_A,
101 .force = IPIC_SEFCR,
102 .bit = 3,
103 .prio_mask = 7,
104 },
105 [20] = {
106 .pend = IPIC_SEPNR,
107 .mask = IPIC_SEMSR,
108 .prio = IPIC_SMPRR_B,
109 .force = IPIC_SEFCR,
110 .bit = 4,
111 .prio_mask = 4,
112 },
113 [21] = {
114 .pend = IPIC_SEPNR,
115 .mask = IPIC_SEMSR,
116 .prio = IPIC_SMPRR_B,
117 .force = IPIC_SEFCR,
118 .bit = 5,
119 .prio_mask = 5,
120 },
121 [22] = {
122 .pend = IPIC_SEPNR,
123 .mask = IPIC_SEMSR,
124 .prio = IPIC_SMPRR_B,
125 .force = IPIC_SEFCR,
126 .bit = 6,
127 .prio_mask = 6,
128 },
129 [23] = {
130 .pend = IPIC_SEPNR,
131 .mask = IPIC_SEMSR,
132 .prio = IPIC_SMPRR_B,
133 .force = IPIC_SEFCR,
134 .bit = 7,
135 .prio_mask = 7,
136 },
137 [32] = {
138 .pend = IPIC_SIPNR_H,
139 .mask = IPIC_SIMSR_H,
140 .prio = IPIC_SIPRR_A,
141 .force = IPIC_SIFCR_H,
142 .bit = 0,
143 .prio_mask = 0,
144 },
145 [33] = {
146 .pend = IPIC_SIPNR_H,
147 .mask = IPIC_SIMSR_H,
148 .prio = IPIC_SIPRR_A,
149 .force = IPIC_SIFCR_H,
150 .bit = 1,
151 .prio_mask = 1,
152 },
153 [34] = {
154 .pend = IPIC_SIPNR_H,
155 .mask = IPIC_SIMSR_H,
156 .prio = IPIC_SIPRR_A,
157 .force = IPIC_SIFCR_H,
158 .bit = 2,
159 .prio_mask = 2,
160 },
161 [35] = {
162 .pend = IPIC_SIPNR_H,
163 .mask = IPIC_SIMSR_H,
164 .prio = IPIC_SIPRR_A,
165 .force = IPIC_SIFCR_H,
166 .bit = 3,
167 .prio_mask = 3,
168 },
169 [36] = {
170 .pend = IPIC_SIPNR_H,
171 .mask = IPIC_SIMSR_H,
172 .prio = IPIC_SIPRR_A,
173 .force = IPIC_SIFCR_H,
174 .bit = 4,
175 .prio_mask = 4,
176 },
177 [37] = {
178 .pend = IPIC_SIPNR_H,
179 .mask = IPIC_SIMSR_H,
180 .prio = IPIC_SIPRR_A,
181 .force = IPIC_SIFCR_H,
182 .bit = 5,
183 .prio_mask = 5,
184 },
185 [38] = {
186 .pend = IPIC_SIPNR_H,
187 .mask = IPIC_SIMSR_H,
188 .prio = IPIC_SIPRR_A,
189 .force = IPIC_SIFCR_H,
190 .bit = 6,
191 .prio_mask = 6,
192 },
193 [39] = {
194 .pend = IPIC_SIPNR_H,
195 .mask = IPIC_SIMSR_H,
196 .prio = IPIC_SIPRR_A,
197 .force = IPIC_SIFCR_H,
198 .bit = 7,
199 .prio_mask = 7,
200 },
201 [48] = {
202 .pend = IPIC_SEPNR,
203 .mask = IPIC_SEMSR,
204 .prio = IPIC_SMPRR_A,
205 .force = IPIC_SEFCR,
206 .bit = 0,
207 .prio_mask = 4,
208 },
209 [64] = {
210 .pend = IPIC_SIPNR_H,
211 .mask = IPIC_SIMSR_L,
212 .prio = IPIC_SMPRR_A,
213 .force = IPIC_SIFCR_L,
214 .bit = 0,
215 .prio_mask = 0,
216 },
217 [65] = {
218 .pend = IPIC_SIPNR_H,
219 .mask = IPIC_SIMSR_L,
220 .prio = IPIC_SMPRR_A,
221 .force = IPIC_SIFCR_L,
222 .bit = 1,
223 .prio_mask = 1,
224 },
225 [66] = {
226 .pend = IPIC_SIPNR_H,
227 .mask = IPIC_SIMSR_L,
228 .prio = IPIC_SMPRR_A,
229 .force = IPIC_SIFCR_L,
230 .bit = 2,
231 .prio_mask = 2,
232 },
233 [67] = {
234 .pend = IPIC_SIPNR_H,
235 .mask = IPIC_SIMSR_L,
236 .prio = IPIC_SMPRR_A,
237 .force = IPIC_SIFCR_L,
238 .bit = 3,
239 .prio_mask = 3,
240 },
241 [68] = {
242 .pend = IPIC_SIPNR_H,
243 .mask = IPIC_SIMSR_L,
244 .prio = IPIC_SMPRR_B,
245 .force = IPIC_SIFCR_L,
246 .bit = 4,
247 .prio_mask = 0,
248 },
249 [69] = {
250 .pend = IPIC_SIPNR_H,
251 .mask = IPIC_SIMSR_L,
252 .prio = IPIC_SMPRR_B,
253 .force = IPIC_SIFCR_L,
254 .bit = 5,
255 .prio_mask = 1,
256 },
257 [70] = {
258 .pend = IPIC_SIPNR_H,
259 .mask = IPIC_SIMSR_L,
260 .prio = IPIC_SMPRR_B,
261 .force = IPIC_SIFCR_L,
262 .bit = 6,
263 .prio_mask = 2,
264 },
265 [71] = {
266 .pend = IPIC_SIPNR_H,
267 .mask = IPIC_SIMSR_L,
268 .prio = IPIC_SMPRR_B,
269 .force = IPIC_SIFCR_L,
270 .bit = 7,
271 .prio_mask = 3,
272 },
273 [72] = {
274 .pend = IPIC_SIPNR_H,
275 .mask = IPIC_SIMSR_L,
276 .prio = 0,
277 .force = IPIC_SIFCR_L,
278 .bit = 8,
279 },
280 [73] = {
281 .pend = IPIC_SIPNR_H,
282 .mask = IPIC_SIMSR_L,
283 .prio = 0,
284 .force = IPIC_SIFCR_L,
285 .bit = 9,
286 },
287 [74] = {
288 .pend = IPIC_SIPNR_H,
289 .mask = IPIC_SIMSR_L,
290 .prio = 0,
291 .force = IPIC_SIFCR_L,
292 .bit = 10,
293 },
294 [75] = {
295 .pend = IPIC_SIPNR_H,
296 .mask = IPIC_SIMSR_L,
297 .prio = 0,
298 .force = IPIC_SIFCR_L,
299 .bit = 11,
300 },
301 [76] = {
302 .pend = IPIC_SIPNR_H,
303 .mask = IPIC_SIMSR_L,
304 .prio = 0,
305 .force = IPIC_SIFCR_L,
306 .bit = 12,
307 },
308 [77] = {
309 .pend = IPIC_SIPNR_H,
310 .mask = IPIC_SIMSR_L,
311 .prio = 0,
312 .force = IPIC_SIFCR_L,
313 .bit = 13,
314 },
315 [78] = {
316 .pend = IPIC_SIPNR_H,
317 .mask = IPIC_SIMSR_L,
318 .prio = 0,
319 .force = IPIC_SIFCR_L,
320 .bit = 14,
321 },
322 [79] = {
323 .pend = IPIC_SIPNR_H,
324 .mask = IPIC_SIMSR_L,
325 .prio = 0,
326 .force = IPIC_SIFCR_L,
327 .bit = 15,
328 },
329 [80] = {
330 .pend = IPIC_SIPNR_H,
331 .mask = IPIC_SIMSR_L,
332 .prio = 0,
333 .force = IPIC_SIFCR_L,
334 .bit = 16,
335 },
336 [84] = {
337 .pend = IPIC_SIPNR_H,
338 .mask = IPIC_SIMSR_L,
339 .prio = 0,
340 .force = IPIC_SIFCR_L,
341 .bit = 20,
342 },
343 [85] = {
344 .pend = IPIC_SIPNR_H,
345 .mask = IPIC_SIMSR_L,
346 .prio = 0,
347 .force = IPIC_SIFCR_L,
348 .bit = 21,
349 },
350 [90] = {
351 .pend = IPIC_SIPNR_H,
352 .mask = IPIC_SIMSR_L,
353 .prio = 0,
354 .force = IPIC_SIFCR_L,
355 .bit = 26,
356 },
357 [91] = {
358 .pend = IPIC_SIPNR_H,
359 .mask = IPIC_SIMSR_L,
360 .prio = 0,
361 .force = IPIC_SIFCR_L,
362 .bit = 27,
363 },
364};
365
366static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
367{
368 return in_be32(base + (reg >> 2));
369}
370
371static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
372{
373 out_be32(base + (reg >> 2), value);
374}
375
376static inline struct ipic * ipic_from_irq(unsigned int irq)
377{
378 return primary_ipic;
379}
380
381static void ipic_enable_irq(unsigned int irq)
382{
383 struct ipic *ipic = ipic_from_irq(irq);
384 unsigned int src = irq - ipic->irq_offset;
385 u32 temp;
386
387 temp = ipic_read(ipic->regs, ipic_info[src].mask);
388 temp |= (1 << (31 - ipic_info[src].bit));
389 ipic_write(ipic->regs, ipic_info[src].mask, temp);
390}
391
392static void ipic_disable_irq(unsigned int irq)
393{
394 struct ipic *ipic = ipic_from_irq(irq);
395 unsigned int src = irq - ipic->irq_offset;
396 u32 temp;
397
398 temp = ipic_read(ipic->regs, ipic_info[src].mask);
399 temp &= ~(1 << (31 - ipic_info[src].bit));
400 ipic_write(ipic->regs, ipic_info[src].mask, temp);
401}
402
403static void ipic_disable_irq_and_ack(unsigned int irq)
404{
405 struct ipic *ipic = ipic_from_irq(irq);
406 unsigned int src = irq - ipic->irq_offset;
407 u32 temp;
408
409 ipic_disable_irq(irq);
410
411 temp = ipic_read(ipic->regs, ipic_info[src].pend);
412 temp |= (1 << (31 - ipic_info[src].bit));
413 ipic_write(ipic->regs, ipic_info[src].pend, temp);
414}
415
416static void ipic_end_irq(unsigned int irq)
417{
418 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
419 ipic_enable_irq(irq);
420}
421
422struct hw_interrupt_type ipic = {
423 .typename = " IPIC ",
424 .enable = ipic_enable_irq,
425 .disable = ipic_disable_irq,
426 .ack = ipic_disable_irq_and_ack,
427 .end = ipic_end_irq,
428};
429
430void __init ipic_init(phys_addr_t phys_addr,
431 unsigned int flags,
432 unsigned int irq_offset,
433 unsigned char *senses,
434 unsigned int senses_count)
435{
436 u32 i, temp = 0;
437
438 primary_ipic = &p_ipic;
439 primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
440
441 primary_ipic->irq_offset = irq_offset;
442
443 ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0);
444
445 /* default priority scheme is grouped. If spread mode is required
446 * configure SICFR accordingly */
447 if (flags & IPIC_SPREADMODE_GRP_A)
448 temp |= SICFR_IPSA;
449 if (flags & IPIC_SPREADMODE_GRP_D)
450 temp |= SICFR_IPSD;
451 if (flags & IPIC_SPREADMODE_MIX_A)
452 temp |= SICFR_MPSA;
453 if (flags & IPIC_SPREADMODE_MIX_B)
454 temp |= SICFR_MPSB;
455
456 ipic_write(primary_ipic->regs, IPIC_SICNR, temp);
457
458 /* handle MCP route */
459 temp = 0;
460 if (flags & IPIC_DISABLE_MCP_OUT)
461 temp = SERCR_MCPR;
462 ipic_write(primary_ipic->regs, IPIC_SERCR, temp);
463
464 /* handle routing of IRQ0 to MCP */
465 temp = ipic_read(primary_ipic->regs, IPIC_SEMSR);
466
467 if (flags & IPIC_IRQ0_MCP)
468 temp |= SEMSR_SIRQ0;
469 else
470 temp &= ~SEMSR_SIRQ0;
471
472 ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
473
474 for (i = 0 ; i < NR_IPIC_INTS ; i++) {
475 irq_desc[i+irq_offset].chip = &ipic;
476 irq_desc[i+irq_offset].status = IRQ_LEVEL;
477 }
478
479 temp = 0;
480 for (i = 0 ; i < senses_count ; i++) {
481 if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
482 temp |= 1 << (15 - i);
483 if (i != 0)
484 irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
485 else
486 irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
487 }
488 }
489 ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
490
491 printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
492 senses_count, primary_ipic->regs);
493}
494
495int ipic_set_priority(unsigned int irq, unsigned int priority)
496{
497 struct ipic *ipic = ipic_from_irq(irq);
498 unsigned int src = irq - ipic->irq_offset;
499 u32 temp;
500
501 if (priority > 7)
502 return -EINVAL;
503 if (src > 127)
504 return -EINVAL;
505 if (ipic_info[src].prio == 0)
506 return -EINVAL;
507
508 temp = ipic_read(ipic->regs, ipic_info[src].prio);
509
510 if (priority < 4) {
511 temp &= ~(0x7 << (20 + (3 - priority) * 3));
512 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
513 } else {
514 temp &= ~(0x7 << (4 + (7 - priority) * 3));
515 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
516 }
517
518 ipic_write(ipic->regs, ipic_info[src].prio, temp);
519
520 return 0;
521}
522
523void ipic_set_highest_priority(unsigned int irq)
524{
525 struct ipic *ipic = ipic_from_irq(irq);
526 unsigned int src = irq - ipic->irq_offset;
527 u32 temp;
528
529 temp = ipic_read(ipic->regs, IPIC_SICFR);
530
531 /* clear and set HPI */
532 temp &= 0x7f000000;
533 temp |= (src & 0x7f) << 24;
534
535 ipic_write(ipic->regs, IPIC_SICFR, temp);
536}
537
538void ipic_set_default_priority(void)
539{
540 ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
541 ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
542 ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
543 ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
544 ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
545 ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
546 ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
547 ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
548
549 ipic_set_priority(MPC83xx_IRQ_UART1, 0);
550 ipic_set_priority(MPC83xx_IRQ_UART2, 1);
551 ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
552 ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
553 ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
554 ipic_set_priority(MPC83xx_IRQ_SPI, 7);
555 ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
556 ipic_set_priority(MPC83xx_IRQ_PIT, 1);
557 ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
558 ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
559 ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
560 ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
561 ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
562 ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
563 ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
564 ipic_set_priority(MPC83xx_IRQ_MU, 1);
565 ipic_set_priority(MPC83xx_IRQ_SBA, 2);
566 ipic_set_priority(MPC83xx_IRQ_DMA, 3);
567 ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
568 ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
569 ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
570 ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
571}
572
573void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
574{
575 struct ipic *ipic = primary_ipic;
576 u32 temp;
577
578 temp = ipic_read(ipic->regs, IPIC_SERMR);
579 temp |= (1 << (31 - mcp_irq));
580 ipic_write(ipic->regs, IPIC_SERMR, temp);
581}
582
583void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
584{
585 struct ipic *ipic = primary_ipic;
586 u32 temp;
587
588 temp = ipic_read(ipic->regs, IPIC_SERMR);
589 temp &= (1 << (31 - mcp_irq));
590 ipic_write(ipic->regs, IPIC_SERMR, temp);
591}
592
593u32 ipic_get_mcp_status(void)
594{
595 return ipic_read(primary_ipic->regs, IPIC_SERMR);
596}
597
598void ipic_clear_mcp_status(u32 mask)
599{
600 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
601}
602
603/* Return an interrupt vector or -1 if no interrupt is pending. */
604int ipic_get_irq(void)
605{
606 int irq;
607
608 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f;
609
610 if (irq == 0) /* 0 --> no irq is pending */
611 irq = -1;
612
613 return irq;
614}
615
616static struct sysdev_class ipic_sysclass = {
617 set_kset_name("ipic"),
618};
619
620static struct sys_device device_ipic = {
621 .id = 0,
622 .cls = &ipic_sysclass,
623};
624
625static int __init init_ipic_sysfs(void)
626{
627 int rc;
628
629 if (!primary_ipic->regs)
630 return -ENODEV;
631 printk(KERN_DEBUG "Registering ipic with sysfs...\n");
632
633 rc = sysdev_class_register(&ipic_sysclass);
634 if (rc) {
635 printk(KERN_ERR "Failed registering ipic sys class\n");
636 return -ENODEV;
637 }
638 rc = sysdev_register(&device_ipic);
639 if (rc) {
640 printk(KERN_ERR "Failed registering ipic sys device\n");
641 return -ENODEV;
642 }
643 return 0;
644}
645
646subsys_initcall(init_ipic_sysfs);
diff --git a/arch/ppc/syslib/ipic.h b/arch/ppc/syslib/ipic.h
deleted file mode 100644
index a60c9d18bb7f..000000000000
--- a/arch/ppc/syslib/ipic.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * IPIC private definitions and structure.
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#ifndef __IPIC_H__
14#define __IPIC_H__
15
16#include <asm/ipic.h>
17
18#define MPC83xx_IPIC_SIZE (0x00100)
19
20/* System Global Interrupt Configuration Register */
21#define SICFR_IPSA 0x00010000
22#define SICFR_IPSD 0x00080000
23#define SICFR_MPSA 0x00200000
24#define SICFR_MPSB 0x00400000
25
26/* System External Interrupt Mask Register */
27#define SEMSR_SIRQ0 0x00008000
28
29/* System Error Control Register */
30#define SERCR_MCPR 0x00000001
31
32struct ipic {
33 volatile u32 __iomem *regs;
34 unsigned int irq_offset;
35};
36
37struct ipic_info {
38 u8 pend; /* pending register offset from base */
39 u8 mask; /* mask register offset from base */
40 u8 prio; /* priority register offset from base */
41 u8 force; /* force register offset from base */
42 u8 bit; /* register bit position (as per doc)
43 bit mask = 1 << (31 - bit) */
44 u8 prio_mask; /* priority mask value */
45};
46
47#endif /* __IPIC_H__ */
diff --git a/arch/ppc/syslib/mpc83xx_devices.c b/arch/ppc/syslib/mpc83xx_devices.c
deleted file mode 100644
index 5c4932ca8e9b..000000000000
--- a/arch/ppc/syslib/mpc83xx_devices.c
+++ /dev/null
@@ -1,251 +0,0 @@
1/*
2 * MPC83xx Device descriptions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/serial_8250.h>
18#include <linux/fsl_devices.h>
19#include <asm/mpc83xx.h>
20#include <asm/irq.h>
21#include <asm/ppc_sys.h>
22#include <asm/machdep.h>
23
24/* We use offsets for IORESOURCE_MEM since we do not know at compile time
25 * what IMMRBAR is, will get fixed up by mach_mpc83xx_fixup
26 */
27
28struct gianfar_mdio_data mpc83xx_mdio_pdata = {
29};
30
31static struct gianfar_platform_data mpc83xx_tsec1_pdata = {
32 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
33 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
34 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
35};
36
37static struct gianfar_platform_data mpc83xx_tsec2_pdata = {
38 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
39 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
40 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
41};
42
43static struct fsl_i2c_platform_data mpc83xx_fsl_i2c1_pdata = {
44 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
45};
46
47static struct fsl_i2c_platform_data mpc83xx_fsl_i2c2_pdata = {
48 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
49};
50
51static struct plat_serial8250_port serial_platform_data[] = {
52 [0] = {
53 .mapbase = 0x4500,
54 .irq = MPC83xx_IRQ_UART1,
55 .iotype = UPIO_MEM,
56 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
57 },
58 [1] = {
59 .mapbase = 0x4600,
60 .irq = MPC83xx_IRQ_UART2,
61 .iotype = UPIO_MEM,
62 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
63 },
64 { },
65};
66
67struct platform_device ppc_sys_platform_devices[] = {
68 [MPC83xx_TSEC1] = {
69 .name = "fsl-gianfar",
70 .id = 1,
71 .dev.platform_data = &mpc83xx_tsec1_pdata,
72 .num_resources = 4,
73 .resource = (struct resource[]) {
74 {
75 .start = 0x24000,
76 .end = 0x24fff,
77 .flags = IORESOURCE_MEM,
78 },
79 {
80 .name = "tx",
81 .start = MPC83xx_IRQ_TSEC1_TX,
82 .end = MPC83xx_IRQ_TSEC1_TX,
83 .flags = IORESOURCE_IRQ,
84 },
85 {
86 .name = "rx",
87 .start = MPC83xx_IRQ_TSEC1_RX,
88 .end = MPC83xx_IRQ_TSEC1_RX,
89 .flags = IORESOURCE_IRQ,
90 },
91 {
92 .name = "error",
93 .start = MPC83xx_IRQ_TSEC1_ERROR,
94 .end = MPC83xx_IRQ_TSEC1_ERROR,
95 .flags = IORESOURCE_IRQ,
96 },
97 },
98 },
99 [MPC83xx_TSEC2] = {
100 .name = "fsl-gianfar",
101 .id = 2,
102 .dev.platform_data = &mpc83xx_tsec2_pdata,
103 .num_resources = 4,
104 .resource = (struct resource[]) {
105 {
106 .start = 0x25000,
107 .end = 0x25fff,
108 .flags = IORESOURCE_MEM,
109 },
110 {
111 .name = "tx",
112 .start = MPC83xx_IRQ_TSEC2_TX,
113 .end = MPC83xx_IRQ_TSEC2_TX,
114 .flags = IORESOURCE_IRQ,
115 },
116 {
117 .name = "rx",
118 .start = MPC83xx_IRQ_TSEC2_RX,
119 .end = MPC83xx_IRQ_TSEC2_RX,
120 .flags = IORESOURCE_IRQ,
121 },
122 {
123 .name = "error",
124 .start = MPC83xx_IRQ_TSEC2_ERROR,
125 .end = MPC83xx_IRQ_TSEC2_ERROR,
126 .flags = IORESOURCE_IRQ,
127 },
128 },
129 },
130 [MPC83xx_IIC1] = {
131 .name = "fsl-i2c",
132 .id = 1,
133 .dev.platform_data = &mpc83xx_fsl_i2c1_pdata,
134 .num_resources = 2,
135 .resource = (struct resource[]) {
136 {
137 .start = 0x3000,
138 .end = 0x30ff,
139 .flags = IORESOURCE_MEM,
140 },
141 {
142 .start = MPC83xx_IRQ_IIC1,
143 .end = MPC83xx_IRQ_IIC1,
144 .flags = IORESOURCE_IRQ,
145 },
146 },
147 },
148 [MPC83xx_IIC2] = {
149 .name = "fsl-i2c",
150 .id = 2,
151 .dev.platform_data = &mpc83xx_fsl_i2c2_pdata,
152 .num_resources = 2,
153 .resource = (struct resource[]) {
154 {
155 .start = 0x3100,
156 .end = 0x31ff,
157 .flags = IORESOURCE_MEM,
158 },
159 {
160 .start = MPC83xx_IRQ_IIC2,
161 .end = MPC83xx_IRQ_IIC2,
162 .flags = IORESOURCE_IRQ,
163 },
164 },
165 },
166 [MPC83xx_DUART] = {
167 .name = "serial8250",
168 .id = PLAT8250_DEV_PLATFORM,
169 .dev.platform_data = serial_platform_data,
170 },
171 [MPC83xx_SEC2] = {
172 .name = "fsl-sec2",
173 .id = 1,
174 .num_resources = 2,
175 .resource = (struct resource[]) {
176 {
177 .start = 0x30000,
178 .end = 0x3ffff,
179 .flags = IORESOURCE_MEM,
180 },
181 {
182 .start = MPC83xx_IRQ_SEC2,
183 .end = MPC83xx_IRQ_SEC2,
184 .flags = IORESOURCE_IRQ,
185 },
186 },
187 },
188 [MPC83xx_USB2_DR] = {
189 .name = "fsl-ehci",
190 .id = 1,
191 .num_resources = 2,
192 .resource = (struct resource[]) {
193 {
194 .start = 0x23000,
195 .end = 0x23fff,
196 .flags = IORESOURCE_MEM,
197 },
198 {
199 .start = MPC83xx_IRQ_USB2_DR,
200 .end = MPC83xx_IRQ_USB2_DR,
201 .flags = IORESOURCE_IRQ,
202 },
203 },
204 },
205 [MPC83xx_USB2_MPH] = {
206 .name = "fsl-ehci",
207 .id = 2,
208 .num_resources = 2,
209 .resource = (struct resource[]) {
210 {
211 .start = 0x22000,
212 .end = 0x22fff,
213 .flags = IORESOURCE_MEM,
214 },
215 {
216 .start = MPC83xx_IRQ_USB2_MPH,
217 .end = MPC83xx_IRQ_USB2_MPH,
218 .flags = IORESOURCE_IRQ,
219 },
220 },
221 },
222 [MPC83xx_MDIO] = {
223 .name = "fsl-gianfar_mdio",
224 .id = 0,
225 .dev.platform_data = &mpc83xx_mdio_pdata,
226 .num_resources = 1,
227 .resource = (struct resource[]) {
228 {
229 .start = 0x24520,
230 .end = 0x2453f,
231 .flags = IORESOURCE_MEM,
232 },
233 },
234 },
235};
236
237static int __init mach_mpc83xx_fixup(struct platform_device *pdev)
238{
239 ppc_sys_fixup_mem_resource(pdev, immrbar);
240 return 0;
241}
242
243static int __init mach_mpc83xx_init(void)
244{
245 if (ppc_md.progress)
246 ppc_md.progress("mach_mpc83xx_init:enter", 0);
247 ppc_sys_device_fixup = mach_mpc83xx_fixup;
248 return 0;
249}
250
251postcore_initcall(mach_mpc83xx_init);
diff --git a/arch/ppc/syslib/mpc83xx_sys.c b/arch/ppc/syslib/mpc83xx_sys.c
deleted file mode 100644
index 0498ae7e01e3..000000000000
--- a/arch/ppc/syslib/mpc83xx_sys.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * MPC83xx System descriptions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <asm/ppc_sys.h>
18
19struct ppc_sys_spec *cur_ppc_sys_spec;
20struct ppc_sys_spec ppc_sys_specs[] = {
21 {
22 .ppc_sys_name = "8349E",
23 .mask = 0xFFFF0000,
24 .value = 0x80500000,
25 .num_devices = 9,
26 .device_list = (enum ppc_sys_devices[])
27 {
28 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
29 MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
30 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
31 },
32 },
33 {
34 .ppc_sys_name = "8349",
35 .mask = 0xFFFF0000,
36 .value = 0x80510000,
37 .num_devices = 8,
38 .device_list = (enum ppc_sys_devices[])
39 {
40 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
41 MPC83xx_IIC2, MPC83xx_DUART,
42 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
43 },
44 },
45 {
46 .ppc_sys_name = "8347E",
47 .mask = 0xFFFF0000,
48 .value = 0x80520000,
49 .num_devices = 9,
50 .device_list = (enum ppc_sys_devices[])
51 {
52 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
53 MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
54 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
55 },
56 },
57 {
58 .ppc_sys_name = "8347",
59 .mask = 0xFFFF0000,
60 .value = 0x80530000,
61 .num_devices = 8,
62 .device_list = (enum ppc_sys_devices[])
63 {
64 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
65 MPC83xx_IIC2, MPC83xx_DUART,
66 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
67 },
68 },
69 {
70 .ppc_sys_name = "8347E",
71 .mask = 0xFFFF0000,
72 .value = 0x80540000,
73 .num_devices = 9,
74 .device_list = (enum ppc_sys_devices[])
75 {
76 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
77 MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
78 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
79 },
80 },
81 {
82 .ppc_sys_name = "8347",
83 .mask = 0xFFFF0000,
84 .value = 0x80550000,
85 .num_devices = 8,
86 .device_list = (enum ppc_sys_devices[])
87 {
88 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
89 MPC83xx_IIC2, MPC83xx_DUART,
90 MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
91 },
92 },
93 {
94 .ppc_sys_name = "8343E",
95 .mask = 0xFFFF0000,
96 .value = 0x80560000,
97 .num_devices = 8,
98 .device_list = (enum ppc_sys_devices[])
99 {
100 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
101 MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
102 MPC83xx_USB2_DR, MPC83xx_MDIO
103 },
104 },
105 {
106 .ppc_sys_name = "8343",
107 .mask = 0xFFFF0000,
108 .value = 0x80570000,
109 .num_devices = 7,
110 .device_list = (enum ppc_sys_devices[])
111 {
112 MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
113 MPC83xx_IIC2, MPC83xx_DUART,
114 MPC83xx_USB2_DR, MPC83xx_MDIO
115 },
116 },
117 { /* default match */
118 .ppc_sys_name = "",
119 .mask = 0x00000000,
120 .value = 0x00000000,
121 },
122};
diff --git a/arch/ppc/syslib/ppc83xx_pci.h b/arch/ppc/syslib/ppc83xx_pci.h
deleted file mode 100644
index ec691640f6be..000000000000
--- a/arch/ppc/syslib/ppc83xx_pci.h
+++ /dev/null
@@ -1,151 +0,0 @@
1/* Created by Tony Li <tony.li@freescale.com>
2 * Copyright (c) 2005 freescale semiconductor
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __PPC_SYSLIB_PPC83XX_PCI_H
20#define __PPC_SYSLIB_PPC83XX_PCI_H
21
22typedef struct immr_clk {
23 u32 spmr; /* system PLL mode Register */
24 u32 occr; /* output clock control Register */
25 u32 sccr; /* system clock control Register */
26 u8 res0[0xF4];
27} immr_clk_t;
28
29/*
30 * Sequencer
31 */
32typedef struct immr_ios {
33 u32 potar0;
34 u8 res0[4];
35 u32 pobar0;
36 u8 res1[4];
37 u32 pocmr0;
38 u8 res2[4];
39 u32 potar1;
40 u8 res3[4];
41 u32 pobar1;
42 u8 res4[4];
43 u32 pocmr1;
44 u8 res5[4];
45 u32 potar2;
46 u8 res6[4];
47 u32 pobar2;
48 u8 res7[4];
49 u32 pocmr2;
50 u8 res8[4];
51 u32 potar3;
52 u8 res9[4];
53 u32 pobar3;
54 u8 res10[4];
55 u32 pocmr3;
56 u8 res11[4];
57 u32 potar4;
58 u8 res12[4];
59 u32 pobar4;
60 u8 res13[4];
61 u32 pocmr4;
62 u8 res14[4];
63 u32 potar5;
64 u8 res15[4];
65 u32 pobar5;
66 u8 res16[4];
67 u32 pocmr5;
68 u8 res17[4];
69 u8 res18[0x60];
70 u32 pmcr;
71 u8 res19[4];
72 u32 dtcr;
73 u8 res20[4];
74} immr_ios_t;
75#define POTAR_TA_MASK 0x000fffff
76#define POBAR_BA_MASK 0x000fffff
77#define POCMR_EN 0x80000000
78#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
79#define POCMR_SE 0x20000000 /* streaming enable */
80#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */
81#define POCMR_CM_MASK 0x000fffff
82
83/*
84 * PCI Controller Control and Status Registers
85 */
86typedef struct immr_pcictrl {
87 u32 esr;
88 u32 ecdr;
89 u32 eer;
90 u32 eatcr;
91 u32 eacr;
92 u32 eeacr;
93 u32 edlcr;
94 u32 edhcr;
95 u32 gcr;
96 u32 ecr;
97 u32 gsr;
98 u8 res0[12];
99 u32 pitar2;
100 u8 res1[4];
101 u32 pibar2;
102 u32 piebar2;
103 u32 piwar2;
104 u8 res2[4];
105 u32 pitar1;
106 u8 res3[4];
107 u32 pibar1;
108 u32 piebar1;
109 u32 piwar1;
110 u8 res4[4];
111 u32 pitar0;
112 u8 res5[4];
113 u32 pibar0;
114 u8 res6[4];
115 u32 piwar0;
116 u8 res7[132];
117} immr_pcictrl_t;
118#define PITAR_TA_MASK 0x000fffff
119#define PIBAR_MASK 0xffffffff
120#define PIEBAR_EBA_MASK 0x000fffff
121#define PIWAR_EN 0x80000000
122#define PIWAR_PF 0x20000000
123#define PIWAR_RTT_MASK 0x000f0000
124#define PIWAR_RTT_NO_SNOOP 0x00040000
125#define PIWAR_RTT_SNOOP 0x00050000
126#define PIWAR_WTT_MASK 0x0000f000
127#define PIWAR_WTT_NO_SNOOP 0x00004000
128#define PIWAR_WTT_SNOOP 0x00005000
129#define PIWAR_IWS_MASK 0x0000003F
130#define PIWAR_IWS_4K 0x0000000B
131#define PIWAR_IWS_8K 0x0000000C
132#define PIWAR_IWS_16K 0x0000000D
133#define PIWAR_IWS_32K 0x0000000E
134#define PIWAR_IWS_64K 0x0000000F
135#define PIWAR_IWS_128K 0x00000010
136#define PIWAR_IWS_256K 0x00000011
137#define PIWAR_IWS_512K 0x00000012
138#define PIWAR_IWS_1M 0x00000013
139#define PIWAR_IWS_2M 0x00000014
140#define PIWAR_IWS_4M 0x00000015
141#define PIWAR_IWS_8M 0x00000016
142#define PIWAR_IWS_16M 0x00000017
143#define PIWAR_IWS_32M 0x00000018
144#define PIWAR_IWS_64M 0x00000019
145#define PIWAR_IWS_128M 0x0000001A
146#define PIWAR_IWS_256M 0x0000001B
147#define PIWAR_IWS_512M 0x0000001C
148#define PIWAR_IWS_1G 0x0000001D
149#define PIWAR_IWS_2G 0x0000001E
150
151#endif /* __PPC_SYSLIB_PPC83XX_PCI_H */
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c
deleted file mode 100644
index ea372914dd6e..000000000000
--- a/arch/ppc/syslib/ppc83xx_setup.c
+++ /dev/null
@@ -1,410 +0,0 @@
1/*
2 * MPC83XX common board code
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Added PCI support -- Tony Li <tony.li@freescale.com>
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/pci.h>
29#include <linux/serial.h>
30#include <linux/tty.h> /* for linux/serial_core.h */
31#include <linux/serial_core.h>
32#include <linux/serial_8250.h>
33
34#include <asm/time.h>
35#include <asm/mpc83xx.h>
36#include <asm/mmu.h>
37#include <asm/ppc_sys.h>
38#include <asm/kgdb.h>
39#include <asm/delay.h>
40#include <asm/machdep.h>
41
42#include <syslib/ppc83xx_setup.h>
43#if defined(CONFIG_PCI)
44#include <syslib/ppc83xx_pci.h>
45#endif
46
47phys_addr_t immrbar;
48
49/* Return the amount of memory */
50unsigned long __init
51mpc83xx_find_end_of_memory(void)
52{
53 bd_t *binfo;
54
55 binfo = (bd_t *) __res;
56
57 return binfo->bi_memsize;
58}
59
60long __init
61mpc83xx_time_init(void)
62{
63#define SPCR_OFFS 0x00000110
64#define SPCR_TBEN 0x00400000
65
66 bd_t *binfo = (bd_t *)__res;
67 u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4);
68
69 *spcr |= SPCR_TBEN;
70
71 iounmap(spcr);
72
73 return 0;
74}
75
76/* The decrementer counts at the system (internal) clock freq divided by 4 */
77void __init
78mpc83xx_calibrate_decr(void)
79{
80 bd_t *binfo = (bd_t *) __res;
81 unsigned int freq, divisor;
82
83 freq = binfo->bi_busfreq;
84 divisor = 4;
85 tb_ticks_per_jiffy = freq / HZ / divisor;
86 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
87}
88
89#ifdef CONFIG_SERIAL_8250
90void __init
91mpc83xx_early_serial_map(void)
92{
93#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
94 struct uart_port serial_req;
95#endif
96 struct plat_serial8250_port *pdata;
97 bd_t *binfo = (bd_t *) __res;
98 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART);
99
100 /* Setup serial port access */
101 pdata[0].uartclk = binfo->bi_busfreq;
102 pdata[0].mapbase += binfo->bi_immr_base;
103 pdata[0].membase = ioremap(pdata[0].mapbase, 0x100);
104
105#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
106 memset(&serial_req, 0, sizeof (serial_req));
107 serial_req.iotype = UPIO_MEM;
108 serial_req.mapbase = pdata[0].mapbase;
109 serial_req.membase = pdata[0].membase;
110 serial_req.regshift = 0;
111
112 gen550_init(0, &serial_req);
113#endif
114
115 pdata[1].uartclk = binfo->bi_busfreq;
116 pdata[1].mapbase += binfo->bi_immr_base;
117 pdata[1].membase = ioremap(pdata[1].mapbase, 0x100);
118
119#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
120 /* Assume gen550_init() doesn't modify serial_req */
121 serial_req.mapbase = pdata[1].mapbase;
122 serial_req.membase = pdata[1].membase;
123
124 gen550_init(1, &serial_req);
125#endif
126}
127#endif
128
129void
130mpc83xx_restart(char *cmd)
131{
132 volatile unsigned char __iomem *reg;
133 unsigned char tmp;
134
135 reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
136
137 local_irq_disable();
138
139 /*
140 * Unlock the BCSR bits so a PRST will update the contents.
141 * Otherwise the reset asserts but doesn't clear.
142 */
143 tmp = in_8(reg + BCSR_MISC_REG3_OFF);
144 tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
145 out_8(reg + BCSR_MISC_REG3_OFF, tmp);
146
147 /*
148 * Trigger a reset via a low->high transition of the
149 * PORESET bit.
150 */
151 tmp = in_8(reg + BCSR_MISC_REG2_OFF);
152 tmp &= ~BCSR_MISC_REG2_PORESET;
153 out_8(reg + BCSR_MISC_REG2_OFF, tmp);
154
155 udelay(1);
156
157 tmp |= BCSR_MISC_REG2_PORESET;
158 out_8(reg + BCSR_MISC_REG2_OFF, tmp);
159
160 for(;;);
161}
162
163void
164mpc83xx_power_off(void)
165{
166 local_irq_disable();
167 for(;;);
168}
169
170void
171mpc83xx_halt(void)
172{
173 local_irq_disable();
174 for(;;);
175}
176
177#if defined(CONFIG_PCI)
178void __init
179mpc83xx_setup_pci1(struct pci_controller *hose)
180{
181 u16 reg16;
182 volatile immr_pcictrl_t * pci_ctrl;
183 volatile immr_ios_t * ios;
184 bd_t *binfo = (bd_t *) __res;
185
186 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t));
187 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
188
189 /*
190 * Configure PCI Outbound Translation Windows
191 */
192 ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK;
193 ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK;
194 ios->pocmr0 = POCMR_EN |
195 (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM -
196 MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
197
198 /* mapped to PCI1 IO space */
199 ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK;
200 ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK;
201 ios->pocmr1 = POCMR_EN | POCMR_IO |
202 (((0xffffffff - (MPC83xx_PCI1_UPPER_IO -
203 MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK);
204
205 /*
206 * Configure PCI Inbound Translation Windows
207 */
208 pci_ctrl->pitar1 = 0x0;
209 pci_ctrl->pibar1 = 0x0;
210 pci_ctrl->piebar1 = 0x0;
211 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
212
213 /*
214 * Release PCI RST signal
215 */
216 pci_ctrl->gcr = 0;
217 udelay(2000);
218 pci_ctrl->gcr = 1;
219 udelay(2000);
220
221 reg16 = 0xff;
222 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
223 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
224 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
225
226 /*
227 * Clear non-reserved bits in status register.
228 */
229 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
230 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
231
232 iounmap(pci_ctrl);
233 iounmap(ios);
234}
235
236void __init
237mpc83xx_setup_pci2(struct pci_controller *hose)
238{
239 u16 reg16;
240 volatile immr_pcictrl_t * pci_ctrl;
241 volatile immr_ios_t * ios;
242 bd_t *binfo = (bd_t *) __res;
243
244 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t));
245 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
246
247 /*
248 * Configure PCI Outbound Translation Windows
249 */
250 ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK;
251 ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK;
252 ios->pocmr3 = POCMR_EN | POCMR_DST |
253 (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM -
254 MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
255
256 /* mapped to PCI2 IO space */
257 ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK;
258 ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK;
259 ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO |
260 (((0xffffffff - (MPC83xx_PCI2_UPPER_IO -
261 MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK);
262
263 /*
264 * Configure PCI Inbound Translation Windows
265 */
266 pci_ctrl->pitar1 = 0x0;
267 pci_ctrl->pibar1 = 0x0;
268 pci_ctrl->piebar1 = 0x0;
269 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
270
271 /*
272 * Release PCI RST signal
273 */
274 pci_ctrl->gcr = 0;
275 udelay(2000);
276 pci_ctrl->gcr = 1;
277 udelay(2000);
278
279 reg16 = 0xff;
280 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
281 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
282 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
283
284 /*
285 * Clear non-reserved bits in status register.
286 */
287 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
288 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
289
290 iounmap(pci_ctrl);
291 iounmap(ios);
292}
293
294/*
295 * PCI buses can be enabled only if SYS board combinates with PIB
296 * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses
297 * and 3 PCI slots, so people must configure the routes between them before
298 * enable PCI bus. This routes are under the control of PCA9555PW device which
299 * can be accessed via I2C bus 2 and are configured by firmware. Refer to
300 * Freescale to get more information about firmware configuration.
301 */
302
303extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
304extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel,
305 unsigned char pin);
306void __init
307mpc83xx_setup_hose(void)
308{
309 u32 val32;
310 volatile immr_clk_t * clk;
311 struct pci_controller * hose1;
312#ifdef CONFIG_MPC83xx_PCI2
313 struct pci_controller * hose2;
314#endif
315 bd_t * binfo = (bd_t *)__res;
316
317 clk = ioremap(binfo->bi_immr_base + 0xA00,
318 sizeof(immr_clk_t));
319
320 /*
321 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
322 */
323 val32 = clk->occr;
324 udelay(2000);
325 clk->occr = 0xff000000;
326 udelay(2000);
327
328 iounmap(clk);
329
330 hose1 = pcibios_alloc_controller();
331 if(!hose1)
332 return;
333
334 ppc_md.pci_swizzle = common_swizzle;
335 ppc_md.pci_map_irq = mpc83xx_map_irq;
336
337 hose1->bus_offset = 0;
338 hose1->first_busno = 0;
339 hose1->last_busno = 0xff;
340
341 setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
342 binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
343 hose1->set_cfg_type = 1;
344
345 mpc83xx_setup_pci1(hose1);
346
347 hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
348 hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
349 hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
350
351 hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
352 hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
353 hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
354#ifdef CONFIG_MPC83xx_PCI2
355 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
356 MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
357#else
358 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
359 MPC83xx_PCI1_IO_SIZE);
360#endif /* CONFIG_MPC83xx_PCI2 */
361 hose1->io_base_virt = (void *)isa_io_base;
362 /* setup resources */
363 pci_init_resource(&hose1->io_resource,
364 MPC83xx_PCI1_LOWER_IO,
365 MPC83xx_PCI1_UPPER_IO,
366 IORESOURCE_IO, "PCI host bridge 1");
367 pci_init_resource(&hose1->mem_resources[0],
368 MPC83xx_PCI1_LOWER_MEM,
369 MPC83xx_PCI1_UPPER_MEM,
370 IORESOURCE_MEM, "PCI host bridge 1");
371
372 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
373 hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
374
375#ifdef CONFIG_MPC83xx_PCI2
376 hose2 = pcibios_alloc_controller();
377 if(!hose2)
378 return;
379
380 hose2->bus_offset = hose1->last_busno + 1;
381 hose2->first_busno = hose1->last_busno + 1;
382 hose2->last_busno = 0xff;
383 setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
384 binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
385 hose2->set_cfg_type = 1;
386
387 mpc83xx_setup_pci2(hose2);
388
389 hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
390 hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
391 hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
392
393 hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
394 hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
395 hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
396 hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
397 /* setup resources */
398 pci_init_resource(&hose2->io_resource,
399 MPC83xx_PCI2_LOWER_IO,
400 MPC83xx_PCI2_UPPER_IO,
401 IORESOURCE_IO, "PCI host bridge 2");
402 pci_init_resource(&hose2->mem_resources[0],
403 MPC83xx_PCI2_LOWER_MEM,
404 MPC83xx_PCI2_UPPER_MEM,
405 IORESOURCE_MEM, "PCI host bridge 2");
406
407 hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
408#endif /* CONFIG_MPC83xx_PCI2 */
409}
410#endif /*CONFIG_PCI*/
diff --git a/arch/ppc/syslib/ppc83xx_setup.h b/arch/ppc/syslib/ppc83xx_setup.h
deleted file mode 100644
index b918a2d245ea..000000000000
--- a/arch/ppc/syslib/ppc83xx_setup.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * MPC83XX common board definitions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __PPC_SYSLIB_PPC83XX_SETUP_H
24#define __PPC_SYSLIB_PPC83XX_SETUP_H
25
26#include <linux/init.h>
27
28extern unsigned long mpc83xx_find_end_of_memory(void) __init;
29extern long mpc83xx_time_init(void) __init;
30extern void mpc83xx_calibrate_decr(void) __init;
31extern void mpc83xx_early_serial_map(void) __init;
32extern void mpc83xx_restart(char *cmd);
33extern void mpc83xx_power_off(void);
34extern void mpc83xx_halt(void);
35extern void mpc83xx_setup_hose(void) __init;
36
37/* PCI config */
38#define PCI1_CFG_ADDR_OFFSET (0x8300)
39#define PCI1_CFG_DATA_OFFSET (0x8304)
40
41#define PCI2_CFG_ADDR_OFFSET (0x8380)
42#define PCI2_CFG_DATA_OFFSET (0x8384)
43
44/* Serial Config */
45#ifdef CONFIG_SERIAL_MANY_PORTS
46#define RS_TABLE_SIZE 64
47#else
48#define RS_TABLE_SIZE 2
49#endif
50
51#ifndef BASE_BAUD
52#define BASE_BAUD 115200
53#endif
54
55#endif /* __PPC_SYSLIB_PPC83XX_SETUP_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 20:02:12 -0500