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authorLen Brown <len.brown@intel.com>2005-09-08 01:45:47 -0400
committerLen Brown <len.brown@intel.com>2005-09-08 01:45:47 -0400
commit64e47488c913ac704d465a6af86a26786d1412a5 (patch)
treed3b0148592963dcde26e4bb35ddfec8b1eaf8e23 /arch/ppc/syslib
parent4a35a46bf1cda4737c428380d1db5d15e2590d18 (diff)
parentcaf39e87cc1182f7dae84eefc43ca14d54c78ef9 (diff)
Merge linux-2.6 with linux-acpi-2.6
Diffstat (limited to 'arch/ppc/syslib')
-rw-r--r--arch/ppc/syslib/Makefile12
-rw-r--r--arch/ppc/syslib/mv64360_pic.c31
-rw-r--r--arch/ppc/syslib/mv64x60.c246
-rw-r--r--arch/ppc/syslib/ocp.c2
-rw-r--r--arch/ppc/syslib/of_device.c2
-rw-r--r--arch/ppc/syslib/open_pic.c2
-rw-r--r--arch/ppc/syslib/ppc4xx_setup.c27
-rw-r--r--arch/ppc/syslib/ppc83xx_pci.h151
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.c250
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.h19
-rw-r--r--arch/ppc/syslib/ppc_sys.c52
-rw-r--r--arch/ppc/syslib/pq2_devices.c389
-rw-r--r--arch/ppc/syslib/pq2_sys.c200
13 files changed, 1227 insertions, 156 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 220a65ab0a51..8b9b226005d1 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -43,8 +43,6 @@ obj-$(CONFIG_PPC_PMAC) += open_pic.o indirect_pci.o
43obj-$(CONFIG_POWER4) += open_pic2.o 43obj-$(CONFIG_POWER4) += open_pic2.o
44obj-$(CONFIG_PPC_CHRP) += open_pic.o indirect_pci.o i8259.o 44obj-$(CONFIG_PPC_CHRP) += open_pic.o indirect_pci.o i8259.o
45obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o 45obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
46obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
47 todc_time.o
48obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o 46obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o
49obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o 47obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
50obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o 48obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
@@ -52,16 +50,10 @@ obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
52obj-$(CONFIG_CHESTNUT) += mv64360_pic.o pci_auto.o 50obj-$(CONFIG_CHESTNUT) += mv64360_pic.o pci_auto.o
53obj-$(CONFIG_GEMINI) += open_pic.o indirect_pci.o 51obj-$(CONFIG_GEMINI) += open_pic.o indirect_pci.o
54obj-$(CONFIG_GT64260) += gt64260_pic.o 52obj-$(CONFIG_GT64260) += gt64260_pic.o
55obj-$(CONFIG_K2) += i8259.o indirect_pci.o todc_time.o \
56 pci_auto.o
57obj-$(CONFIG_LOPEC) += i8259.o pci_auto.o todc_time.o 53obj-$(CONFIG_LOPEC) += i8259.o pci_auto.o todc_time.o
58obj-$(CONFIG_HDPU) += pci_auto.o 54obj-$(CONFIG_HDPU) += pci_auto.o
59obj-$(CONFIG_LUAN) += indirect_pci.o pci_auto.o todc_time.o 55obj-$(CONFIG_LUAN) += indirect_pci.o pci_auto.o todc_time.o
60obj-$(CONFIG_KATANA) += pci_auto.o 56obj-$(CONFIG_KATANA) += pci_auto.o
61obj-$(CONFIG_MCPN765) += todc_time.o indirect_pci.o pci_auto.o \
62 open_pic.o i8259.o hawk_common.o
63obj-$(CONFIG_MENF1) += todc_time.o i8259.o mpc10x_common.o \
64 pci_auto.o indirect_pci.o
65obj-$(CONFIG_MV64360) += mv64360_pic.o 57obj-$(CONFIG_MV64360) += mv64360_pic.o
66obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o indirect_pci.o 58obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o indirect_pci.o
67obj-$(CONFIG_MVME5100) += open_pic.o todc_time.o indirect_pci.o \ 59obj-$(CONFIG_MVME5100) += open_pic.o todc_time.o indirect_pci.o \
@@ -69,7 +61,6 @@ obj-$(CONFIG_MVME5100) += open_pic.o todc_time.o indirect_pci.o \
69obj-$(CONFIG_MVME5100_IPMC761_PRESENT) += i8259.o 61obj-$(CONFIG_MVME5100_IPMC761_PRESENT) += i8259.o
70obj-$(CONFIG_OCOTEA) += indirect_pci.o pci_auto.o todc_time.o 62obj-$(CONFIG_OCOTEA) += indirect_pci.o pci_auto.o todc_time.o
71obj-$(CONFIG_PAL4) += cpc700_pic.o 63obj-$(CONFIG_PAL4) += cpc700_pic.o
72obj-$(CONFIG_PCORE) += todc_time.o i8259.o pci_auto.o
73obj-$(CONFIG_POWERPMC250) += pci_auto.o 64obj-$(CONFIG_POWERPMC250) += pci_auto.o
74obj-$(CONFIG_PPLUS) += hawk_common.o open_pic.o i8259.o \ 65obj-$(CONFIG_PPLUS) += hawk_common.o open_pic.o i8259.o \
75 indirect_pci.o todc_time.o pci_auto.o 66 indirect_pci.o todc_time.o pci_auto.o
@@ -82,7 +73,8 @@ obj-$(CONFIG_SANDPOINT) += i8259.o pci_auto.o todc_time.o
82obj-$(CONFIG_SBC82xx) += todc_time.o 73obj-$(CONFIG_SBC82xx) += todc_time.o
83obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \ 74obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
84 todc_time.o 75 todc_time.o
85obj-$(CONFIG_8260) += m8260_setup.o 76obj-$(CONFIG_8260) += m8260_setup.o pq2_devices.o pq2_sys.o \
77 ppc_sys.o
86obj-$(CONFIG_PCI_8260) += m82xx_pci.o indirect_pci.o pci_auto.o 78obj-$(CONFIG_PCI_8260) += m82xx_pci.o indirect_pci.o pci_auto.o
87obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o 79obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o
88obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o 80obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
diff --git a/arch/ppc/syslib/mv64360_pic.c b/arch/ppc/syslib/mv64360_pic.c
index 74d8996418e9..8356da4678a2 100644
--- a/arch/ppc/syslib/mv64360_pic.c
+++ b/arch/ppc/syslib/mv64360_pic.c
@@ -366,10 +366,16 @@ mv64360_pci_error_int_handler(int irq, void *dev_id, struct pt_regs *regs)
366 return IRQ_HANDLED; 366 return IRQ_HANDLED;
367} 367}
368 368
369/*
370 * Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of
371 * errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as
372 * well. IOW, don't set bit 0.
373 */
374#define MV64360_PCI0_ERR_MASK_VAL 0x00a50c24
375
369static int __init 376static int __init
370mv64360_register_hdlrs(void) 377mv64360_register_hdlrs(void)
371{ 378{
372 u32 mask;
373 int rc; 379 int rc;
374 380
375 /* Clear old errors and register CPU interface error intr handler */ 381 /* Clear old errors and register CPU interface error intr handler */
@@ -387,17 +393,6 @@ mv64360_register_hdlrs(void)
387 mv64360_sram_error_int_handler,SA_INTERRUPT,SRAM_INTR_STR, 0))) 393 mv64360_sram_error_int_handler,SA_INTERRUPT,SRAM_INTR_STR, 0)))
388 printk(KERN_WARNING "Can't register SRAM error handler: %d",rc); 394 printk(KERN_WARNING "Can't register SRAM error handler: %d",rc);
389 395
390 /*
391 * Bit 0 reserved on 64360 and erratum FEr PCI-#11 (PCI internal
392 * data parity error set incorrectly) on rev 0 & 1 of 64460 requires
393 * bit 0 to be cleared.
394 */
395 mask = 0x00a50c24;
396
397 if ((mv64x60_get_bridge_type() == MV64x60_TYPE_MV64460) &&
398 (mv64x60_get_bridge_rev() > 1))
399 mask |= 0x1; /* enable DPErr on 64460 */
400
401 /* Clear old errors and register PCI 0 error intr handler */ 396 /* Clear old errors and register PCI 0 error intr handler */
402 mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0); 397 mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0);
403 if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base, 398 if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base,
@@ -407,7 +402,11 @@ mv64360_register_hdlrs(void)
407 rc); 402 rc);
408 403
409 mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0); 404 mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
410 mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, mask); 405 mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL);
406
407 /* Erratum FEr PCI-#16 says to clear bit 0 of PCI SERRn Mask reg. */
408 mv64x60_write(&bh, MV64x60_PCI0_ERR_SERR_MASK,
409 mv64x60_read(&bh, MV64x60_PCI0_ERR_SERR_MASK) & ~0x1UL);
411 410
412 /* Clear old errors and register PCI 1 error intr handler */ 411 /* Clear old errors and register PCI 1 error intr handler */
413 mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0); 412 mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0);
@@ -418,7 +417,11 @@ mv64360_register_hdlrs(void)
418 rc); 417 rc);
419 418
420 mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0); 419 mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
421 mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, mask); 420 mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL);
421
422 /* Erratum FEr PCI-#16 says to clear bit 0 of PCI Intr Mask reg. */
423 mv64x60_write(&bh, MV64x60_PCI1_ERR_SERR_MASK,
424 mv64x60_read(&bh, MV64x60_PCI1_ERR_SERR_MASK) & ~0x1UL);
422 425
423 return 0; 426 return 0;
424} 427}
diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c
index cc77177fa1c6..6262b11f366f 100644
--- a/arch/ppc/syslib/mv64x60.c
+++ b/arch/ppc/syslib/mv64x60.c
@@ -30,13 +30,16 @@
30#include <asm/mv64x60.h> 30#include <asm/mv64x60.h>
31 31
32 32
33u8 mv64x60_pci_exclude_bridge = 1; 33u8 mv64x60_pci_exclude_bridge = 1;
34spinlock_t mv64x60_lock = SPIN_LOCK_UNLOCKED; 34spinlock_t mv64x60_lock = SPIN_LOCK_UNLOCKED;
35 35
36static phys_addr_t mv64x60_bridge_pbase = 0; 36static phys_addr_t mv64x60_bridge_pbase;
37static void *mv64x60_bridge_vbase = 0; 37static void *mv64x60_bridge_vbase;
38static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID; 38static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID;
39static u32 mv64x60_bridge_rev = 0; 39static u32 mv64x60_bridge_rev;
40#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
41static struct pci_controller sysfs_hose_a;
42#endif
40 43
41static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits); 44static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
42static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits); 45static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
@@ -432,6 +435,20 @@ static struct platform_device i2c_device = {
432}; 435};
433#endif 436#endif
434 437
438#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
439static struct mv64xxx_pdata mv64xxx_pdata = {
440 .hs_reg_valid = 0,
441};
442
443static struct platform_device mv64xxx_device = { /* general mv64x60 stuff */
444 .name = MV64XXX_DEV_NAME,
445 .id = 0,
446 .dev = {
447 .platform_data = &mv64xxx_pdata,
448 },
449};
450#endif
451
435static struct platform_device *mv64x60_pd_devs[] __initdata = { 452static struct platform_device *mv64x60_pd_devs[] __initdata = {
436#ifdef CONFIG_SERIAL_MPSC 453#ifdef CONFIG_SERIAL_MPSC
437 &mpsc_shared_device, 454 &mpsc_shared_device,
@@ -453,6 +470,9 @@ static struct platform_device *mv64x60_pd_devs[] __initdata = {
453#ifdef CONFIG_I2C_MV64XXX 470#ifdef CONFIG_I2C_MV64XXX
454 &i2c_device, 471 &i2c_device,
455#endif 472#endif
473#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
474 &mv64xxx_device,
475#endif
456}; 476};
457 477
458/* 478/*
@@ -574,6 +594,11 @@ mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
574 bh->hose_a = &hose_a; 594 bh->hose_a = &hose_a;
575 bh->hose_b = &hose_b; 595 bh->hose_b = &hose_b;
576 596
597#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
598 /* Save a copy of hose_a for sysfs functions -- hack */
599 memcpy(&sysfs_hose_a, &hose_a, sizeof(hose_a));
600#endif
601
577 mv64x60_set_bus(bh, 0, 0); 602 mv64x60_set_bus(bh, 0, 0);
578 mv64x60_set_bus(bh, 1, 0); 603 mv64x60_set_bus(bh, 1, 0);
579 604
@@ -590,8 +615,6 @@ mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
590 615
591 mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff); 616 mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff);
592 mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff); 617 mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff);
593
594 return;
595} 618}
596 619
597/* 620/*
@@ -628,19 +651,15 @@ mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
628 val = mv64x60_read(bh, size_reg); 651 val = mv64x60_read(bh, size_reg);
629 val = get_from_field(val, size_bits); 652 val = get_from_field(val, size_bits);
630 *size = bh->ci->untranslate_size(*base, val, size_bits); 653 *size = bh->ci->untranslate_size(*base, val, size_bits);
631 } 654 } else
632 else
633 *size = 0; 655 *size = 0;
634 } 656 } else {
635 else {
636 *base = 0; 657 *base = 0;
637 *size = 0; 658 *size = 0;
638 } 659 }
639 660
640 pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n", 661 pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
641 window, *base, *size); 662 window, *base, *size);
642
643 return;
644} 663}
645 664
646/* 665/*
@@ -677,8 +696,6 @@ mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window,
677 696
678 (void)mv64x60_read(bh, base_reg); /* Flush FIFO */ 697 (void)mv64x60_read(bh, base_reg); /* Flush FIFO */
679 } 698 }
680
681 return;
682} 699}
683 700
684/* 701/*
@@ -712,11 +729,9 @@ mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
712 val = get_from_field(val, size_bits); 729 val = get_from_field(val, size_bits);
713 *size = bh->ci->untranslate_size(*base_lo, val, 730 *size = bh->ci->untranslate_size(*base_lo, val,
714 size_bits); 731 size_bits);
715 } 732 } else
716 else
717 *size = 0; 733 *size = 0;
718 } 734 } else {
719 else {
720 *base_hi = 0; 735 *base_hi = 0;
721 *base_lo = 0; 736 *base_lo = 0;
722 *size = 0; 737 *size = 0;
@@ -724,8 +739,6 @@ mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
724 739
725 pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, " 740 pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
726 "size: 0x%x\n", window, *base_hi, *base_lo, *size); 741 "size: 0x%x\n", window, *base_hi, *base_lo, *size);
727
728 return;
729} 742}
730 743
731/* 744/*
@@ -766,8 +779,6 @@ mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
766 779
767 (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */ 780 (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */
768 } 781 }
769
770 return;
771} 782}
772 783
773/* 784/*
@@ -1008,8 +1019,6 @@ mv64x60_get_mem_windows(struct mv64x60_handle *bh,
1008 mem_windows[i][0] = 0; 1019 mem_windows[i][0] = 0;
1009 mem_windows[i][1] = 0; 1020 mem_windows[i][1] = 0;
1010 } 1021 }
1011
1012 return;
1013} 1022}
1014 1023
1015/* 1024/*
@@ -1077,8 +1086,6 @@ mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
1077 } 1086 }
1078 1087
1079 } 1088 }
1080
1081 return;
1082} 1089}
1083 1090
1084/* 1091/*
@@ -1112,8 +1119,7 @@ mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
1112 mv64x60_set_32bit_window(bh, remap_tab[bus][0], 1119 mv64x60_set_32bit_window(bh, remap_tab[bus][0],
1113 pi->pci_io.pci_base_lo, 0, 0); 1120 pi->pci_io.pci_base_lo, 0, 0);
1114 bh->ci->enable_window_32bit(bh, win_tab[bus][0]); 1121 bh->ci->enable_window_32bit(bh, win_tab[bus][0]);
1115 } 1122 } else /* Actually, the window should already be disabled */
1116 else /* Actually, the window should already be disabled */
1117 bh->ci->disable_window_32bit(bh, win_tab[bus][0]); 1123 bh->ci->disable_window_32bit(bh, win_tab[bus][0]);
1118 1124
1119 for (i=0; i<3; i++) 1125 for (i=0; i<3; i++)
@@ -1125,11 +1131,8 @@ mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
1125 pi->pci_mem[i].pci_base_hi, 1131 pi->pci_mem[i].pci_base_hi,
1126 pi->pci_mem[i].pci_base_lo, 0, 0); 1132 pi->pci_mem[i].pci_base_lo, 0, 0);
1127 bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]); 1133 bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]);
1128 } 1134 } else /* Actually, the window should already be disabled */
1129 else /* Actually, the window should already be disabled */
1130 bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]); 1135 bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]);
1131
1132 return;
1133} 1136}
1134 1137
1135/* 1138/*
@@ -1206,8 +1209,6 @@ mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
1206 MV64x60_PCI0_BAR_ENABLE : 1209 MV64x60_PCI0_BAR_ENABLE :
1207 MV64x60_PCI1_BAR_ENABLE), (1 << i)); 1210 MV64x60_PCI1_BAR_ENABLE), (1 << i));
1208 } 1211 }
1209
1210 return;
1211} 1212}
1212 1213
1213/* 1214/*
@@ -1229,7 +1230,6 @@ mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data,
1229 *hose = pcibios_alloc_controller(); 1230 *hose = pcibios_alloc_controller();
1230 setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr, 1231 setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr,
1231 bh->v_base + cfg_data); 1232 bh->v_base + cfg_data);
1232 return;
1233} 1233}
1234 1234
1235/* 1235/*
@@ -1272,7 +1272,6 @@ mv64x60_config_resources(struct pci_controller *hose,
1272 pi->pci_mem[0].size - 1; 1272 pi->pci_mem[0].size - 1;
1273 hose->pci_mem_offset = pi->pci_mem[0].cpu_base - 1273 hose->pci_mem_offset = pi->pci_mem[0].cpu_base -
1274 pi->pci_mem[0].pci_base_lo; 1274 pi->pci_mem[0].pci_base_lo;
1275 return;
1276} 1275}
1277 1276
1278/* 1277/*
@@ -1309,7 +1308,6 @@ mv64x60_config_pci_params(struct pci_controller *hose,
1309 early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val); 1308 early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val);
1310 1309
1311 mv64x60_pci_exclude_bridge = save_exclude; 1310 mv64x60_pci_exclude_bridge = save_exclude;
1312 return;
1313} 1311}
1314 1312
1315/* 1313/*
@@ -1336,8 +1334,7 @@ mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus)
1336 p2p_cfg = MV64x60_PCI0_P2P_CONFIG; 1334 p2p_cfg = MV64x60_PCI0_P2P_CONFIG;
1337 pci_cfg_offset = 0x64; 1335 pci_cfg_offset = 0x64;
1338 hose = bh->hose_a; 1336 hose = bh->hose_a;
1339 } 1337 } else {
1340 else {
1341 pci_mode = bh->pci_mode_b; 1338 pci_mode = bh->pci_mode_b;
1342 p2p_cfg = MV64x60_PCI1_P2P_CONFIG; 1339 p2p_cfg = MV64x60_PCI1_P2P_CONFIG;
1343 pci_cfg_offset = 0xe4; 1340 pci_cfg_offset = 0xe4;
@@ -1352,8 +1349,7 @@ mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus)
1352 val |= (child_bus << 16) | 0xff; 1349 val |= (child_bus << 16) | 0xff;
1353 mv64x60_write(bh, p2p_cfg, val); 1350 mv64x60_write(bh, p2p_cfg, val);
1354 (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */ 1351 (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */
1355 } 1352 } else { /* PCI-X */
1356 else { /* PCI-X */
1357 /* 1353 /*
1358 * Need to use the current bus/dev number (that's in the 1354 * Need to use the current bus/dev number (that's in the
1359 * P2P CONFIG reg) to access the bridge's pci config space. 1355 * P2P CONFIG reg) to access the bridge's pci config space.
@@ -1365,8 +1361,6 @@ mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus)
1365 pci_cfg_offset, child_bus << 8); 1361 pci_cfg_offset, child_bus << 8);
1366 mv64x60_pci_exclude_bridge = save_exclude; 1362 mv64x60_pci_exclude_bridge = save_exclude;
1367 } 1363 }
1368
1369 return;
1370} 1364}
1371 1365
1372/* 1366/*
@@ -1423,8 +1417,6 @@ mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[],
1423 j++; 1417 j++;
1424 } 1418 }
1425 } 1419 }
1426
1427 return;
1428} 1420}
1429 1421
1430/* 1422/*
@@ -1498,8 +1490,6 @@ gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1498 early_write_config_dword(hose, 0, PCI_DEVFN(0, 0), 1490 early_write_config_dword(hose, 0, PCI_DEVFN(0, 0),
1499 gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8); 1491 gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8);
1500 mv64x60_pci_exclude_bridge = save_exclude; 1492 mv64x60_pci_exclude_bridge = save_exclude;
1501
1502 return;
1503} 1493}
1504 1494
1505/* 1495/*
@@ -1523,8 +1513,6 @@ gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
1523 early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus], 1513 early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus],
1524 (base << 16)); 1514 (base << 16));
1525 mv64x60_pci_exclude_bridge = save_exclude; 1515 mv64x60_pci_exclude_bridge = save_exclude;
1526
1527 return;
1528} 1516}
1529 1517
1530/* 1518/*
@@ -1561,7 +1549,6 @@ static void __init
1561gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window) 1549gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
1562{ 1550{
1563 pr_debug("enable 32bit window: %d\n", window); 1551 pr_debug("enable 32bit window: %d\n", window);
1564 return;
1565} 1552}
1566 1553
1567/* 1554/*
@@ -1584,8 +1571,6 @@ gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
1584 mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff); 1571 mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff);
1585 mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0); 1572 mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0);
1586 } 1573 }
1587
1588 return;
1589} 1574}
1590 1575
1591/* 1576/*
@@ -1599,7 +1584,6 @@ static void __init
1599gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window) 1584gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
1600{ 1585{
1601 pr_debug("enable 64bit window: %d\n", window); 1586 pr_debug("enable 64bit window: %d\n", window);
1602 return; /* Enabled when window configured (i.e., when top >= base) */
1603} 1587}
1604 1588
1605/* 1589/*
@@ -1624,8 +1608,6 @@ gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
1624 mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0); 1608 mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0);
1625 mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0); 1609 mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0);
1626 } 1610 }
1627
1628 return;
1629} 1611}
1630 1612
1631/* 1613/*
@@ -1712,8 +1694,6 @@ gt64260_disable_all_windows(struct mv64x60_handle *bh,
1712 mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0); 1694 mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0);
1713 mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0); 1695 mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0);
1714 mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0); 1696 mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0);
1715
1716 return;
1717} 1697}
1718 1698
1719/* 1699/*
@@ -1781,14 +1761,11 @@ gt64260a_chip_specific_init(struct mv64x60_handle *bh,
1781 mv64x60_mpsc1_pdata.cache_mgmt = 1; 1761 mv64x60_mpsc1_pdata.cache_mgmt = 1;
1782 1762
1783 if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0)) 1763 if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1784 != NULL) { 1764 != NULL) {
1785
1786 r->start = MV64x60_IRQ_SDMA_0; 1765 r->start = MV64x60_IRQ_SDMA_0;
1787 r->end = MV64x60_IRQ_SDMA_0; 1766 r->end = MV64x60_IRQ_SDMA_0;
1788 } 1767 }
1789#endif 1768#endif
1790
1791 return;
1792} 1769}
1793 1770
1794/* 1771/*
@@ -1861,14 +1838,11 @@ gt64260b_chip_specific_init(struct mv64x60_handle *bh,
1861 mv64x60_mpsc1_pdata.cache_mgmt = 1; 1838 mv64x60_mpsc1_pdata.cache_mgmt = 1;
1862 1839
1863 if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0)) 1840 if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
1864 != NULL) { 1841 != NULL) {
1865
1866 r->start = MV64x60_IRQ_SDMA_0; 1842 r->start = MV64x60_IRQ_SDMA_0;
1867 r->end = MV64x60_IRQ_SDMA_0; 1843 r->end = MV64x60_IRQ_SDMA_0;
1868 } 1844 }
1869#endif 1845#endif
1870
1871 return;
1872} 1846}
1873 1847
1874/* 1848/*
@@ -1945,8 +1919,6 @@ mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
1945 mv64360_reg_addrs[bus][window].base_lo_bar, 1919 mv64360_reg_addrs[bus][window].base_lo_bar,
1946 mv64x60_mask(base,20) | 0xc); 1920 mv64x60_mask(base,20) | 0xc);
1947 mv64x60_pci_exclude_bridge = save_exclude; 1921 mv64x60_pci_exclude_bridge = save_exclude;
1948
1949 return;
1950} 1922}
1951 1923
1952/* 1924/*
@@ -1972,8 +1944,6 @@ mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
1972 early_write_config_dword(hose, 0, PCI_DEVFN(0,0), 1944 early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
1973 mv64360_offset[bus][1], 0); 1945 mv64360_offset[bus][1], 0);
1974 mv64x60_pci_exclude_bridge = save_exclude; 1946 mv64x60_pci_exclude_bridge = save_exclude;
1975
1976 return;
1977} 1947}
1978 1948
1979/* 1949/*
@@ -2082,8 +2052,6 @@ mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
2082 "32bit table corrupted"); 2052 "32bit table corrupted");
2083 } 2053 }
2084 } 2054 }
2085
2086 return;
2087} 2055}
2088 2056
2089/* 2057/*
@@ -2139,8 +2107,6 @@ mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
2139 "32bit table corrupted"); 2107 "32bit table corrupted");
2140 } 2108 }
2141 } 2109 }
2142
2143 return;
2144} 2110}
2145 2111
2146/* 2112/*
@@ -2158,8 +2124,7 @@ mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
2158 (mv64360_64bit_windows[window].size_reg != 0)) { 2124 (mv64360_64bit_windows[window].size_reg != 0)) {
2159 2125
2160 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK) 2126 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2161 == MV64x60_EXTRA_PCIACC_ENAB) 2127 == MV64x60_EXTRA_PCIACC_ENAB)
2162
2163 mv64x60_set_bits(bh, 2128 mv64x60_set_bits(bh,
2164 mv64360_64bit_windows[window].base_lo_reg, 2129 mv64360_64bit_windows[window].base_lo_reg,
2165 (1 << (mv64360_64bit_windows[window].extra & 2130 (1 << (mv64360_64bit_windows[window].extra &
@@ -2168,8 +2133,6 @@ mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
2168 printk(KERN_ERR "mv64360_enable: %s\n", 2133 printk(KERN_ERR "mv64360_enable: %s\n",
2169 "64bit table corrupted"); 2134 "64bit table corrupted");
2170 } 2135 }
2171
2172 return;
2173} 2136}
2174 2137
2175/* 2138/*
@@ -2186,11 +2149,9 @@ mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
2186 mv64360_64bit_windows[window].size_reg); 2149 mv64360_64bit_windows[window].size_reg);
2187 2150
2188 if ((mv64360_64bit_windows[window].base_lo_reg != 0) && 2151 if ((mv64360_64bit_windows[window].base_lo_reg != 0) &&
2189 (mv64360_64bit_windows[window].size_reg != 0)) { 2152 (mv64360_64bit_windows[window].size_reg != 0)) {
2190
2191 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK) 2153 if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
2192 == MV64x60_EXTRA_PCIACC_ENAB) 2154 == MV64x60_EXTRA_PCIACC_ENAB)
2193
2194 mv64x60_clr_bits(bh, 2155 mv64x60_clr_bits(bh,
2195 mv64360_64bit_windows[window].base_lo_reg, 2156 mv64360_64bit_windows[window].base_lo_reg,
2196 (1 << (mv64360_64bit_windows[window].extra & 2157 (1 << (mv64360_64bit_windows[window].extra &
@@ -2199,8 +2160,6 @@ mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
2199 printk(KERN_ERR "mv64360_disable: %s\n", 2160 printk(KERN_ERR "mv64360_disable: %s\n",
2200 "64bit table corrupted"); 2161 "64bit table corrupted");
2201 } 2162 }
2202
2203 return;
2204} 2163}
2205 2164
2206/* 2165/*
@@ -2241,8 +2200,6 @@ mv64360_disable_all_windows(struct mv64x60_handle *bh,
2241 /* Disable all PCI-><whatever> windows */ 2200 /* Disable all PCI-><whatever> windows */
2242 mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff); 2201 mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff);
2243 mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff); 2202 mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff);
2244
2245 return;
2246} 2203}
2247 2204
2248/* 2205/*
@@ -2335,8 +2292,6 @@ mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
2335 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3, 2292 mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3,
2336 (0x3 << (i << 1))); 2293 (0x3 << (i << 1)));
2337 } 2294 }
2338
2339 return;
2340} 2295}
2341 2296
2342/* 2297/*
@@ -2350,42 +2305,145 @@ static void __init
2350mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base) 2305mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base)
2351{ 2306{
2352 pr_debug("set mpsc->internal regs, base: 0x%x\n", base); 2307 pr_debug("set mpsc->internal regs, base: 0x%x\n", base);
2353
2354 mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000); 2308 mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000);
2355 return;
2356} 2309}
2357 2310
2358/* 2311/*
2359 * mv64360_chip_specific_init() 2312 * mv64360_chip_specific_init()
2360 * 2313 *
2361 * No errata work arounds for the MV64360 implemented at this point. 2314 * Implement errata work arounds for the MV64360.
2362 */ 2315 */
2363static void __init 2316static void __init
2364mv64360_chip_specific_init(struct mv64x60_handle *bh, 2317mv64360_chip_specific_init(struct mv64x60_handle *bh,
2365 struct mv64x60_setup_info *si) 2318 struct mv64x60_setup_info *si)
2366{ 2319{
2320#if !defined(CONFIG_NOT_COHERENT_CACHE)
2321 mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24));
2322#endif
2367#ifdef CONFIG_SERIAL_MPSC 2323#ifdef CONFIG_SERIAL_MPSC
2368 mv64x60_mpsc0_pdata.brg_can_tune = 1; 2324 mv64x60_mpsc0_pdata.brg_can_tune = 1;
2369 mv64x60_mpsc0_pdata.cache_mgmt = 1; 2325 mv64x60_mpsc0_pdata.cache_mgmt = 1;
2370 mv64x60_mpsc1_pdata.brg_can_tune = 1; 2326 mv64x60_mpsc1_pdata.brg_can_tune = 1;
2371 mv64x60_mpsc1_pdata.cache_mgmt = 1; 2327 mv64x60_mpsc1_pdata.cache_mgmt = 1;
2372#endif 2328#endif
2373
2374 return;
2375} 2329}
2376 2330
2377/* 2331/*
2378 * mv64460_chip_specific_init() 2332 * mv64460_chip_specific_init()
2379 * 2333 *
2380 * No errata work arounds for the MV64460 implemented at this point. 2334 * Implement errata work arounds for the MV64460.
2381 */ 2335 */
2382static void __init 2336static void __init
2383mv64460_chip_specific_init(struct mv64x60_handle *bh, 2337mv64460_chip_specific_init(struct mv64x60_handle *bh,
2384 struct mv64x60_setup_info *si) 2338 struct mv64x60_setup_info *si)
2385{ 2339{
2340#if !defined(CONFIG_NOT_COHERENT_CACHE)
2341 mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24) | (1<<25));
2342 mv64x60_set_bits(bh, MV64460_D_UNIT_MMASK, (1<<1) | (1<<4));
2343#endif
2386#ifdef CONFIG_SERIAL_MPSC 2344#ifdef CONFIG_SERIAL_MPSC
2387 mv64x60_mpsc0_pdata.brg_can_tune = 1; 2345 mv64x60_mpsc0_pdata.brg_can_tune = 1;
2346 mv64x60_mpsc0_pdata.cache_mgmt = 1;
2388 mv64x60_mpsc1_pdata.brg_can_tune = 1; 2347 mv64x60_mpsc1_pdata.brg_can_tune = 1;
2348 mv64x60_mpsc1_pdata.cache_mgmt = 1;
2389#endif 2349#endif
2390 return;
2391} 2350}
2351
2352
2353#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
2354/* Export the hotswap register via sysfs for enum event monitoring */
2355#define VAL_LEN_MAX 11 /* 32-bit hex or dec stringified number + '\n' */
2356
2357DECLARE_MUTEX(mv64xxx_hs_lock);
2358
2359static ssize_t
2360mv64xxx_hs_reg_read(struct kobject *kobj, char *buf, loff_t off, size_t count)
2361{
2362 u32 v;
2363 u8 save_exclude;
2364
2365 if (off > 0)
2366 return 0;
2367 if (count < VAL_LEN_MAX)
2368 return -EINVAL;
2369
2370 if (down_interruptible(&mv64xxx_hs_lock))
2371 return -ERESTARTSYS;
2372 save_exclude = mv64x60_pci_exclude_bridge;
2373 mv64x60_pci_exclude_bridge = 0;
2374 early_read_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
2375 MV64360_PCICFG_CPCI_HOTSWAP, &v);
2376 mv64x60_pci_exclude_bridge = save_exclude;
2377 up(&mv64xxx_hs_lock);
2378
2379 return sprintf(buf, "0x%08x\n", v);
2380}
2381
2382static ssize_t
2383mv64xxx_hs_reg_write(struct kobject *kobj, char *buf, loff_t off, size_t count)
2384{
2385 u32 v;
2386 u8 save_exclude;
2387
2388 if (off > 0)
2389 return 0;
2390 if (count <= 0)
2391 return -EINVAL;
2392
2393 if (sscanf(buf, "%i", &v) == 1) {
2394 if (down_interruptible(&mv64xxx_hs_lock))
2395 return -ERESTARTSYS;
2396 save_exclude = mv64x60_pci_exclude_bridge;
2397 mv64x60_pci_exclude_bridge = 0;
2398 early_write_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
2399 MV64360_PCICFG_CPCI_HOTSWAP, v);
2400 mv64x60_pci_exclude_bridge = save_exclude;
2401 up(&mv64xxx_hs_lock);
2402 }
2403 else
2404 count = -EINVAL;
2405
2406 return count;
2407}
2408
2409static struct bin_attribute mv64xxx_hs_reg_attr = { /* Hotswap register */
2410 .attr = {
2411 .name = "hs_reg",
2412 .mode = S_IRUGO | S_IWUSR,
2413 .owner = THIS_MODULE,
2414 },
2415 .size = VAL_LEN_MAX,
2416 .read = mv64xxx_hs_reg_read,
2417 .write = mv64xxx_hs_reg_write,
2418};
2419
2420/* Provide sysfs file indicating if this platform supports the hs_reg */
2421static ssize_t
2422mv64xxx_hs_reg_valid_show(struct device *dev, struct device_attribute *attr,
2423 char *buf)
2424{
2425 struct platform_device *pdev;
2426 struct mv64xxx_pdata *pdp;
2427 u32 v;
2428
2429 pdev = container_of(dev, struct platform_device, dev);
2430 pdp = (struct mv64xxx_pdata *)pdev->dev.platform_data;
2431
2432 if (down_interruptible(&mv64xxx_hs_lock))
2433 return -ERESTARTSYS;
2434 v = pdp->hs_reg_valid;
2435 up(&mv64xxx_hs_lock);
2436
2437 return sprintf(buf, "%i\n", v);
2438}
2439static DEVICE_ATTR(hs_reg_valid, S_IRUGO, mv64xxx_hs_reg_valid_show, NULL);
2440
2441static int __init
2442mv64xxx_sysfs_init(void)
2443{
2444 sysfs_create_bin_file(&mv64xxx_device.dev.kobj, &mv64xxx_hs_reg_attr);
2445 sysfs_create_file(&mv64xxx_device.dev.kobj,&dev_attr_hs_reg_valid.attr);
2446 return 0;
2447}
2448subsys_initcall(mv64xxx_sysfs_init);
2449#endif
diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c
index e5fd2ae503ea..9ccce438bd7a 100644
--- a/arch/ppc/syslib/ocp.c
+++ b/arch/ppc/syslib/ocp.c
@@ -165,7 +165,7 @@ ocp_device_remove(struct device *dev)
165} 165}
166 166
167static int 167static int
168ocp_device_suspend(struct device *dev, u32 state) 168ocp_device_suspend(struct device *dev, pm_message_t state)
169{ 169{
170 struct ocp_device *ocp_dev = to_ocp_dev(dev); 170 struct ocp_device *ocp_dev = to_ocp_dev(dev);
171 struct ocp_driver *ocp_drv = to_ocp_drv(dev->driver); 171 struct ocp_driver *ocp_drv = to_ocp_drv(dev->driver);
diff --git a/arch/ppc/syslib/of_device.c b/arch/ppc/syslib/of_device.c
index 1eb4f726ca9f..da8a0f2128dc 100644
--- a/arch/ppc/syslib/of_device.c
+++ b/arch/ppc/syslib/of_device.c
@@ -105,7 +105,7 @@ static int of_device_remove(struct device *dev)
105 return 0; 105 return 0;
106} 106}
107 107
108static int of_device_suspend(struct device *dev, u32 state) 108static int of_device_suspend(struct device *dev, pm_message_t state)
109{ 109{
110 struct of_device * of_dev = to_of_device(dev); 110 struct of_device * of_dev = to_of_device(dev);
111 struct of_platform_driver * drv = to_of_platform_driver(dev->driver); 111 struct of_platform_driver * drv = to_of_platform_driver(dev->driver);
diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c
index ad39b86ca92c..53da58523e39 100644
--- a/arch/ppc/syslib/open_pic.c
+++ b/arch/ppc/syslib/open_pic.c
@@ -948,7 +948,7 @@ static void openpic_cached_disable_irq(u_int irq)
948 * we need something better to deal with that... Maybe switch to S1 for 948 * we need something better to deal with that... Maybe switch to S1 for
949 * cpufreq changes 949 * cpufreq changes
950 */ 950 */
951int openpic_suspend(struct sys_device *sysdev, u32 state) 951int openpic_suspend(struct sys_device *sysdev, pm_message_t state)
952{ 952{
953 int i; 953 int i;
954 unsigned long flags; 954 unsigned long flags;
diff --git a/arch/ppc/syslib/ppc4xx_setup.c b/arch/ppc/syslib/ppc4xx_setup.c
index e170aebeb69b..b843c4fef25e 100644
--- a/arch/ppc/syslib/ppc4xx_setup.c
+++ b/arch/ppc/syslib/ppc4xx_setup.c
@@ -48,10 +48,6 @@
48extern void abort(void); 48extern void abort(void);
49extern void ppc4xx_find_bridges(void); 49extern void ppc4xx_find_bridges(void);
50 50
51extern void ppc4xx_wdt_heartbeat(void);
52extern int wdt_enable;
53extern unsigned long wdt_period;
54
55/* Global Variables */ 51/* Global Variables */
56bd_t __res; 52bd_t __res;
57 53
@@ -171,7 +167,7 @@ ppc4xx_calibrate_decr(void)
171 unsigned int freq; 167 unsigned int freq;
172 bd_t *bip = &__res; 168 bd_t *bip = &__res;
173 169
174#if defined(CONFIG_WALNUT) || defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE) 170#if defined(CONFIG_WALNUT) || defined(CONFIG_SYCAMORE)
175 /* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */ 171 /* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */
176 mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE); 172 mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
177#endif 173#endif
@@ -257,22 +253,6 @@ ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
257 *(char *) (r7 + KERNELBASE) = 0; 253 *(char *) (r7 + KERNELBASE) = 0;
258 strcpy(cmd_line, (char *) (r6 + KERNELBASE)); 254 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
259 } 255 }
260#if defined(CONFIG_PPC405_WDT)
261/* Look for wdt= option on command line */
262 if (strstr(cmd_line, "wdt=")) {
263 int valid_wdt = 0;
264 char *p, *q;
265 for (q = cmd_line; (p = strstr(q, "wdt=")) != 0;) {
266 q = p + 4;
267 if (p > cmd_line && p[-1] != ' ')
268 continue;
269 wdt_period = simple_strtoul(q, &q, 0);
270 valid_wdt = 1;
271 ++q;
272 }
273 wdt_enable = valid_wdt;
274 }
275#endif
276 256
277 /* Initialize machine-dependent vectors */ 257 /* Initialize machine-dependent vectors */
278 258
@@ -287,11 +267,6 @@ ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
287 267
288 ppc_md.calibrate_decr = ppc4xx_calibrate_decr; 268 ppc_md.calibrate_decr = ppc4xx_calibrate_decr;
289 269
290#ifdef CONFIG_PPC405_WDT
291 ppc_md.heartbeat = ppc4xx_wdt_heartbeat;
292#endif
293 ppc_md.heartbeat_count = 0;
294
295 ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory; 270 ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory;
296 ppc_md.setup_io_mappings = ppc4xx_map_io; 271 ppc_md.setup_io_mappings = ppc4xx_map_io;
297 272
diff --git a/arch/ppc/syslib/ppc83xx_pci.h b/arch/ppc/syslib/ppc83xx_pci.h
new file mode 100644
index 000000000000..ec691640f6be
--- /dev/null
+++ b/arch/ppc/syslib/ppc83xx_pci.h
@@ -0,0 +1,151 @@
1/* Created by Tony Li <tony.li@freescale.com>
2 * Copyright (c) 2005 freescale semiconductor
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __PPC_SYSLIB_PPC83XX_PCI_H
20#define __PPC_SYSLIB_PPC83XX_PCI_H
21
22typedef struct immr_clk {
23 u32 spmr; /* system PLL mode Register */
24 u32 occr; /* output clock control Register */
25 u32 sccr; /* system clock control Register */
26 u8 res0[0xF4];
27} immr_clk_t;
28
29/*
30 * Sequencer
31 */
32typedef struct immr_ios {
33 u32 potar0;
34 u8 res0[4];
35 u32 pobar0;
36 u8 res1[4];
37 u32 pocmr0;
38 u8 res2[4];
39 u32 potar1;
40 u8 res3[4];
41 u32 pobar1;
42 u8 res4[4];
43 u32 pocmr1;
44 u8 res5[4];
45 u32 potar2;
46 u8 res6[4];
47 u32 pobar2;
48 u8 res7[4];
49 u32 pocmr2;
50 u8 res8[4];
51 u32 potar3;
52 u8 res9[4];
53 u32 pobar3;
54 u8 res10[4];
55 u32 pocmr3;
56 u8 res11[4];
57 u32 potar4;
58 u8 res12[4];
59 u32 pobar4;
60 u8 res13[4];
61 u32 pocmr4;
62 u8 res14[4];
63 u32 potar5;
64 u8 res15[4];
65 u32 pobar5;
66 u8 res16[4];
67 u32 pocmr5;
68 u8 res17[4];
69 u8 res18[0x60];
70 u32 pmcr;
71 u8 res19[4];
72 u32 dtcr;
73 u8 res20[4];
74} immr_ios_t;
75#define POTAR_TA_MASK 0x000fffff
76#define POBAR_BA_MASK 0x000fffff
77#define POCMR_EN 0x80000000
78#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
79#define POCMR_SE 0x20000000 /* streaming enable */
80#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */
81#define POCMR_CM_MASK 0x000fffff
82
83/*
84 * PCI Controller Control and Status Registers
85 */
86typedef struct immr_pcictrl {
87 u32 esr;
88 u32 ecdr;
89 u32 eer;
90 u32 eatcr;
91 u32 eacr;
92 u32 eeacr;
93 u32 edlcr;
94 u32 edhcr;
95 u32 gcr;
96 u32 ecr;
97 u32 gsr;
98 u8 res0[12];
99 u32 pitar2;
100 u8 res1[4];
101 u32 pibar2;
102 u32 piebar2;
103 u32 piwar2;
104 u8 res2[4];
105 u32 pitar1;
106 u8 res3[4];
107 u32 pibar1;
108 u32 piebar1;
109 u32 piwar1;
110 u8 res4[4];
111 u32 pitar0;
112 u8 res5[4];
113 u32 pibar0;
114 u8 res6[4];
115 u32 piwar0;
116 u8 res7[132];
117} immr_pcictrl_t;
118#define PITAR_TA_MASK 0x000fffff
119#define PIBAR_MASK 0xffffffff
120#define PIEBAR_EBA_MASK 0x000fffff
121#define PIWAR_EN 0x80000000
122#define PIWAR_PF 0x20000000
123#define PIWAR_RTT_MASK 0x000f0000
124#define PIWAR_RTT_NO_SNOOP 0x00040000
125#define PIWAR_RTT_SNOOP 0x00050000
126#define PIWAR_WTT_MASK 0x0000f000
127#define PIWAR_WTT_NO_SNOOP 0x00004000
128#define PIWAR_WTT_SNOOP 0x00005000
129#define PIWAR_IWS_MASK 0x0000003F
130#define PIWAR_IWS_4K 0x0000000B
131#define PIWAR_IWS_8K 0x0000000C
132#define PIWAR_IWS_16K 0x0000000D
133#define PIWAR_IWS_32K 0x0000000E
134#define PIWAR_IWS_64K 0x0000000F
135#define PIWAR_IWS_128K 0x00000010
136#define PIWAR_IWS_256K 0x00000011
137#define PIWAR_IWS_512K 0x00000012
138#define PIWAR_IWS_1M 0x00000013
139#define PIWAR_IWS_2M 0x00000014
140#define PIWAR_IWS_4M 0x00000015
141#define PIWAR_IWS_8M 0x00000016
142#define PIWAR_IWS_16M 0x00000017
143#define PIWAR_IWS_32M 0x00000018
144#define PIWAR_IWS_64M 0x00000019
145#define PIWAR_IWS_128M 0x0000001A
146#define PIWAR_IWS_256M 0x0000001B
147#define PIWAR_IWS_512M 0x0000001C
148#define PIWAR_IWS_1G 0x0000001D
149#define PIWAR_IWS_2G 0x0000001E
150
151#endif /* __PPC_SYSLIB_PPC83XX_PCI_H */
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c
index 602a86891f7f..890484e576e7 100644
--- a/arch/ppc/syslib/ppc83xx_setup.c
+++ b/arch/ppc/syslib/ppc83xx_setup.c
@@ -11,6 +11,17 @@
11 * under the terms of the GNU General Public License as published by the 11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your 12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version. 13 * option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 * Added PCI support -- Tony Li <tony.li@freescale.com>
14 */ 25 */
15 26
16#include <linux/config.h> 27#include <linux/config.h>
@@ -31,6 +42,10 @@
31#include <asm/delay.h> 42#include <asm/delay.h>
32 43
33#include <syslib/ppc83xx_setup.h> 44#include <syslib/ppc83xx_setup.h>
45#if defined(CONFIG_PCI)
46#include <asm/delay.h>
47#include <syslib/ppc83xx_pci.h>
48#endif
34 49
35phys_addr_t immrbar; 50phys_addr_t immrbar;
36 51
@@ -162,4 +177,237 @@ mpc83xx_halt(void)
162 for(;;); 177 for(;;);
163} 178}
164 179
165/* PCI SUPPORT DOES NOT EXIT, MODEL after ppc85xx_setup.c */ 180#if defined(CONFIG_PCI)
181void __init
182mpc83xx_setup_pci1(struct pci_controller *hose)
183{
184 u16 reg16;
185 volatile immr_pcictrl_t * pci_ctrl;
186 volatile immr_ios_t * ios;
187 bd_t *binfo = (bd_t *) __res;
188
189 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t));
190 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
191
192 /*
193 * Configure PCI Outbound Translation Windows
194 */
195 ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK;
196 ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK;
197 ios->pocmr0 = POCMR_EN |
198 (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM -
199 MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
200
201 /* mapped to PCI1 IO space */
202 ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK;
203 ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK;
204 ios->pocmr1 = POCMR_EN | POCMR_IO |
205 (((0xffffffff - (MPC83xx_PCI1_UPPER_IO -
206 MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK);
207
208 /*
209 * Configure PCI Inbound Translation Windows
210 */
211 pci_ctrl->pitar1 = 0x0;
212 pci_ctrl->pibar1 = 0x0;
213 pci_ctrl->piebar1 = 0x0;
214 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
215
216 /*
217 * Release PCI RST signal
218 */
219 pci_ctrl->gcr = 0;
220 udelay(2000);
221 pci_ctrl->gcr = 1;
222 udelay(2000);
223
224 reg16 = 0xff;
225 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
226 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
227 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
228
229 /*
230 * Clear non-reserved bits in status register.
231 */
232 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
233 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
234
235 iounmap(pci_ctrl);
236 iounmap(ios);
237}
238
239void __init
240mpc83xx_setup_pci2(struct pci_controller *hose)
241{
242 u16 reg16;
243 volatile immr_pcictrl_t * pci_ctrl;
244 volatile immr_ios_t * ios;
245 bd_t *binfo = (bd_t *) __res;
246
247 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t));
248 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
249
250 /*
251 * Configure PCI Outbound Translation Windows
252 */
253 ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK;
254 ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK;
255 ios->pocmr3 = POCMR_EN | POCMR_DST |
256 (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM -
257 MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
258
259 /* mapped to PCI2 IO space */
260 ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK;
261 ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK;
262 ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO |
263 (((0xffffffff - (MPC83xx_PCI2_UPPER_IO -
264 MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK);
265
266 /*
267 * Configure PCI Inbound Translation Windows
268 */
269 pci_ctrl->pitar1 = 0x0;
270 pci_ctrl->pibar1 = 0x0;
271 pci_ctrl->piebar1 = 0x0;
272 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
273
274 /*
275 * Release PCI RST signal
276 */
277 pci_ctrl->gcr = 0;
278 udelay(2000);
279 pci_ctrl->gcr = 1;
280 udelay(2000);
281
282 reg16 = 0xff;
283 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
284 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
285 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
286
287 /*
288 * Clear non-reserved bits in status register.
289 */
290 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
291 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
292
293 iounmap(pci_ctrl);
294 iounmap(ios);
295}
296
297/*
298 * PCI buses can be enabled only if SYS board combinates with PIB
299 * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses
300 * and 3 PCI slots, so people must configure the routes between them before
301 * enable PCI bus. This routes are under the control of PCA9555PW device which
302 * can be accessed via I2C bus 2 and are configured by firmware. Refer to
303 * Freescale to get more information about firmware configuration.
304 */
305
306extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
307extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel,
308 unsigned char pin);
309void __init
310mpc83xx_setup_hose(void)
311{
312 u32 val32;
313 volatile immr_clk_t * clk;
314 struct pci_controller * hose1;
315#ifdef CONFIG_MPC83xx_PCI2
316 struct pci_controller * hose2;
317#endif
318 bd_t * binfo = (bd_t *)__res;
319
320 clk = ioremap(binfo->bi_immr_base + 0xA00,
321 sizeof(immr_clk_t));
322
323 /*
324 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
325 */
326 val32 = clk->occr;
327 udelay(2000);
328 clk->occr = 0xff000000;
329 udelay(2000);
330
331 iounmap(clk);
332
333 hose1 = pcibios_alloc_controller();
334 if(!hose1)
335 return;
336
337 ppc_md.pci_swizzle = common_swizzle;
338 ppc_md.pci_map_irq = mpc83xx_map_irq;
339
340 hose1->bus_offset = 0;
341 hose1->first_busno = 0;
342 hose1->last_busno = 0xff;
343
344 setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
345 binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
346 hose1->set_cfg_type = 1;
347
348 mpc83xx_setup_pci1(hose1);
349
350 hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
351 hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
352 hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
353
354 hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
355 hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
356 hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
357#ifdef CONFIG_MPC83xx_PCI2
358 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
359 MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
360#else
361 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
362 MPC83xx_PCI1_IO_SIZE);
363#endif /* CONFIG_MPC83xx_PCI2 */
364 hose1->io_base_virt = (void *)isa_io_base;
365 /* setup resources */
366 pci_init_resource(&hose1->io_resource,
367 MPC83xx_PCI1_LOWER_IO,
368 MPC83xx_PCI1_UPPER_IO,
369 IORESOURCE_IO, "PCI host bridge 1");
370 pci_init_resource(&hose1->mem_resources[0],
371 MPC83xx_PCI1_LOWER_MEM,
372 MPC83xx_PCI1_UPPER_MEM,
373 IORESOURCE_MEM, "PCI host bridge 1");
374
375 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
376 hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
377
378#ifdef CONFIG_MPC83xx_PCI2
379 hose2 = pcibios_alloc_controller();
380 if(!hose2)
381 return;
382
383 hose2->bus_offset = hose1->last_busno + 1;
384 hose2->first_busno = hose1->last_busno + 1;
385 hose2->last_busno = 0xff;
386 setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
387 binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
388 hose2->set_cfg_type = 1;
389
390 mpc83xx_setup_pci2(hose2);
391
392 hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
393 hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
394 hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
395
396 hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
397 hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
398 hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
399 hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
400 /* setup resources */
401 pci_init_resource(&hose2->io_resource,
402 MPC83xx_PCI2_LOWER_IO,
403 MPC83xx_PCI2_UPPER_IO,
404 IORESOURCE_IO, "PCI host bridge 2");
405 pci_init_resource(&hose2->mem_resources[0],
406 MPC83xx_PCI2_LOWER_MEM,
407 MPC83xx_PCI2_UPPER_MEM,
408 IORESOURCE_MEM, "PCI host bridge 2");
409
410 hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
411#endif /* CONFIG_MPC83xx_PCI2 */
412}
413#endif /*CONFIG_PCI*/
diff --git a/arch/ppc/syslib/ppc83xx_setup.h b/arch/ppc/syslib/ppc83xx_setup.h
index 683f179b746c..c766c1a5f786 100644
--- a/arch/ppc/syslib/ppc83xx_setup.h
+++ b/arch/ppc/syslib/ppc83xx_setup.h
@@ -12,6 +12,14 @@
12 * Free Software Foundation; either version 2 of the License, or (at your 12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version. 13 * option) any later version.
14 * 14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
15 */ 23 */
16 24
17#ifndef __PPC_SYSLIB_PPC83XX_SETUP_H 25#ifndef __PPC_SYSLIB_PPC83XX_SETUP_H
@@ -19,7 +27,6 @@
19 27
20#include <linux/config.h> 28#include <linux/config.h>
21#include <linux/init.h> 29#include <linux/init.h>
22#include <asm/ppcboot.h>
23 30
24extern unsigned long mpc83xx_find_end_of_memory(void) __init; 31extern unsigned long mpc83xx_find_end_of_memory(void) __init;
25extern long mpc83xx_time_init(void) __init; 32extern long mpc83xx_time_init(void) __init;
@@ -31,13 +38,11 @@ extern void mpc83xx_halt(void);
31extern void mpc83xx_setup_hose(void) __init; 38extern void mpc83xx_setup_hose(void) __init;
32 39
33/* PCI config */ 40/* PCI config */
34#if 0 41#define PCI1_CFG_ADDR_OFFSET (0x8300)
35#define PCI1_CFG_ADDR_OFFSET (FIXME) 42#define PCI1_CFG_DATA_OFFSET (0x8304)
36#define PCI1_CFG_DATA_OFFSET (FIXME)
37 43
38#define PCI2_CFG_ADDR_OFFSET (FIXME) 44#define PCI2_CFG_ADDR_OFFSET (0x8380)
39#define PCI2_CFG_DATA_OFFSET (FIXME) 45#define PCI2_CFG_DATA_OFFSET (0x8384)
40#endif
41 46
42/* Serial Config */ 47/* Serial Config */
43#ifdef CONFIG_SERIAL_MANY_PORTS 48#ifdef CONFIG_SERIAL_MANY_PORTS
diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c
index 879202352560..52ba0c68078d 100644
--- a/arch/ppc/syslib/ppc_sys.c
+++ b/arch/ppc/syslib/ppc_sys.c
@@ -6,6 +6,7 @@
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com> 6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 * 7 *
8 * Copyright 2005 Freescale Semiconductor Inc. 8 * Copyright 2005 Freescale Semiconductor Inc.
9 * Copyright 2005 MontaVista, Inc. by Vitaly Bordug <vbordug@ru.mvista.com>
9 * 10 *
10 * This program is free software; you can redistribute it and/or modify it 11 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 12 * under the terms of the GNU General Public License as published by the
@@ -35,10 +36,59 @@ void __init identify_ppc_sys_by_id(u32 id)
35 36
36void __init identify_ppc_sys_by_name(char *name) 37void __init identify_ppc_sys_by_name(char *name)
37{ 38{
38 /* TODO */ 39 unsigned int i = 0;
40 while (ppc_sys_specs[i].ppc_sys_name[0])
41 {
42 if (!strcmp(ppc_sys_specs[i].ppc_sys_name, name))
43 break;
44 i++;
45 }
46 cur_ppc_sys_spec = &ppc_sys_specs[i];
39 return; 47 return;
40} 48}
41 49
50static int __init count_sys_specs(void)
51{
52 int i = 0;
53 while (ppc_sys_specs[i].ppc_sys_name[0])
54 i++;
55 return i;
56}
57
58static int __init find_chip_by_name_and_id(char *name, u32 id)
59{
60 int ret = -1;
61 unsigned int i = 0;
62 unsigned int j = 0;
63 unsigned int dups = 0;
64
65 unsigned char matched[count_sys_specs()];
66
67 while (ppc_sys_specs[i].ppc_sys_name[0]) {
68 if (!strcmp(ppc_sys_specs[i].ppc_sys_name, name))
69 matched[j++] = i;
70 i++;
71 }
72 if (j != 0) {
73 for (i = 0; i < j; i++) {
74 if ((ppc_sys_specs[matched[i]].mask & id) ==
75 ppc_sys_specs[matched[i]].value) {
76 ret = matched[i];
77 dups++;
78 }
79 }
80 ret = (dups == 1) ? ret : (-1 * dups);
81 }
82 return ret;
83}
84
85void __init identify_ppc_sys_by_name_and_id(char *name, u32 id)
86{
87 int i = find_chip_by_name_and_id(name, id);
88 BUG_ON(i < 0);
89 cur_ppc_sys_spec = &ppc_sys_specs[i];
90}
91
42/* Update all memory resources by paddr, call before platform_device_register */ 92/* Update all memory resources by paddr, call before platform_device_register */
43void __init 93void __init
44ppc_sys_fixup_mem_resource(struct platform_device *pdev, phys_addr_t paddr) 94ppc_sys_fixup_mem_resource(struct platform_device *pdev, phys_addr_t paddr)
diff --git a/arch/ppc/syslib/pq2_devices.c b/arch/ppc/syslib/pq2_devices.c
new file mode 100644
index 000000000000..1d3869768f96
--- /dev/null
+++ b/arch/ppc/syslib/pq2_devices.c
@@ -0,0 +1,389 @@
1/*
2 * arch/ppc/syslib/pq2_devices.c
3 *
4 * PQ2 Device descriptions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/ioport.h>
18#include <asm/cpm2.h>
19#include <asm/irq.h>
20#include <asm/ppc_sys.h>
21
22struct platform_device ppc_sys_platform_devices[] = {
23 [MPC82xx_CPM_FCC1] = {
24 .name = "fsl-cpm-fcc",
25 .id = 1,
26 .num_resources = 3,
27 .resource = (struct resource[]) {
28 {
29 .name = "fcc_regs",
30 .start = 0x11300,
31 .end = 0x1131f,
32 .flags = IORESOURCE_MEM,
33 },
34 {
35 .name = "fcc_pram",
36 .start = 0x8400,
37 .end = 0x84ff,
38 .flags = IORESOURCE_MEM,
39 },
40 {
41 .start = SIU_INT_FCC1,
42 .end = SIU_INT_FCC1,
43 .flags = IORESOURCE_IRQ,
44 },
45 },
46 },
47 [MPC82xx_CPM_FCC2] = {
48 .name = "fsl-cpm-fcc",
49 .id = 2,
50 .num_resources = 3,
51 .resource = (struct resource[]) {
52 {
53 .name = "fcc_regs",
54 .start = 0x11320,
55 .end = 0x1133f,
56 .flags = IORESOURCE_MEM,
57 },
58 {
59 .name = "fcc_pram",
60 .start = 0x8500,
61 .end = 0x85ff,
62 .flags = IORESOURCE_MEM,
63 },
64 {
65 .start = SIU_INT_FCC2,
66 .end = SIU_INT_FCC2,
67 .flags = IORESOURCE_IRQ,
68 },
69 },
70 },
71 [MPC82xx_CPM_FCC3] = {
72 .name = "fsl-cpm-fcc",
73 .id = 3,
74 .num_resources = 3,
75 .resource = (struct resource[]) {
76 {
77 .name = "fcc_regs",
78 .start = 0x11340,
79 .end = 0x1135f,
80 .flags = IORESOURCE_MEM,
81 },
82 {
83 .name = "fcc_pram",
84 .start = 0x8600,
85 .end = 0x86ff,
86 .flags = IORESOURCE_MEM,
87 },
88 {
89 .start = SIU_INT_FCC3,
90 .end = SIU_INT_FCC3,
91 .flags = IORESOURCE_IRQ,
92 },
93 },
94 },
95 [MPC82xx_CPM_I2C] = {
96 .name = "fsl-cpm-i2c",
97 .id = 1,
98 .num_resources = 3,
99 .resource = (struct resource[]) {
100 {
101 .name = "i2c_mem",
102 .start = 0x11860,
103 .end = 0x118BF,
104 .flags = IORESOURCE_MEM,
105 },
106 {
107 .name = "i2c_pram",
108 .start = 0x8afc,
109 .end = 0x8afd,
110 .flags = IORESOURCE_MEM,
111 },
112 {
113 .start = SIU_INT_I2C,
114 .end = SIU_INT_I2C,
115 .flags = IORESOURCE_IRQ,
116 },
117 },
118 },
119 [MPC82xx_CPM_SCC1] = {
120 .name = "fsl-cpm-scc",
121 .id = 1,
122 .num_resources = 3,
123 .resource = (struct resource[]) {
124 {
125 .name = "scc_mem",
126 .start = 0x11A00,
127 .end = 0x11A1F,
128 .flags = IORESOURCE_MEM,
129 },
130 {
131 .name = "scc_pram",
132 .start = 0x8000,
133 .end = 0x80ff,
134 .flags = IORESOURCE_MEM,
135 },
136 {
137 .start = SIU_INT_SCC1,
138 .end = SIU_INT_SCC1,
139 .flags = IORESOURCE_IRQ,
140 },
141 },
142 },
143 [MPC82xx_CPM_SCC2] = {
144 .name = "fsl-cpm-scc",
145 .id = 2,
146 .num_resources = 3,
147 .resource = (struct resource[]) {
148 {
149 .name = "scc_mem",
150 .start = 0x11A20,
151 .end = 0x11A3F,
152 .flags = IORESOURCE_MEM,
153 },
154 {
155 .name = "scc_pram",
156 .start = 0x8100,
157 .end = 0x81ff,
158 .flags = IORESOURCE_MEM,
159 },
160 {
161 .start = SIU_INT_SCC2,
162 .end = SIU_INT_SCC2,
163 .flags = IORESOURCE_IRQ,
164 },
165 },
166 },
167 [MPC82xx_CPM_SCC3] = {
168 .name = "fsl-cpm-scc",
169 .id = 3,
170 .num_resources = 3,
171 .resource = (struct resource[]) {
172 {
173 .name = "scc_mem",
174 .start = 0x11A40,
175 .end = 0x11A5F,
176 .flags = IORESOURCE_MEM,
177 },
178 {
179 .name = "scc_pram",
180 .start = 0x8200,
181 .end = 0x82ff,
182 .flags = IORESOURCE_MEM,
183 },
184 {
185 .start = SIU_INT_SCC3,
186 .end = SIU_INT_SCC3,
187 .flags = IORESOURCE_IRQ,
188 },
189 },
190 },
191 [MPC82xx_CPM_SCC4] = {
192 .name = "fsl-cpm-scc",
193 .id = 4,
194 .num_resources = 3,
195 .resource = (struct resource[]) {
196 {
197 .name = "scc_mem",
198 .start = 0x11A60,
199 .end = 0x11A7F,
200 .flags = IORESOURCE_MEM,
201 },
202 {
203 .name = "scc_pram",
204 .start = 0x8300,
205 .end = 0x83ff,
206 .flags = IORESOURCE_MEM,
207 },
208 {
209 .start = SIU_INT_SCC4,
210 .end = SIU_INT_SCC4,
211 .flags = IORESOURCE_IRQ,
212 },
213 },
214 },
215 [MPC82xx_CPM_SPI] = {
216 .name = "fsl-cpm-spi",
217 .id = 1,
218 .num_resources = 3,
219 .resource = (struct resource[]) {
220 {
221 .name = "spi_mem",
222 .start = 0x11AA0,
223 .end = 0x11AFF,
224 .flags = IORESOURCE_MEM,
225 },
226 {
227 .name = "spi_pram",
228 .start = 0x89fc,
229 .end = 0x89fd,
230 .flags = IORESOURCE_MEM,
231 },
232 {
233 .start = SIU_INT_SPI,
234 .end = SIU_INT_SPI,
235 .flags = IORESOURCE_IRQ,
236 },
237 },
238 },
239 [MPC82xx_CPM_MCC1] = {
240 .name = "fsl-cpm-mcc",
241 .id = 1,
242 .num_resources = 3,
243 .resource = (struct resource[]) {
244 {
245 .name = "mcc_mem",
246 .start = 0x11B30,
247 .end = 0x11B3F,
248 .flags = IORESOURCE_MEM,
249 },
250 {
251 .name = "mcc_pram",
252 .start = 0x8700,
253 .end = 0x877f,
254 .flags = IORESOURCE_MEM,
255 },
256 {
257 .start = SIU_INT_MCC1,
258 .end = SIU_INT_MCC1,
259 .flags = IORESOURCE_IRQ,
260 },
261 },
262 },
263 [MPC82xx_CPM_MCC2] = {
264 .name = "fsl-cpm-mcc",
265 .id = 2,
266 .num_resources = 3,
267 .resource = (struct resource[]) {
268 {
269 .name = "mcc_mem",
270 .start = 0x11B50,
271 .end = 0x11B5F,
272 .flags = IORESOURCE_MEM,
273 },
274 {
275 .name = "mcc_pram",
276 .start = 0x8800,
277 .end = 0x887f,
278 .flags = IORESOURCE_MEM,
279 },
280 {
281 .start = SIU_INT_MCC2,
282 .end = SIU_INT_MCC2,
283 .flags = IORESOURCE_IRQ,
284 },
285 },
286 },
287 [MPC82xx_CPM_SMC1] = {
288 .name = "fsl-cpm-smc",
289 .id = 1,
290 .num_resources = 3,
291 .resource = (struct resource[]) {
292 {
293 .name = "smc_mem",
294 .start = 0x11A80,
295 .end = 0x11A8F,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .name = "smc_pram",
300 .start = 0x87fc,
301 .end = 0x87fd,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .start = SIU_INT_SMC1,
306 .end = SIU_INT_SMC1,
307 .flags = IORESOURCE_IRQ,
308 },
309 },
310 },
311 [MPC82xx_CPM_SMC2] = {
312 .name = "fsl-cpm-smc",
313 .id = 2,
314 .num_resources = 3,
315 .resource = (struct resource[]) {
316 {
317 .name = "smc_mem",
318 .start = 0x11A90,
319 .end = 0x11A9F,
320 .flags = IORESOURCE_MEM,
321 },
322 {
323 .name = "smc_pram",
324 .start = 0x88fc,
325 .end = 0x88fd,
326 .flags = IORESOURCE_MEM,
327 },
328 {
329 .start = SIU_INT_SMC2,
330 .end = SIU_INT_SMC2,
331 .flags = IORESOURCE_IRQ,
332 },
333 },
334 },
335 [MPC82xx_CPM_USB] = {
336 .name = "fsl-cpm-usb",
337 .id = 1,
338 .num_resources = 3,
339 .resource = (struct resource[]) {
340 {
341 .name = "usb_mem",
342 .start = 0x11b60,
343 .end = 0x11b78,
344 .flags = IORESOURCE_MEM,
345 },
346 {
347 .name = "usb_pram",
348 .start = 0x8b00,
349 .end = 0x8bff,
350 .flags = IORESOURCE_MEM,
351 },
352 {
353 .start = SIU_INT_USB,
354 .end = SIU_INT_USB,
355 .flags = IORESOURCE_IRQ,
356 },
357
358 },
359 },
360 [MPC82xx_SEC1] = {
361 .name = "fsl-sec",
362 .id = 1,
363 .num_resources = 1,
364 .resource = (struct resource[]) {
365 {
366 .name = "sec_mem",
367 .start = 0x40000,
368 .end = 0x52fff,
369 .flags = IORESOURCE_MEM,
370 },
371 },
372 },
373};
374
375static int __init mach_mpc82xx_fixup(struct platform_device *pdev)
376{
377 ppc_sys_fixup_mem_resource(pdev, CPM_MAP_ADDR);
378 return 0;
379}
380
381static int __init mach_mpc82xx_init(void)
382{
383 if (ppc_md.progress)
384 ppc_md.progress("mach_mpc82xx_init:enter", 0);
385 ppc_sys_device_fixup = mach_mpc82xx_fixup;
386 return 0;
387}
388
389postcore_initcall(mach_mpc82xx_init);
diff --git a/arch/ppc/syslib/pq2_sys.c b/arch/ppc/syslib/pq2_sys.c
new file mode 100644
index 000000000000..7b6c9ebdb9e3
--- /dev/null
+++ b/arch/ppc/syslib/pq2_sys.c
@@ -0,0 +1,200 @@
1/*
2 * arch/ppc/syslib/pq2_devices.c
3 *
4 * PQ2 System descriptions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/device.h>
16
17#include <asm/ppc_sys.h>
18
19struct ppc_sys_spec *cur_ppc_sys_spec;
20struct ppc_sys_spec ppc_sys_specs[] = {
21 /* below is a list of the 8260 family of processors */
22 {
23 .ppc_sys_name = "8250",
24 .mask = 0x0000ff00,
25 .value = 0x00000000,
26 .num_devices = 12,
27 .device_list = (enum ppc_sys_devices[])
28 {
29 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
30 MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
31 MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
32 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
33 }
34 },
35 {
36 .ppc_sys_name = "8255",
37 .mask = 0x0000ff00,
38 .value = 0x00000000,
39 .num_devices = 11,
40 .device_list = (enum ppc_sys_devices[])
41 {
42 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1,
43 MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4,
44 MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2,
45 MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
46 }
47 },
48 {
49 .ppc_sys_name = "8260",
50 .mask = 0x0000ff00,
51 .value = 0x00000000,
52 .num_devices = 12,
53 .device_list = (enum ppc_sys_devices[])
54 {
55 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
56 MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
57 MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
58 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
59 }
60 },
61 {
62 .ppc_sys_name = "8264",
63 .mask = 0x0000ff00,
64 .value = 0x00000000,
65 .num_devices = 12,
66 .device_list = (enum ppc_sys_devices[])
67 {
68 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
69 MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
70 MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
71 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
72 }
73 },
74 {
75 .ppc_sys_name = "8265",
76 .mask = 0x0000ff00,
77 .value = 0x00000000,
78 .num_devices = 12,
79 .device_list = (enum ppc_sys_devices[])
80 {
81 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
82 MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
83 MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
84 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
85 }
86 },
87 {
88 .ppc_sys_name = "8266",
89 .mask = 0x0000ff00,
90 .value = 0x00000000,
91 .num_devices = 12,
92 .device_list = (enum ppc_sys_devices[])
93 {
94 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
95 MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
96 MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
97 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
98 }
99 },
100 /* below is a list of the 8272 family of processors */
101 {
102 .ppc_sys_name = "8247",
103 .mask = 0x0000ff00,
104 .value = 0x00000d00,
105 .num_devices = 10,
106 .device_list = (enum ppc_sys_devices[])
107 {
108 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1,
109 MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SMC1,
110 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
111 MPC82xx_CPM_USB,
112 },
113 },
114 {
115 .ppc_sys_name = "8248",
116 .mask = 0x0000ff00,
117 .value = 0x00000c00,
118 .num_devices = 11,
119 .device_list = (enum ppc_sys_devices[])
120 {
121 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1,
122 MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SMC1,
123 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
124 MPC82xx_CPM_USB, MPC82xx_SEC1,
125 },
126 },
127 {
128 .ppc_sys_name = "8271",
129 .mask = 0x0000ff00,
130 .value = 0x00000d00,
131 .num_devices = 10,
132 .device_list = (enum ppc_sys_devices[])
133 {
134 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1,
135 MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SMC1,
136 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
137 MPC82xx_CPM_USB,
138 },
139 },
140 {
141 .ppc_sys_name = "8272",
142 .mask = 0x0000ff00,
143 .value = 0x00000c00,
144 .num_devices = 11,
145 .device_list = (enum ppc_sys_devices[])
146 {
147 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1,
148 MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SMC1,
149 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
150 MPC82xx_CPM_USB, MPC82xx_SEC1,
151 },
152 },
153 /* below is a list of the 8280 family of processors */
154 {
155 .ppc_sys_name = "8270",
156 .mask = 0x0000ff00,
157 .value = 0x00000a00,
158 .num_devices = 12,
159 .device_list = (enum ppc_sys_devices[])
160 {
161 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
162 MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
163 MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
164 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
165 },
166 },
167 {
168 .ppc_sys_name = "8275",
169 .mask = 0x0000ff00,
170 .value = 0x00000a00,
171 .num_devices = 12,
172 .device_list = (enum ppc_sys_devices[])
173 {
174 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
175 MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
176 MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1,
177 MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C,
178 },
179 },
180 {
181 .ppc_sys_name = "8280",
182 .mask = 0x0000ff00,
183 .value = 0x00000a00,
184 .num_devices = 13,
185 .device_list = (enum ppc_sys_devices[])
186 {
187 MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3,
188 MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3,
189 MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2,
190 MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI,
191 MPC82xx_CPM_I2C,
192 },
193 },
194 {
195 /* default match */
196 .ppc_sys_name = "",
197 .mask = 0x00000000,
198 .value = 0x00000000,
199 },
200};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 10:14:44 -0500