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authorAndy Fleming <afleming@freescale.com>2005-10-28 20:46:27 -0400
committerPaul Mackerras <paulus@samba.org>2005-10-29 00:42:28 -0400
commitb37665e0ba1d3f05697bfae249b09a2e9cc95132 (patch)
tree22c80609e3254524038d5b690f1f886b0987f58d /arch/ppc/syslib
parentdd03d25fac90ee6f394874fb4e6995866304e4ba (diff)
[PATCH] ppc32: 85xx PHY Platform Update
This patch updates the 85xx platform code to support the new PHY Layer. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <Kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/syslib')
-rw-r--r--arch/ppc/syslib/mpc85xx_devices.c17
-rw-r--r--arch/ppc/syslib/mpc85xx_sys.c44
2 files changed, 38 insertions, 23 deletions
diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c
index bbc5ac0de878..2ede677a0a53 100644
--- a/arch/ppc/syslib/mpc85xx_devices.c
+++ b/arch/ppc/syslib/mpc85xx_devices.c
@@ -25,19 +25,20 @@
25/* We use offsets for IORESOURCE_MEM since we do not know at compile time 25/* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup 26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
27 */ 27 */
28struct gianfar_mdio_data mpc85xx_mdio_pdata = {
29 .paddr = MPC85xx_MIIM_OFFSET,
30};
28 31
29static struct gianfar_platform_data mpc85xx_tsec1_pdata = { 32static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
30 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | 33 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
31 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | 34 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
32 FSL_GIANFAR_DEV_HAS_MULTI_INTR, 35 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
33 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
34}; 36};
35 37
36static struct gianfar_platform_data mpc85xx_tsec2_pdata = { 38static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
37 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | 39 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
38 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | 40 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
39 FSL_GIANFAR_DEV_HAS_MULTI_INTR, 41 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
40 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
41}; 42};
42 43
43static struct gianfar_platform_data mpc85xx_etsec1_pdata = { 44static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
@@ -46,7 +47,6 @@ static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 47 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | 48 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, 49 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
50}; 50};
51 51
52static struct gianfar_platform_data mpc85xx_etsec2_pdata = { 52static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
@@ -55,7 +55,6 @@ static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
55 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 55 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
56 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | 56 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, 57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
58 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
59}; 58};
60 59
61static struct gianfar_platform_data mpc85xx_etsec3_pdata = { 60static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
@@ -64,7 +63,6 @@ static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
64 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 63 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
65 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | 64 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
66 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, 65 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
67 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
68}; 66};
69 67
70static struct gianfar_platform_data mpc85xx_etsec4_pdata = { 68static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
@@ -73,11 +71,10 @@ static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
73 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 71 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
74 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | 72 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
75 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH, 73 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
76 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
77}; 74};
78 75
79static struct gianfar_platform_data mpc85xx_fec_pdata = { 76static struct gianfar_platform_data mpc85xx_fec_pdata = {
80 .phy_reg_addr = MPC85xx_ENET1_OFFSET, 77 .device_flags = 0,
81}; 78};
82 79
83static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = { 80static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
@@ -719,6 +716,12 @@ struct platform_device ppc_sys_platform_devices[] = {
719 }, 716 },
720 }, 717 },
721 }, 718 },
719 [MPC85xx_MDIO] = {
720 .name = "fsl-gianfar_mdio",
721 .id = 0,
722 .dev.platform_data = &mpc85xx_mdio_pdata,
723 .num_resources = 0,
724 },
722}; 725};
723 726
724static int __init mach_mpc85xx_fixup(struct platform_device *pdev) 727static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
diff --git a/arch/ppc/syslib/mpc85xx_sys.c b/arch/ppc/syslib/mpc85xx_sys.c
index 6e3184ab354f..cb68d8c58348 100644
--- a/arch/ppc/syslib/mpc85xx_sys.c
+++ b/arch/ppc/syslib/mpc85xx_sys.c
@@ -24,19 +24,19 @@ struct ppc_sys_spec ppc_sys_specs[] = {
24 .ppc_sys_name = "8540", 24 .ppc_sys_name = "8540",
25 .mask = 0xFFFF0000, 25 .mask = 0xFFFF0000,
26 .value = 0x80300000, 26 .value = 0x80300000,
27 .num_devices = 10, 27 .num_devices = 11,
28 .device_list = (enum ppc_sys_devices[]) 28 .device_list = (enum ppc_sys_devices[])
29 { 29 {
30 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_FEC, MPC85xx_IIC1, 30 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_FEC, MPC85xx_IIC1,
31 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 31 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
32 MPC85xx_PERFMON, MPC85xx_DUART, 32 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_MDIO,
33 }, 33 },
34 }, 34 },
35 { 35 {
36 .ppc_sys_name = "8560", 36 .ppc_sys_name = "8560",
37 .mask = 0xFFFF0000, 37 .mask = 0xFFFF0000,
38 .value = 0x80700000, 38 .value = 0x80700000,
39 .num_devices = 19, 39 .num_devices = 20,
40 .device_list = (enum ppc_sys_devices[]) 40 .device_list = (enum ppc_sys_devices[])
41 { 41 {
42 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, 42 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -45,14 +45,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
45 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1, 45 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
46 MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3, MPC85xx_CPM_SCC4, 46 MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3, MPC85xx_CPM_SCC4,
47 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3, 47 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3,
48 MPC85xx_CPM_MCC1, MPC85xx_CPM_MCC2, 48 MPC85xx_CPM_MCC1, MPC85xx_CPM_MCC2, MPC85xx_MDIO,
49 }, 49 },
50 }, 50 },
51 { 51 {
52 .ppc_sys_name = "8541", 52 .ppc_sys_name = "8541",
53 .mask = 0xFFFF0000, 53 .mask = 0xFFFF0000,
54 .value = 0x80720000, 54 .value = 0x80720000,
55 .num_devices = 13, 55 .num_devices = 14,
56 .device_list = (enum ppc_sys_devices[]) 56 .device_list = (enum ppc_sys_devices[])
57 { 57 {
58 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, 58 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -60,13 +60,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
60 MPC85xx_PERFMON, MPC85xx_DUART, 60 MPC85xx_PERFMON, MPC85xx_DUART,
61 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, 61 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C,
62 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, 62 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
63 MPC85xx_MDIO,
63 }, 64 },
64 }, 65 },
65 { 66 {
66 .ppc_sys_name = "8541E", 67 .ppc_sys_name = "8541E",
67 .mask = 0xFFFF0000, 68 .mask = 0xFFFF0000,
68 .value = 0x807A0000, 69 .value = 0x807A0000,
69 .num_devices = 14, 70 .num_devices = 15,
70 .device_list = (enum ppc_sys_devices[]) 71 .device_list = (enum ppc_sys_devices[])
71 { 72 {
72 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, 73 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -74,13 +75,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
74 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, 75 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
75 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, 76 MPC85xx_CPM_SPI, MPC85xx_CPM_I2C,
76 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, 77 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
78 MPC85xx_MDIO,
77 }, 79 },
78 }, 80 },
79 { 81 {
80 .ppc_sys_name = "8555", 82 .ppc_sys_name = "8555",
81 .mask = 0xFFFF0000, 83 .mask = 0xFFFF0000,
82 .value = 0x80710000, 84 .value = 0x80710000,
83 .num_devices = 19, 85 .num_devices = 20,
84 .device_list = (enum ppc_sys_devices[]) 86 .device_list = (enum ppc_sys_devices[])
85 { 87 {
86 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, 88 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -91,13 +93,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
91 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, 93 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
92 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2, 94 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
93 MPC85xx_CPM_USB, 95 MPC85xx_CPM_USB,
96 MPC85xx_MDIO,
94 }, 97 },
95 }, 98 },
96 { 99 {
97 .ppc_sys_name = "8555E", 100 .ppc_sys_name = "8555E",
98 .mask = 0xFFFF0000, 101 .mask = 0xFFFF0000,
99 .value = 0x80790000, 102 .value = 0x80790000,
100 .num_devices = 20, 103 .num_devices = 21,
101 .device_list = (enum ppc_sys_devices[]) 104 .device_list = (enum ppc_sys_devices[])
102 { 105 {
103 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1, 106 MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
@@ -108,6 +111,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
108 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, 111 MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
109 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2, 112 MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
110 MPC85xx_CPM_USB, 113 MPC85xx_CPM_USB,
114 MPC85xx_MDIO,
111 }, 115 },
112 }, 116 },
113 /* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */ 117 /* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */
@@ -115,104 +119,112 @@ struct ppc_sys_spec ppc_sys_specs[] = {
115 .ppc_sys_name = "8548E", 119 .ppc_sys_name = "8548E",
116 .mask = 0xFFFF00F0, 120 .mask = 0xFFFF00F0,
117 .value = 0x80390010, 121 .value = 0x80390010,
118 .num_devices = 13, 122 .num_devices = 14,
119 .device_list = (enum ppc_sys_devices[]) 123 .device_list = (enum ppc_sys_devices[])
120 { 124 {
121 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, 125 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
122 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, 126 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
123 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 127 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
124 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, 128 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
129 MPC85xx_MDIO,
125 }, 130 },
126 }, 131 },
127 { 132 {
128 .ppc_sys_name = "8548", 133 .ppc_sys_name = "8548",
129 .mask = 0xFFFF00F0, 134 .mask = 0xFFFF00F0,
130 .value = 0x80310010, 135 .value = 0x80310010,
131 .num_devices = 12, 136 .num_devices = 13,
132 .device_list = (enum ppc_sys_devices[]) 137 .device_list = (enum ppc_sys_devices[])
133 { 138 {
134 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, 139 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
135 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, 140 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
136 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 141 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
137 MPC85xx_PERFMON, MPC85xx_DUART, 142 MPC85xx_PERFMON, MPC85xx_DUART,
143 MPC85xx_MDIO,
138 }, 144 },
139 }, 145 },
140 { 146 {
141 .ppc_sys_name = "8547E", 147 .ppc_sys_name = "8547E",
142 .mask = 0xFFFF00F0, 148 .mask = 0xFFFF00F0,
143 .value = 0x80390010, 149 .value = 0x80390010,
144 .num_devices = 13, 150 .num_devices = 14,
145 .device_list = (enum ppc_sys_devices[]) 151 .device_list = (enum ppc_sys_devices[])
146 { 152 {
147 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, 153 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
148 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, 154 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
149 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 155 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
150 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, 156 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
157 MPC85xx_MDIO,
151 }, 158 },
152 }, 159 },
153 { 160 {
154 .ppc_sys_name = "8547", 161 .ppc_sys_name = "8547",
155 .mask = 0xFFFF00F0, 162 .mask = 0xFFFF00F0,
156 .value = 0x80310010, 163 .value = 0x80310010,
157 .num_devices = 12, 164 .num_devices = 13,
158 .device_list = (enum ppc_sys_devices[]) 165 .device_list = (enum ppc_sys_devices[])
159 { 166 {
160 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3, 167 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
161 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2, 168 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
162 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 169 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
163 MPC85xx_PERFMON, MPC85xx_DUART, 170 MPC85xx_PERFMON, MPC85xx_DUART,
171 MPC85xx_MDIO,
164 }, 172 },
165 }, 173 },
166 { 174 {
167 .ppc_sys_name = "8545E", 175 .ppc_sys_name = "8545E",
168 .mask = 0xFFFF00F0, 176 .mask = 0xFFFF00F0,
169 .value = 0x80390010, 177 .value = 0x80390010,
170 .num_devices = 11, 178 .num_devices = 12,
171 .device_list = (enum ppc_sys_devices[]) 179 .device_list = (enum ppc_sys_devices[])
172 { 180 {
173 MPC85xx_eTSEC1, MPC85xx_eTSEC2, 181 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
174 MPC85xx_IIC1, MPC85xx_IIC2, 182 MPC85xx_IIC1, MPC85xx_IIC2,
175 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 183 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
176 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, 184 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
185 MPC85xx_MDIO,
177 }, 186 },
178 }, 187 },
179 { 188 {
180 .ppc_sys_name = "8545", 189 .ppc_sys_name = "8545",
181 .mask = 0xFFFF00F0, 190 .mask = 0xFFFF00F0,
182 .value = 0x80310010, 191 .value = 0x80310010,
183 .num_devices = 10, 192 .num_devices = 11,
184 .device_list = (enum ppc_sys_devices[]) 193 .device_list = (enum ppc_sys_devices[])
185 { 194 {
186 MPC85xx_eTSEC1, MPC85xx_eTSEC2, 195 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
187 MPC85xx_IIC1, MPC85xx_IIC2, 196 MPC85xx_IIC1, MPC85xx_IIC2,
188 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 197 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
189 MPC85xx_PERFMON, MPC85xx_DUART, 198 MPC85xx_PERFMON, MPC85xx_DUART,
199 MPC85xx_MDIO,
190 }, 200 },
191 }, 201 },
192 { 202 {
193 .ppc_sys_name = "8543E", 203 .ppc_sys_name = "8543E",
194 .mask = 0xFFFF00F0, 204 .mask = 0xFFFF00F0,
195 .value = 0x803A0010, 205 .value = 0x803A0010,
196 .num_devices = 11, 206 .num_devices = 12,
197 .device_list = (enum ppc_sys_devices[]) 207 .device_list = (enum ppc_sys_devices[])
198 { 208 {
199 MPC85xx_eTSEC1, MPC85xx_eTSEC2, 209 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
200 MPC85xx_IIC1, MPC85xx_IIC2, 210 MPC85xx_IIC1, MPC85xx_IIC2,
201 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 211 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
202 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2, 212 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
213 MPC85xx_MDIO,
203 }, 214 },
204 }, 215 },
205 { 216 {
206 .ppc_sys_name = "8543", 217 .ppc_sys_name = "8543",
207 .mask = 0xFFFF00F0, 218 .mask = 0xFFFF00F0,
208 .value = 0x80320010, 219 .value = 0x80320010,
209 .num_devices = 10, 220 .num_devices = 11,
210 .device_list = (enum ppc_sys_devices[]) 221 .device_list = (enum ppc_sys_devices[])
211 { 222 {
212 MPC85xx_eTSEC1, MPC85xx_eTSEC2, 223 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
213 MPC85xx_IIC1, MPC85xx_IIC2, 224 MPC85xx_IIC1, MPC85xx_IIC2,
214 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3, 225 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
215 MPC85xx_PERFMON, MPC85xx_DUART, 226 MPC85xx_PERFMON, MPC85xx_DUART,
227 MPC85xx_MDIO,
216 }, 228 },
217 }, 229 },
218 { /* default match */ 230 { /* default match */