[PATCH] ppc32: ppc4xx_pic - add acknowledge when enabling level-sensitive IRQ

This patch adds interrupt acknowledge to the PPC4xx PIC enable_irq
implementation for level-sensitive IRQ sources.  This helps in cases when
enable/disable_irq is used in interrupt handlers for hardware, which
requires IRQ acknowledge to be issued from non-interrupt context (e.g. 
when actual ACK in device needs an I2C transaction).  For such strange
hardware, interrupt handler disables IRQ and defers actual ACK to some
other context.  When this happens, IRQ is enabled again.  For
level-sensitive sources we get spurious triggering right after IRQ is
enabled.  This patch fixes this.

Suggested by Tolunay Orkun <listmember@orkun.us>.

Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 4 insertions, 1 deletions

diff --git a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c
index 08f06dd17e7b..05686fa73545 100644
--- a/arch/ppc/syslib/ppc4xx_pic.c
+++ b/arch/ppc/syslib/ppc4xx_pic.c
@@ -41,7 +41,10 @@ extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
 #define UIC_HANDLERS(n)                                                 \
 static void ppc4xx_uic##n##_enable(unsigned int irq)                    \
 {                                                                       \
-        ppc_cached_irq_mask[n] |= IRQ_MASK_UIC##n(irq);                 \
+        u32 mask = IRQ_MASK_UIC##n(irq);                                \
+        if (irq_desc[irq].status & IRQ_LEVEL)                           \
+                mtdcr(DCRN_UIC_SR(UIC##n), mask);                       \
+        ppc_cached_irq_mask[n] |= mask;                                 \
         mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]);             \
 }                                                                       \
                                                                         \