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authorThomas Gleixner <tglx@linutronix.de>2006-07-01 22:29:22 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 16:58:48 -0400
commitbc59d2800d535ff36dc9e6c5328b4a075076bbaa (patch)
treefc2c82e64004a769226b9de38184212bd2e351d9 /arch/ppc/syslib
parent6714465e83e784d65d0f4dbab7f2238574febfce (diff)
[PATCH] irq-flags: PPC: Use the new IRQF_ constants
Use the new IRQF_ constants and remove the SA_INTERRUPT define Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@elte.hu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/syslib')
-rw-r--r--arch/ppc/syslib/gt64260_pic.c6
-rw-r--r--arch/ppc/syslib/ibm440gx_common.c2
-rw-r--r--arch/ppc/syslib/m82xx_pci.c2
-rw-r--r--arch/ppc/syslib/mv64360_pic.c8
-rw-r--r--arch/ppc/syslib/open_pic.c15
5 files changed, 18 insertions, 15 deletions
diff --git a/arch/ppc/syslib/gt64260_pic.c b/arch/ppc/syslib/gt64260_pic.c
index 91096b38ae70..7fd550a7d586 100644
--- a/arch/ppc/syslib/gt64260_pic.c
+++ b/arch/ppc/syslib/gt64260_pic.c
@@ -297,7 +297,7 @@ gt64260_register_hdlrs(void)
297 297
298 /* Register CPU interface error interrupt handler */ 298 /* Register CPU interface error interrupt handler */
299 if ((rc = request_irq(MV64x60_IRQ_CPU_ERR, 299 if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
300 gt64260_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0))) 300 gt64260_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, 0)))
301 printk(KERN_WARNING "Can't register cpu error handler: %d", rc); 301 printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
302 302
303 mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); 303 mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
@@ -305,7 +305,7 @@ gt64260_register_hdlrs(void)
305 305
306 /* Register PCI 0 error interrupt handler */ 306 /* Register PCI 0 error interrupt handler */
307 if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler, 307 if ((rc = request_irq(MV64360_IRQ_PCI0, gt64260_pci_error_int_handler,
308 SA_INTERRUPT, PCI0_INTR_STR, (void *)0))) 308 IRQF_DISABLED, PCI0_INTR_STR, (void *)0)))
309 printk(KERN_WARNING "Can't register pci 0 error handler: %d", 309 printk(KERN_WARNING "Can't register pci 0 error handler: %d",
310 rc); 310 rc);
311 311
@@ -314,7 +314,7 @@ gt64260_register_hdlrs(void)
314 314
315 /* Register PCI 1 error interrupt handler */ 315 /* Register PCI 1 error interrupt handler */
316 if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler, 316 if ((rc = request_irq(MV64360_IRQ_PCI1, gt64260_pci_error_int_handler,
317 SA_INTERRUPT, PCI1_INTR_STR, (void *)1))) 317 IRQF_DISABLED, PCI1_INTR_STR, (void *)1)))
318 printk(KERN_WARNING "Can't register pci 1 error handler: %d", 318 printk(KERN_WARNING "Can't register pci 1 error handler: %d",
319 rc); 319 rc);
320 320
diff --git a/arch/ppc/syslib/ibm440gx_common.c b/arch/ppc/syslib/ibm440gx_common.c
index 0440d8f4ce16..4b77e6c8c87f 100644
--- a/arch/ppc/syslib/ibm440gx_common.c
+++ b/arch/ppc/syslib/ibm440gx_common.c
@@ -149,7 +149,7 @@ void __init ibm440gx_l2c_enable(void){
149 unsigned long flags; 149 unsigned long flags;
150 150
151 /* Install error handler */ 151 /* Install error handler */
152 if (request_irq(87, l2c_error_handler, SA_INTERRUPT, "L2C", 0) < 0){ 152 if (request_irq(87, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0){
153 printk(KERN_ERR "Cannot install L2C error handler, cache is not enabled\n"); 153 printk(KERN_ERR "Cannot install L2C error handler, cache is not enabled\n");
154 return; 154 return;
155 } 155 }
diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c
index 63fa5b313396..d3fa264e179e 100644
--- a/arch/ppc/syslib/m82xx_pci.c
+++ b/arch/ppc/syslib/m82xx_pci.c
@@ -139,7 +139,7 @@ pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
139 139
140static struct irqaction pq2pci_irqaction = { 140static struct irqaction pq2pci_irqaction = {
141 .handler = pq2pci_irq_demux, 141 .handler = pq2pci_irq_demux,
142 .flags = SA_INTERRUPT, 142 .flags = IRQF_DISABLED,
143 .mask = CPU_MASK_NONE, 143 .mask = CPU_MASK_NONE,
144 .name = "PQ2 PCI cascade", 144 .name = "PQ2 PCI cascade",
145}; 145};
diff --git a/arch/ppc/syslib/mv64360_pic.c b/arch/ppc/syslib/mv64360_pic.c
index a4244d468381..3f6d162f87cf 100644
--- a/arch/ppc/syslib/mv64360_pic.c
+++ b/arch/ppc/syslib/mv64360_pic.c
@@ -380,7 +380,7 @@ mv64360_register_hdlrs(void)
380 /* Clear old errors and register CPU interface error intr handler */ 380 /* Clear old errors and register CPU interface error intr handler */
381 mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0); 381 mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
382 if ((rc = request_irq(MV64x60_IRQ_CPU_ERR + mv64360_irq_base, 382 if ((rc = request_irq(MV64x60_IRQ_CPU_ERR + mv64360_irq_base,
383 mv64360_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0))) 383 mv64360_cpu_error_int_handler, IRQF_DISABLED, CPU_INTR_STR, 0)))
384 printk(KERN_WARNING "Can't register cpu error handler: %d", rc); 384 printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
385 385
386 mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); 386 mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
@@ -389,14 +389,14 @@ mv64360_register_hdlrs(void)
389 /* Clear old errors and register internal SRAM error intr handler */ 389 /* Clear old errors and register internal SRAM error intr handler */
390 mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0); 390 mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0);
391 if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR + mv64360_irq_base, 391 if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR + mv64360_irq_base,
392 mv64360_sram_error_int_handler,SA_INTERRUPT,SRAM_INTR_STR, 0))) 392 mv64360_sram_error_int_handler,IRQF_DISABLED,SRAM_INTR_STR, 0)))
393 printk(KERN_WARNING "Can't register SRAM error handler: %d",rc); 393 printk(KERN_WARNING "Can't register SRAM error handler: %d",rc);
394 394
395 /* Clear old errors and register PCI 0 error intr handler */ 395 /* Clear old errors and register PCI 0 error intr handler */
396 mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0); 396 mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0);
397 if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base, 397 if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base,
398 mv64360_pci_error_int_handler, 398 mv64360_pci_error_int_handler,
399 SA_INTERRUPT, PCI0_INTR_STR, (void *)0))) 399 IRQF_DISABLED, PCI0_INTR_STR, (void *)0)))
400 printk(KERN_WARNING "Can't register pci 0 error handler: %d", 400 printk(KERN_WARNING "Can't register pci 0 error handler: %d",
401 rc); 401 rc);
402 402
@@ -411,7 +411,7 @@ mv64360_register_hdlrs(void)
411 mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0); 411 mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0);
412 if ((rc = request_irq(MV64360_IRQ_PCI1 + mv64360_irq_base, 412 if ((rc = request_irq(MV64360_IRQ_PCI1 + mv64360_irq_base,
413 mv64360_pci_error_int_handler, 413 mv64360_pci_error_int_handler,
414 SA_INTERRUPT, PCI1_INTR_STR, (void *)1))) 414 IRQF_DISABLED, PCI1_INTR_STR, (void *)1)))
415 printk(KERN_WARNING "Can't register pci 1 error handler: %d", 415 printk(KERN_WARNING "Can't register pci 1 error handler: %d",
416 rc); 416 rc);
417 417
diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c
index 08973663fa24..aa0b95788705 100644
--- a/arch/ppc/syslib/open_pic.c
+++ b/arch/ppc/syslib/open_pic.c
@@ -575,18 +575,21 @@ void openpic_request_IPIs(void)
575 if (OpenPIC == NULL) 575 if (OpenPIC == NULL)
576 return; 576 return;
577 577
578 /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */ 578 /*
579 * IPIs are marked IRQF_DISABLED as they must run with irqs
580 * disabled
581 */
579 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset, 582 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
580 openpic_ipi_action, SA_INTERRUPT, 583 openpic_ipi_action, IRQF_DISABLED,
581 "IPI0 (call function)", NULL); 584 "IPI0 (call function)", NULL);
582 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1, 585 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
583 openpic_ipi_action, SA_INTERRUPT, 586 openpic_ipi_action, IRQF_DISABLED,
584 "IPI1 (reschedule)", NULL); 587 "IPI1 (reschedule)", NULL);
585 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2, 588 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
586 openpic_ipi_action, SA_INTERRUPT, 589 openpic_ipi_action, IRQF_DISABLED,
587 "IPI2 (invalidate tlb)", NULL); 590 "IPI2 (invalidate tlb)", NULL);
588 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3, 591 request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
589 openpic_ipi_action, SA_INTERRUPT, 592 openpic_ipi_action, IRQF_DISABLED,
590 "IPI3 (xmon break)", NULL); 593 "IPI3 (xmon break)", NULL);
591 594
592 for ( i = 0; i < OPENPIC_NUM_IPI ; i++ ) 595 for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
@@ -691,7 +694,7 @@ openpic_init_nmi_irq(u_int irq)
691 694
692static struct irqaction openpic_cascade_irqaction = { 695static struct irqaction openpic_cascade_irqaction = {
693 .handler = no_action, 696 .handler = no_action,
694 .flags = SA_INTERRUPT, 697 .flags = IRQF_DISABLED,
695 .mask = CPU_MASK_NONE, 698 .mask = CPU_MASK_NONE,
696}; 699};
697 700