aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ppc/syslib/ppc4xx_pic.c
diff options
context:
space:
mode:
authorEugene Surovegin <ebs@ebshome.net>2005-04-16 18:24:15 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:24:15 -0400
commit35b535d9cc8dce79c3b72f47c4417c3159d7a8c9 (patch)
tree48749281a9a6f4e8da9ad3d0e8dd3c88c114f723 /arch/ppc/syslib/ppc4xx_pic.c
parent16acbc624e2b7b750570cb672341d05a816051f4 (diff)
[PATCH] ppc32: ppc4xx_pic - add acknowledge when enabling level-sensitive IRQ
This patch adds interrupt acknowledge to the PPC4xx PIC enable_irq implementation for level-sensitive IRQ sources. This helps in cases when enable/disable_irq is used in interrupt handlers for hardware, which requires IRQ acknowledge to be issued from non-interrupt context (e.g. when actual ACK in device needs an I2C transaction). For such strange hardware, interrupt handler disables IRQ and defers actual ACK to some other context. When this happens, IRQ is enabled again. For level-sensitive sources we get spurious triggering right after IRQ is enabled. This patch fixes this. Suggested by Tolunay Orkun <listmember@orkun.us>. Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/syslib/ppc4xx_pic.c')
-rw-r--r--arch/ppc/syslib/ppc4xx_pic.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c
index 08f06dd17e7b..05686fa73545 100644
--- a/arch/ppc/syslib/ppc4xx_pic.c
+++ b/arch/ppc/syslib/ppc4xx_pic.c
@@ -41,7 +41,10 @@ extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
41#define UIC_HANDLERS(n) \ 41#define UIC_HANDLERS(n) \
42static void ppc4xx_uic##n##_enable(unsigned int irq) \ 42static void ppc4xx_uic##n##_enable(unsigned int irq) \
43{ \ 43{ \
44 ppc_cached_irq_mask[n] |= IRQ_MASK_UIC##n(irq); \ 44 u32 mask = IRQ_MASK_UIC##n(irq); \
45 if (irq_desc[irq].status & IRQ_LEVEL) \
46 mtdcr(DCRN_UIC_SR(UIC##n), mask); \
47 ppc_cached_irq_mask[n] |= mask; \
45 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \ 48 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
46} \ 49} \
47 \ 50 \