Merge branch 'for-2.6.22' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'for-2.6.22' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (255 commits)
  [POWERPC] Remove dev_dbg redefinition in drivers/ps3/vuart.c
  [POWERPC] remove kernel module option for booke wdt
  [POWERPC] Avoid putting cpu node twice
  [POWERPC] Spinlock initializer cleanup
  [POWERPC] ppc4xx_sgdma needs dma-mapping.h
  [POWERPC] arch/powerpc/sysdev/timer.c build fix
  [POWERPC] get_property cleanups
  [POWERPC] Remove the unused HTDMSOUND driver
  [POWERPC] cell: cbe_cpufreq cleanup and crash fix
  [POWERPC] Declare enable_kernel_spe in a header
  [POWERPC] Add dt_xlate_addr() to bootwrapper
  [POWERPC] bootwrapper: CONFIG_ -> CONFIG_DEVICE_TREE
  [POWERPC] Don't define a custom bd_t for Xilixn Virtex based boards.
  [POWERPC] Add sane defaults for Xilinx EDK generated xparameters files
  [POWERPC] Add uartlite boot console driver for the zImage wrapper
  [POWERPC] Stop using ppc_sys for Xilinx Virtex boards
  [POWERPC] New registration for common Xilinx Virtex ppc405 platform devices
  [POWERPC] Merge common virtex header files
  [POWERPC] Rework Kconfig dependancies for Xilinx Virtex ppc405 platform
  [POWERPC] Clean up cpufreq Kconfig dependencies
  ...

1 files changed, 0 insertions, 81 deletions

diff --git a/arch/ppc/syslib/cpc710.h b/arch/ppc/syslib/cpc710.h
deleted file mode 100644
index 5299bf8b5d01..000000000000
--- a/arch/ppc/syslib/cpc710.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Definitions for the IBM CPC710 PCI Host Bridge
- *
- * Author: Matt Porter <mporter@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PPC_PLATFORMS_CPC710_H
-#define __PPC_PLATFORMS_CPC710_H
-
-/* General bridge and memory controller registers */
-#define PIDR    0xff000008
-#define CNFR    0xff00000c
-#define RSTR    0xff000010
-#define UCTL    0xff001000
-#define MPSR    0xff001010
-#define SIOC    0xff001020
-#define ABCNTL  0xff001030
-#define SRST    0xff001040
-#define ERRC    0xff001050
-#define SESR    0xff001060
-#define SEAR    0xff001070
-#define SIOC1   0xff001090
-#define PGCHP   0xff001100
-#define GPDIR   0xff001130
-#define GPOUT   0xff001150
-#define ATAS    0xff001160
-#define AVDG    0xff001170
-#define MCCR    0xff001200
-#define MESR    0xff001220
-#define MEAR    0xff001230
-#define MCER0   0xff001300
-#define MCER1   0xff001310
-#define MCER2   0xff001320
-#define MCER3   0xff001330
-#define MCER4   0xff001340
-#define MCER5   0xff001350
-#define MCER6   0xff001360
-#define MCER7   0xff001370
-
-/*
- * PCI32/64 configuration registers
- * Given as offsets from their
- * respective physical segment BAR
- */
-#define PIBAR   0x000f7800
-#define PMBAR   0x000f7810
-#define MSIZE   0x000f7f40
-#define IOSIZE  0x000f7f60
-#define SMBAR   0x000f7f80
-#define SIBAR   0x000f7fc0
-#define PSSIZE  0x000f8100
-#define PPSIZE  0x000f8110
-#define BARPS   0x000f8120
-#define BARPP   0x000f8130
-#define PSBAR   0x000f8140
-#define PPBAR   0x000f8150
-#define BPMDLK  0x000f8200      /* Bottom of Peripheral Memory Space */
-#define TPMDLK  0x000f8210      /* Top of Peripheral Memory Space */
-#define BIODLK  0x000f8220      /* Bottom of Peripheral I/O Space */
-#define TIODLK  0x000f8230      /* Top of Perioheral I/O Space */
-#define DLKCTRL 0x000f8240      /* Deadlock control */
-#define DLKDEV  0x000f8250      /* Deadlock device */
-
-/* System standard configuration registers space */
-#define DCR     0xff200000
-#define DID     0xff200004
-#define BAR     0xff200018
-
-/* Device specific configuration space */
-#define PCIENB  0xff201000
-
-/* Configuration space registers */
-#define CPC710_BUS_NUMBER       0x40
-#define CPC710_SUB_BUS_NUMBER   0x41
-
-#endif /* __PPC_PLATFORMS_CPC710_H */