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authorKumar Gala <galak@kernel.crashing.org>2008-01-27 15:06:14 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 09:33:10 -0500
commitc42f3ad7f1bf17f31c3febdc71034ed6d793d40f (patch)
tree5a56c44717cf8fe4a5f402370506e5fbb78368e4 /arch/ppc/platforms
parent3155f7f23f7865e64f7eb14e226a2dff8197e51f (diff)
[PPC] Remove 85xx from arch/ppc
85xx exists in arch/powerpc as well as cuImage support to boot from a u-boot that doesn't support device trees. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r--arch/ppc/platforms/85xx/Kconfig106
-rw-r--r--arch/ppc/platforms/85xx/Makefile13
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.c226
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.h22
-rw-r--r--arch/ppc/platforms/85xx/mpc8555_cds.h23
-rw-r--r--arch/ppc/platforms/85xx/mpc8560_ads.c303
-rw-r--r--arch/ppc/platforms/85xx/mpc8560_ads.h24
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_ads_common.c197
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_ads_common.h67
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.c601
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.h80
-rw-r--r--arch/ppc/platforms/85xx/sbc8560.c234
-rw-r--r--arch/ppc/platforms/85xx/sbc8560.h47
-rw-r--r--arch/ppc/platforms/85xx/sbc85xx.c166
-rw-r--r--arch/ppc/platforms/85xx/sbc85xx.h70
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.c339
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.h69
-rw-r--r--arch/ppc/platforms/85xx/tqm85xx.c412
-rw-r--r--arch/ppc/platforms/85xx/tqm85xx.h53
19 files changed, 0 insertions, 3052 deletions
diff --git a/arch/ppc/platforms/85xx/Kconfig b/arch/ppc/platforms/85xx/Kconfig
deleted file mode 100644
index 6f2d0add7de6..000000000000
--- a/arch/ppc/platforms/85xx/Kconfig
+++ /dev/null
@@ -1,106 +0,0 @@
1config 85xx
2 bool
3 depends on E500
4 default y
5
6config PPC_INDIRECT_PCI_BE
7 bool
8 depends on 85xx
9 default y
10
11menu "Freescale 85xx options"
12 depends on E500
13
14choice
15 prompt "Machine Type"
16 depends on 85xx
17 default MPC8540_ADS
18
19config MPC8540_ADS
20 bool "Freescale MPC8540 ADS"
21 help
22 This option enables support for the MPC 8540 ADS evaluation board.
23
24config MPC8548_CDS
25 bool "Freescale MPC8548 CDS"
26 help
27 This option enables support for the MPC8548 CDS evaluation board.
28
29config MPC8555_CDS
30 bool "Freescale MPC8555 CDS"
31 help
32 This option enables support for the MPC8555 CDS evaluation board.
33
34config MPC8560_ADS
35 bool "Freescale MPC8560 ADS"
36 help
37 This option enables support for the MPC 8560 ADS evaluation board.
38
39config SBC8560
40 bool "WindRiver PowerQUICC III SBC8560"
41 help
42 This option enables support for the WindRiver PowerQUICC III
43 SBC8560 board.
44
45config STX_GP3
46 bool "Silicon Turnkey Express GP3"
47 help
48 This option enables support for the Silicon Turnkey Express GP3
49 board.
50
51config TQM8540
52 bool "TQ Components TQM8540"
53 help
54 This option enables support for the TQ Components TQM8540 board.
55
56config TQM8541
57 bool "TQ Components TQM8541"
58 help
59 This option enables support for the TQ Components TQM8541 board.
60
61config TQM8555
62 bool "TQ Components TQM8555"
63 help
64 This option enables support for the TQ Components TQM8555 board.
65
66config TQM8560
67 bool "TQ Components TQM8560"
68 help
69 This option enables support for the TQ Components TQM8560 board.
70
71endchoice
72
73# It's often necessary to know the specific 85xx processor type.
74# Fortunately, it is implied (so far) from the board type, so we
75# don't need to ask more redundant questions.
76config MPC8540
77 bool
78 depends on MPC8540_ADS || TQM8540
79 default y
80
81config MPC8548
82 bool
83 depends on MPC8548_CDS
84 default y
85
86config MPC8555
87 bool
88 depends on MPC8555_CDS || TQM8541 || TQM8555
89 default y
90
91config MPC8560
92 bool
93 depends on SBC8560 || MPC8560_ADS || STX_GP3 || TQM8560
94 default y
95
96config 85xx_PCI2
97 bool "Support for 2nd PCI host controller"
98 depends on MPC8555_CDS
99 default y
100
101config PPC_GEN550
102 bool
103 depends on MPC8540 || SBC8560 || MPC8555
104 default y
105
106endmenu
diff --git a/arch/ppc/platforms/85xx/Makefile b/arch/ppc/platforms/85xx/Makefile
deleted file mode 100644
index 6c4753c144d3..000000000000
--- a/arch/ppc/platforms/85xx/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
1#
2# Makefile for the PowerPC 85xx linux kernel.
3#
4obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads_common.o mpc8540_ads.o
5obj-$(CONFIG_MPC8548_CDS) += mpc85xx_cds_common.o
6obj-$(CONFIG_MPC8555_CDS) += mpc85xx_cds_common.o
7obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads_common.o mpc8560_ads.o
8obj-$(CONFIG_SBC8560) += sbc85xx.o sbc8560.o
9obj-$(CONFIG_STX_GP3) += stx_gp3.o
10obj-$(CONFIG_TQM8540) += tqm85xx.o
11obj-$(CONFIG_TQM8541) += tqm85xx.o
12obj-$(CONFIG_TQM8555) += tqm85xx.o
13obj-$(CONFIG_TQM8560) += tqm85xx.o
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c
deleted file mode 100644
index 00a3ba57063f..000000000000
--- a/arch/ppc/platforms/85xx/mpc8540_ads.c
+++ /dev/null
@@ -1,226 +0,0 @@
1/*
2 * MPC8540ADS board specific routines
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/major.h>
22#include <linux/console.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/root_dev.h>
26#include <linux/serial.h>
27#include <linux/tty.h> /* for linux/serial_core.h */
28#include <linux/serial_core.h>
29#include <linux/initrd.h>
30#include <linux/module.h>
31#include <linux/fsl_devices.h>
32
33#include <asm/system.h>
34#include <asm/pgtable.h>
35#include <asm/page.h>
36#include <asm/atomic.h>
37#include <asm/time.h>
38#include <asm/io.h>
39#include <asm/machdep.h>
40#include <asm/open_pic.h>
41#include <asm/bootinfo.h>
42#include <asm/pci-bridge.h>
43#include <asm/mpc85xx.h>
44#include <asm/irq.h>
45#include <asm/immap_85xx.h>
46#include <asm/kgdb.h>
47#include <asm/ppc_sys.h>
48#include <mm/mmu_decl.h>
49
50#include <syslib/ppc85xx_setup.h>
51
52/* ************************************************************************
53 *
54 * Setup the architecture
55 *
56 */
57static void __init
58mpc8540ads_setup_arch(void)
59{
60 bd_t *binfo = (bd_t *) __res;
61 unsigned int freq;
62 struct gianfar_platform_data *pdata;
63 struct gianfar_mdio_data *mdata;
64
65 /* get the core frequency */
66 freq = binfo->bi_intfreq;
67
68 if (ppc_md.progress)
69 ppc_md.progress("mpc8540ads_setup_arch()", 0);
70
71 /* Set loops_per_jiffy to a half-way reasonable value,
72 for use until calibrate_delay gets called. */
73 loops_per_jiffy = freq / HZ;
74
75#ifdef CONFIG_PCI
76 /* setup PCI host bridges */
77 mpc85xx_setup_hose();
78#endif
79
80#ifdef CONFIG_SERIAL_8250
81 mpc85xx_early_serial_map();
82#endif
83
84#ifdef CONFIG_SERIAL_TEXT_DEBUG
85 /* Invalidate the entry we stole earlier the serial ports
86 * should be properly mapped */
87 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
88#endif
89
90 /* setup the board related info for the MDIO bus */
91 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
92
93 mdata->irq[0] = MPC85xx_IRQ_EXT5;
94 mdata->irq[1] = MPC85xx_IRQ_EXT5;
95 mdata->irq[2] = PHY_POLL;
96 mdata->irq[3] = MPC85xx_IRQ_EXT5;
97 mdata->irq[31] = PHY_POLL;
98
99 /* setup the board related information for the enet controllers */
100 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
101 if (pdata) {
102 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
103 pdata->bus_id = 0;
104 pdata->phy_id = 0;
105 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
106 }
107
108 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
109 if (pdata) {
110 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
111 pdata->bus_id = 0;
112 pdata->phy_id = 1;
113 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
114 }
115
116 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);
117 if (pdata) {
118 pdata->board_flags = 0;
119 pdata->bus_id = 0;
120 pdata->phy_id = 3;
121 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);
122 }
123
124#ifdef CONFIG_BLK_DEV_INITRD
125 if (initrd_start)
126 ROOT_DEV = Root_RAM0;
127 else
128#endif
129#ifdef CONFIG_ROOT_NFS
130 ROOT_DEV = Root_NFS;
131#else
132 ROOT_DEV = Root_HDA1;
133#endif
134}
135
136/* ************************************************************************ */
137void __init
138platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
139 unsigned long r6, unsigned long r7)
140{
141 /* parse_bootinfo must always be called first */
142 parse_bootinfo(find_bootinfo());
143
144 /*
145 * If we were passed in a board information, copy it into the
146 * residual data area.
147 */
148 if (r3) {
149 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
150 sizeof (bd_t));
151 }
152#ifdef CONFIG_SERIAL_TEXT_DEBUG
153 {
154 bd_t *binfo = (bd_t *) __res;
155 struct uart_port p;
156
157 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
158 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
159 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
160
161 memset(&p, 0, sizeof (p));
162 p.iotype = UPIO_MEM;
163 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
164 p.uartclk = binfo->bi_busfreq;
165
166 gen550_init(0, &p);
167
168 memset(&p, 0, sizeof (p));
169 p.iotype = UPIO_MEM;
170 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
171 p.uartclk = binfo->bi_busfreq;
172
173 gen550_init(1, &p);
174 }
175#endif
176
177#if defined(CONFIG_BLK_DEV_INITRD)
178 /*
179 * If the init RAM disk has been configured in, and there's a valid
180 * starting address for it, set it up.
181 */
182 if (r4) {
183 initrd_start = r4 + KERNELBASE;
184 initrd_end = r5 + KERNELBASE;
185 }
186#endif /* CONFIG_BLK_DEV_INITRD */
187
188 /* Copy the kernel command line arguments to a safe place. */
189
190 if (r6) {
191 *(char *) (r7 + KERNELBASE) = 0;
192 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
193 }
194
195 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
196
197 /* setup the PowerPC module struct */
198 ppc_md.setup_arch = mpc8540ads_setup_arch;
199 ppc_md.show_cpuinfo = mpc85xx_ads_show_cpuinfo;
200
201 ppc_md.init_IRQ = mpc85xx_ads_init_IRQ;
202 ppc_md.get_irq = openpic_get_irq;
203
204 ppc_md.restart = mpc85xx_restart;
205 ppc_md.power_off = mpc85xx_power_off;
206 ppc_md.halt = mpc85xx_halt;
207
208 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
209
210 ppc_md.time_init = NULL;
211 ppc_md.set_rtc_time = NULL;
212 ppc_md.get_rtc_time = NULL;
213 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
214
215#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
216 ppc_md.progress = gen550_progress;
217#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
218#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
219 ppc_md.early_serial_map = mpc85xx_early_serial_map;
220#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
221
222 if (ppc_md.progress)
223 ppc_md.progress("mpc8540ads_init(): exit", 0);
224
225 return;
226}
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.h b/arch/ppc/platforms/85xx/mpc8540_ads.h
deleted file mode 100644
index 7559f9e6fc28..000000000000
--- a/arch/ppc/platforms/85xx/mpc8540_ads.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * MPC8540ADS board definitions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MACH_MPC8540ADS_H__
16#define __MACH_MPC8540ADS_H__
17
18#include <linux/initrd.h>
19#include <syslib/ppc85xx_setup.h>
20#include <platforms/85xx/mpc85xx_ads_common.h>
21
22#endif /* __MACH_MPC8540ADS_H__ */
diff --git a/arch/ppc/platforms/85xx/mpc8555_cds.h b/arch/ppc/platforms/85xx/mpc8555_cds.h
deleted file mode 100644
index 4f79c372c4e7..000000000000
--- a/arch/ppc/platforms/85xx/mpc8555_cds.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * MPC8555CDS board definitions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MACH_MPC8555CDS_H__
16#define __MACH_MPC8555CDS_H__
17
18#include <syslib/ppc85xx_setup.h>
19#include <platforms/85xx/mpc85xx_cds_common.h>
20
21#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
22
23#endif /* __MACH_MPC8555CDS_H__ */
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c
deleted file mode 100644
index 3a060468dd95..000000000000
--- a/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ /dev/null
@@ -1,303 +0,0 @@
1/*
2 * MPC8560ADS board specific routines
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/major.h>
22#include <linux/console.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/root_dev.h>
26#include <linux/serial.h>
27#include <linux/tty.h> /* for linux/serial_core.h */
28#include <linux/serial_core.h>
29#include <linux/initrd.h>
30#include <linux/module.h>
31#include <linux/fsl_devices.h>
32#include <linux/fs_enet_pd.h>
33
34#include <asm/system.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/atomic.h>
38#include <asm/time.h>
39#include <asm/io.h>
40#include <asm/machdep.h>
41#include <asm/open_pic.h>
42#include <asm/bootinfo.h>
43#include <asm/pci-bridge.h>
44#include <asm/mpc85xx.h>
45#include <asm/irq.h>
46#include <asm/immap_85xx.h>
47#include <asm/kgdb.h>
48#include <asm/ppc_sys.h>
49#include <asm/cpm2.h>
50#include <mm/mmu_decl.h>
51
52#include <syslib/cpm2_pic.h>
53#include <syslib/ppc85xx_common.h>
54#include <syslib/ppc85xx_setup.h>
55
56
57/* ************************************************************************
58 *
59 * Setup the architecture
60 *
61 */
62static void init_fcc_ioports(void)
63{
64 struct immap *immap;
65 struct io_port *io;
66 u32 tempval;
67
68 immap = cpm2_immr;
69
70 io = &immap->im_ioport;
71 /* FCC2/3 are on the ports B/C. */
72 tempval = in_be32(&io->iop_pdirb);
73 tempval &= ~PB2_DIRB0;
74 tempval |= PB2_DIRB1;
75 out_be32(&io->iop_pdirb, tempval);
76
77 tempval = in_be32(&io->iop_psorb);
78 tempval &= ~PB2_PSORB0;
79 tempval |= PB2_PSORB1;
80 out_be32(&io->iop_psorb, tempval);
81
82 tempval = in_be32(&io->iop_pparb);
83 tempval |= (PB2_DIRB0 | PB2_DIRB1);
84 out_be32(&io->iop_pparb, tempval);
85
86 tempval = in_be32(&io->iop_pdirb);
87 tempval &= ~PB3_DIRB0;
88 tempval |= PB3_DIRB1;
89 out_be32(&io->iop_pdirb, tempval);
90
91 tempval = in_be32(&io->iop_psorb);
92 tempval &= ~PB3_PSORB0;
93 tempval |= PB3_PSORB1;
94 out_be32(&io->iop_psorb, tempval);
95
96 tempval = in_be32(&io->iop_pparb);
97 tempval |= (PB3_DIRB0 | PB3_DIRB1);
98 out_be32(&io->iop_pparb, tempval);
99
100 tempval = in_be32(&io->iop_pdirc);
101 tempval |= PC3_DIRC1;
102 out_be32(&io->iop_pdirc, tempval);
103
104 tempval = in_be32(&io->iop_pparc);
105 tempval |= PC3_DIRC1;
106 out_be32(&io->iop_pparc, tempval);
107
108 /* Port C has clocks...... */
109 tempval = in_be32(&io->iop_psorc);
110 tempval &= ~(CLK_TRX);
111 out_be32(&io->iop_psorc, tempval);
112
113 tempval = in_be32(&io->iop_pdirc);
114 tempval &= ~(CLK_TRX);
115 out_be32(&io->iop_pdirc, tempval);
116 tempval = in_be32(&io->iop_pparc);
117 tempval |= (CLK_TRX);
118 out_be32(&io->iop_pparc, tempval);
119
120 /* Configure Serial Interface clock routing.
121 * First, clear all FCC bits to zero,
122 * then set the ones we want.
123 */
124 immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK);
125 immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE;
126}
127
128static void __init
129mpc8560ads_setup_arch(void)
130{
131 bd_t *binfo = (bd_t *) __res;
132 unsigned int freq;
133 struct gianfar_platform_data *pdata;
134 struct gianfar_mdio_data *mdata;
135 struct fs_platform_info *fpi;
136
137 cpm2_reset();
138
139 /* get the core frequency */
140 freq = binfo->bi_intfreq;
141
142 if (ppc_md.progress)
143 ppc_md.progress("mpc8560ads_setup_arch()", 0);
144
145 /* Set loops_per_jiffy to a half-way reasonable value,
146 for use until calibrate_delay gets called. */
147 loops_per_jiffy = freq / HZ;
148
149#ifdef CONFIG_PCI
150 /* setup PCI host bridges */
151 mpc85xx_setup_hose();
152#endif
153
154 /* setup the board related info for the MDIO bus */
155 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
156
157 mdata->irq[0] = MPC85xx_IRQ_EXT5;
158 mdata->irq[1] = MPC85xx_IRQ_EXT5;
159 mdata->irq[2] = PHY_POLL;
160 mdata->irq[3] = MPC85xx_IRQ_EXT5;
161 mdata->irq[31] = PHY_POLL;
162
163 /* setup the board related information for the enet controllers */
164 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
165 if (pdata) {
166 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
167 pdata->bus_id = 0;
168 pdata->phy_id = 0;
169 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
170 }
171
172 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
173 if (pdata) {
174 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
175 pdata->bus_id = 0;
176 pdata->phy_id = 1;
177 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
178 }
179
180 init_fcc_ioports();
181 ppc_sys_device_remove(MPC85xx_CPM_FCC1);
182
183 fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2);
184 if (fpi) {
185 memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
186 fpi->bus_id = "0:02";
187 fpi->phy_addr = 2;
188 fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
189 fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1];
190 }
191
192 fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3);
193 if (fpi) {
194 memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
195 fpi->macaddr[5] += 1;
196 fpi->bus_id = "0:03";
197 fpi->phy_addr = 3;
198 fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
199 fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2];
200 }
201
202#ifdef CONFIG_BLK_DEV_INITRD
203 if (initrd_start)
204 ROOT_DEV = Root_RAM0;
205 else
206#endif
207#ifdef CONFIG_ROOT_NFS
208 ROOT_DEV = Root_NFS;
209#else
210 ROOT_DEV = Root_HDA1;
211#endif
212}
213
214static irqreturn_t cpm2_cascade(int irq, void *dev_id)
215{
216 while ((irq = cpm2_get_irq()) >= 0)
217 __do_IRQ(irq);
218 return IRQ_HANDLED;
219}
220
221static struct irqaction cpm2_irqaction = {
222 .handler = cpm2_cascade,
223 .flags = IRQF_DISABLED,
224 .mask = CPU_MASK_NONE,
225 .name = "cpm2_cascade",
226};
227
228static void __init
229mpc8560_ads_init_IRQ(void)
230{
231 /* Setup OpenPIC */
232 mpc85xx_ads_init_IRQ();
233
234 /* Setup CPM2 PIC */
235 cpm2_init_IRQ();
236
237 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
238
239 return;
240}
241
242
243
244/* ************************************************************************ */
245void __init
246platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
247 unsigned long r6, unsigned long r7)
248{
249 /* parse_bootinfo must always be called first */
250 parse_bootinfo(find_bootinfo());
251
252 /*
253 * If we were passed in a board information, copy it into the
254 * residual data area.
255 */
256 if (r3) {
257 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
258 sizeof (bd_t));
259
260 }
261#if defined(CONFIG_BLK_DEV_INITRD)
262 /*
263 * If the init RAM disk has been configured in, and there's a valid
264 * starting address for it, set it up.
265 */
266 if (r4) {
267 initrd_start = r4 + KERNELBASE;
268 initrd_end = r5 + KERNELBASE;
269 }
270#endif /* CONFIG_BLK_DEV_INITRD */
271
272 /* Copy the kernel command line arguments to a safe place. */
273
274 if (r6) {
275 *(char *) (r7 + KERNELBASE) = 0;
276 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
277 }
278
279 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
280
281 /* setup the PowerPC module struct */
282 ppc_md.setup_arch = mpc8560ads_setup_arch;
283 ppc_md.show_cpuinfo = mpc85xx_ads_show_cpuinfo;
284
285 ppc_md.init_IRQ = mpc8560_ads_init_IRQ;
286 ppc_md.get_irq = openpic_get_irq;
287
288 ppc_md.restart = mpc85xx_restart;
289 ppc_md.power_off = mpc85xx_power_off;
290 ppc_md.halt = mpc85xx_halt;
291
292 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
293
294 ppc_md.time_init = NULL;
295 ppc_md.set_rtc_time = NULL;
296 ppc_md.get_rtc_time = NULL;
297 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
298
299 if (ppc_md.progress)
300 ppc_md.progress("mpc8560ads_init(): exit", 0);
301
302 return;
303}
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.h b/arch/ppc/platforms/85xx/mpc8560_ads.h
deleted file mode 100644
index 9f185ab2e019..000000000000
--- a/arch/ppc/platforms/85xx/mpc8560_ads.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * MPC8540ADS board definitions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MACH_MPC8560ADS_H
16#define __MACH_MPC8560ADS_H
17
18#include <syslib/ppc85xx_setup.h>
19#include <platforms/85xx/mpc85xx_ads_common.h>
20
21#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
22#define PHY_INTERRUPT MPC85xx_IRQ_EXT7
23
24#endif /* __MACH_MPC8560ADS_H */
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
deleted file mode 100644
index 0706dca5a8ea..000000000000
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
+++ /dev/null
@@ -1,197 +0,0 @@
1/*
2 * MPC85xx ADS board common routines
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/major.h>
22#include <linux/console.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/serial.h>
26#include <linux/module.h>
27
28#include <asm/system.h>
29#include <asm/pgtable.h>
30#include <asm/page.h>
31#include <asm/atomic.h>
32#include <asm/time.h>
33#include <asm/io.h>
34#include <asm/machdep.h>
35#include <asm/open_pic.h>
36#include <asm/bootinfo.h>
37#include <asm/pci-bridge.h>
38#include <asm/mpc85xx.h>
39#include <asm/irq.h>
40#include <asm/immap_85xx.h>
41#include <asm/ppc_sys.h>
42
43#include <mm/mmu_decl.h>
44
45#include <platforms/85xx/mpc85xx_ads_common.h>
46
47#ifndef CONFIG_PCI
48unsigned long isa_io_base = 0;
49unsigned long isa_mem_base = 0;
50#endif
51
52extern unsigned long total_memory; /* in mm/init */
53
54unsigned char __res[sizeof (bd_t)];
55
56/* Internal interrupts are all Level Sensitive, and Positive Polarity */
57static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
58 MPC85XX_INTERNAL_IRQ_SENSES,
59 0x0, /* External 0: */
60#if defined(CONFIG_PCI)
61 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 1 */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 2 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 3 */
65#else
66 0x0, /* External 1: */
67 0x0, /* External 2: */
68 0x0, /* External 3: */
69 0x0, /* External 4: */
70#endif
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
72 0x0, /* External 6: */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
74 0x0, /* External 8: */
75 0x0, /* External 9: */
76 0x0, /* External 10: */
77 0x0, /* External 11: */
78};
79
80/* ************************************************************************ */
81int
82mpc85xx_ads_show_cpuinfo(struct seq_file *m)
83{
84 uint pvid, svid, phid1;
85 uint memsize = total_memory;
86 bd_t *binfo = (bd_t *) __res;
87 unsigned int freq;
88
89 /* get the core frequency */
90 freq = binfo->bi_intfreq;
91
92 pvid = mfspr(SPRN_PVR);
93 svid = mfspr(SPRN_SVR);
94
95 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
96 seq_printf(m, "Machine\t\t: mpc%sads\n", cur_ppc_sys_spec->ppc_sys_name);
97 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
98 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
99 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
100
101 /* Display cpu Pll setting */
102 phid1 = mfspr(SPRN_HID1);
103 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
104
105 /* Display the amount of memory */
106 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
107
108 return 0;
109}
110
111void __init
112mpc85xx_ads_init_IRQ(void)
113{
114 bd_t *binfo = (bd_t *) __res;
115 /* Determine the Physical Address of the OpenPIC regs */
116 phys_addr_t OpenPIC_PAddr =
117 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
118 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
119 OpenPIC_InitSenses = mpc85xx_ads_openpic_initsenses;
120 OpenPIC_NumInitSenses = sizeof (mpc85xx_ads_openpic_initsenses);
121
122 /* Skip reserved space and internal sources */
123 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
124 /* Map PIC IRQs 0-11 */
125 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
126
127 /* we let openpic interrupts starting from an offset, to
128 * leave space for cascading interrupts underneath.
129 */
130 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
131
132 return;
133}
134
135#ifdef CONFIG_PCI
136/*
137 * interrupt routing
138 */
139
140int
141mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
142{
143 static char pci_irq_table[][4] =
144 /*
145 * This is little evil, but works around the fact
146 * that revA boards have IDSEL starting at 18
147 * and others boards (older) start at 12
148 *
149 * PCI IDSEL/INTPIN->INTLINE
150 * A B C D
151 */
152 {
153 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 2 */
154 {PIRQD, PIRQA, PIRQB, PIRQC},
155 {PIRQC, PIRQD, PIRQA, PIRQB},
156 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 5 */
157 {0, 0, 0, 0}, /* -- */
158 {0, 0, 0, 0}, /* -- */
159 {0, 0, 0, 0}, /* -- */
160 {0, 0, 0, 0}, /* -- */
161 {0, 0, 0, 0}, /* -- */
162 {0, 0, 0, 0}, /* -- */
163 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 12 */
164 {PIRQD, PIRQA, PIRQB, PIRQC},
165 {PIRQC, PIRQD, PIRQA, PIRQB},
166 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 15 */
167 {0, 0, 0, 0}, /* -- */
168 {0, 0, 0, 0}, /* -- */
169 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 18 */
170 {PIRQD, PIRQA, PIRQB, PIRQC},
171 {PIRQC, PIRQD, PIRQA, PIRQB},
172 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 21 */
173 };
174
175 const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
176 return PCI_IRQ_TABLE_LOOKUP;
177}
178
179int
180mpc85xx_exclude_device(u_char bus, u_char devfn)
181{
182 if (bus == 0 && PCI_SLOT(devfn) == 0)
183 return PCIBIOS_DEVICE_NOT_FOUND;
184 else
185 return PCIBIOS_SUCCESSFUL;
186}
187
188#endif /* CONFIG_PCI */
189
190#ifdef CONFIG_RAPIDIO
191extern void mpc85xx_rio_setup(int law_start, int law_size);
192void platform_rio_init(void)
193{
194 /* 512MB RIO LAW at 0xc0000000 */
195 mpc85xx_rio_setup(0xc0000000, 0x20000000);
196}
197#endif /* CONFIG_RAPIDIO */
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
deleted file mode 100644
index c8c322fe3680..000000000000
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * MPC85XX ADS common board definitions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MACH_MPC85XX_ADS_H__
16#define __MACH_MPC85XX_ADS_H__
17
18#include <linux/init.h>
19#include <asm/ppcboot.h>
20
21#define BOARD_CCSRBAR ((uint)0xe0000000)
22#define BCSR_ADDR ((uint)0xf8000000)
23#define BCSR_SIZE ((uint)(32 * 1024))
24
25struct seq_file;
26
27extern int mpc85xx_ads_show_cpuinfo(struct seq_file *m);
28extern void mpc85xx_ads_init_IRQ(void) __init;
29extern void mpc85xx_ads_map_io(void) __init;
30
31/* PCI interrupt controller */
32#define PIRQA MPC85xx_IRQ_EXT1
33#define PIRQB MPC85xx_IRQ_EXT2
34#define PIRQC MPC85xx_IRQ_EXT3
35#define PIRQD MPC85xx_IRQ_EXT4
36
37#define MPC85XX_PCI1_LOWER_IO 0x00000000
38#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
39
40#define MPC85XX_PCI1_LOWER_MEM 0x80000000
41#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
42
43#define MPC85XX_PCI1_IO_BASE 0xe2000000
44#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
45
46#define MPC85XX_PCI1_IO_SIZE 0x01000000
47
48/* FCC1 Clock Source Configuration. These can be
49 * redefined in the board specific file.
50 * Can only choose from CLK9-12 */
51#define F1_RXCLK 12
52#define F1_TXCLK 11
53
54/* FCC2 Clock Source Configuration. These can be
55 * redefined in the board specific file.
56 * Can only choose from CLK13-16 */
57#define F2_RXCLK 13
58#define F2_TXCLK 14
59
60/* FCC3 Clock Source Configuration. These can be
61 * redefined in the board specific file.
62 * Can only choose from CLK13-16 */
63#define F3_RXCLK 15
64#define F3_TXCLK 16
65
66
67#endif /* __MACH_MPC85XX_ADS_H__ */
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
deleted file mode 100644
index 2d59eb776c95..000000000000
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ /dev/null
@@ -1,601 +0,0 @@
1/*
2 * MPC85xx CDS board specific routines
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/major.h>
22#include <linux/console.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/serial.h>
26#include <linux/module.h>
27#include <linux/root_dev.h>
28#include <linux/initrd.h>
29#include <linux/tty.h>
30#include <linux/serial_core.h>
31#include <linux/fsl_devices.h>
32
33#include <asm/system.h>
34#include <asm/pgtable.h>
35#include <asm/page.h>
36#include <asm/atomic.h>
37#include <asm/time.h>
38#include <asm/todc.h>
39#include <asm/io.h>
40#include <asm/machdep.h>
41#include <asm/open_pic.h>
42#include <asm/i8259.h>
43#include <asm/bootinfo.h>
44#include <asm/pci-bridge.h>
45#include <asm/mpc85xx.h>
46#include <asm/irq.h>
47#include <asm/immap_85xx.h>
48#include <asm/cpm2.h>
49#include <asm/ppc_sys.h>
50#include <asm/kgdb.h>
51
52#include <mm/mmu_decl.h>
53#include <syslib/cpm2_pic.h>
54#include <syslib/ppc85xx_common.h>
55#include <syslib/ppc85xx_setup.h>
56
57
58#ifndef CONFIG_PCI
59unsigned long isa_io_base = 0;
60unsigned long isa_mem_base = 0;
61#endif
62
63extern unsigned long total_memory; /* in mm/init */
64
65unsigned char __res[sizeof (bd_t)];
66
67static int cds_pci_slot = 2;
68static volatile u8 * cadmus;
69
70/* Internal interrupts are all Level Sensitive, and Positive Polarity */
71static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
72 MPC85XX_INTERNAL_IRQ_SENSES,
73#if defined(CONFIG_PCI)
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
78#else
79 0x0, /* External 0: */
80 0x0, /* External 1: */
81 0x0, /* External 2: */
82 0x0, /* External 3: */
83#endif
84 0x0, /* External 4: */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
86 0x0, /* External 6: */
87 0x0, /* External 7: */
88 0x0, /* External 8: */
89 0x0, /* External 9: */
90 0x0, /* External 10: */
91#if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
93#else
94 0x0, /* External 11: */
95#endif
96};
97
98/* ************************************************************************ */
99int
100mpc85xx_cds_show_cpuinfo(struct seq_file *m)
101{
102 uint pvid, svid, phid1;
103 uint memsize = total_memory;
104 bd_t *binfo = (bd_t *) __res;
105 unsigned int freq;
106
107 /* get the core frequency */
108 freq = binfo->bi_intfreq;
109
110 pvid = mfspr(SPRN_PVR);
111 svid = mfspr(SPRN_SVR);
112
113 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
114 seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
115 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
116 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
117 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
118
119 /* Display cpu Pll setting */
120 phid1 = mfspr(SPRN_HID1);
121 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
122
123 /* Display the amount of memory */
124 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
125
126 return 0;
127}
128
129#ifdef CONFIG_CPM2
130static irqreturn_t cpm2_cascade(int irq, void *dev_id)
131{
132 while((irq = cpm2_get_irq()) >= 0)
133 __do_IRQ(irq);
134 return IRQ_HANDLED;
135}
136
137static struct irqaction cpm2_irqaction = {
138 .handler = cpm2_cascade,
139 .flags = IRQF_DISABLED,
140 .mask = CPU_MASK_NONE,
141 .name = "cpm2_cascade",
142};
143#endif /* CONFIG_CPM2 */
144
145void __init
146mpc85xx_cds_init_IRQ(void)
147{
148 bd_t *binfo = (bd_t *) __res;
149 int i;
150
151 /* Determine the Physical Address of the OpenPIC regs */
152 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
153 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
154 OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
155 OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
156
157 /* Skip reserved space and internal sources */
158#ifdef CONFIG_MPC8548
159 openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200);
160#else
161 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
162#endif
163 /* Map PIC IRQs 0-11 */
164 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
165
166 /* we let openpic interrupts starting from an offset, to
167 * leave space for cascading interrupts underneath.
168 */
169 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
170
171#ifdef CONFIG_PCI
172 openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
173
174 i8259_init(0, 0);
175#endif
176
177#ifdef CONFIG_CPM2
178 /* Setup CPM2 PIC */
179 cpm2_init_IRQ();
180
181 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
182#endif
183
184 return;
185}
186
187#ifdef CONFIG_PCI
188/*
189 * interrupt routing
190 */
191int
192mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
193{
194 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
195
196 if (!hose->index)
197 {
198 /* Handle PCI1 interrupts */
199 char pci_irq_table[][4] =
200 /*
201 * PCI IDSEL/INTPIN->INTLINE
202 * A B C D
203 */
204
205 /* Note IRQ assignment for slots is based on which slot the elysium is
206 * in -- in this setup elysium is in slot #2 (this PIRQA as first
207 * interrupt on slot */
208 {
209 { 0, 1, 2, 3 }, /* 16 - PMC */
210 { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
211 { 0, 1, 2, 3 }, /* 18 - Slot 1 */
212 { 1, 2, 3, 0 }, /* 19 - Slot 2 */
213 { 2, 3, 0, 1 }, /* 20 - Slot 3 */
214 { 3, 0, 1, 2 }, /* 21 - Slot 4 */
215 };
216
217 const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
218 int i, j;
219
220 for (i = 0; i < 6; i++)
221 for (j = 0; j < 4; j++)
222 pci_irq_table[i][j] =
223 ((pci_irq_table[i][j] + 5 -
224 cds_pci_slot) & 0x3) + PIRQ0A;
225
226 return PCI_IRQ_TABLE_LOOKUP;
227 } else {
228 /* Handle PCI2 interrupts (if we have one) */
229 char pci_irq_table[][4] =
230 {
231 /*
232 * We only have one slot and one interrupt
233 * going to PIRQA - PIRQD */
234 { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
235 };
236
237 const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
238
239 return PCI_IRQ_TABLE_LOOKUP;
240 }
241}
242
243#define ARCADIA_HOST_BRIDGE_IDSEL 17
244#define ARCADIA_2ND_BRIDGE_IDSEL 3
245
246extern int mpc85xx_pci1_last_busno;
247
248int
249mpc85xx_exclude_device(u_char bus, u_char devfn)
250{
251 if (bus == 0 && PCI_SLOT(devfn) == 0)
252 return PCIBIOS_DEVICE_NOT_FOUND;
253#ifdef CONFIG_85xx_PCI2
254 if (mpc85xx_pci1_last_busno)
255 if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
256 return PCIBIOS_DEVICE_NOT_FOUND;
257#endif
258 /* We explicitly do not go past the Tundra 320 Bridge */
259 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
260 return PCIBIOS_DEVICE_NOT_FOUND;
261 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
262 return PCIBIOS_DEVICE_NOT_FOUND;
263 else
264 return PCIBIOS_SUCCESSFUL;
265}
266
267void __init
268mpc85xx_cds_enable_via(struct pci_controller *hose)
269{
270 u32 pci_class;
271 u16 vid, did;
272
273 early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
274 if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
275 return;
276
277 /* Configure P2P so that we can reach bus 1 */
278 early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
279 early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
280 early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
281
282 early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
283 early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
284
285 if ((vid != PCI_VENDOR_ID_VIA) ||
286 (did != PCI_DEVICE_ID_VIA_82C686))
287 return;
288
289 /* Enable USB and IDE functions */
290 early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
291}
292
293void __init
294mpc85xx_cds_fixup_via(struct pci_controller *hose)
295{
296 u32 pci_class;
297 u16 vid, did;
298
299 early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
300 if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
301 return;
302
303 /*
304 * Force the backplane P2P bridge to have a window
305 * open from 0x00000000-0x00001fff in PCI I/O space.
306 * This allows legacy I/O (i8259, etc) on the VIA
307 * southbridge to be accessed.
308 */
309 early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
310 early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
311 early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
312 early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
313
314 early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
315 early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
316 if ((vid != PCI_VENDOR_ID_VIA) ||
317 (did != PCI_DEVICE_ID_VIA_82C686))
318 return;
319
320 /*
321 * Since the P2P window was forced to cover the fixed
322 * legacy I/O addresses, it is necessary to manually
323 * place the base addresses for the IDE and USB functions
324 * within this window.
325 */
326 /* Function 1, IDE */
327 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
328 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
329 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
330 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
331 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
332
333 /* Function 2, USB ports 0-1 */
334 early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
335
336 /* Function 3, USB ports 2-3 */
337 early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
338
339 /* Function 5, Power Management */
340 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
341 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
342 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
343
344 /* Function 6, AC97 Interface */
345 early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
346}
347
348void __init
349mpc85xx_cds_pcibios_fixup(void)
350{
351 struct pci_dev *dev;
352 u_char c;
353
354 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
355 PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
356 /*
357 * U-Boot does not set the enable bits
358 * for the IDE device. Force them on here.
359 */
360 pci_read_config_byte(dev, 0x40, &c);
361 c |= 0x03; /* IDE: Chip Enable Bits */
362 pci_write_config_byte(dev, 0x40, c);
363
364 /*
365 * Since only primary interface works, force the
366 * IDE function to standard primary IDE interrupt
367 * w/ 8259 offset
368 */
369 dev->irq = 14;
370 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
371 pci_dev_put(dev);
372 }
373
374 /*
375 * Force legacy USB interrupt routing
376 */
377 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
378 PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
379 dev->irq = 10;
380 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
381
382 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
383 PCI_DEVICE_ID_VIA_82C586_2, dev))) {
384 dev->irq = 11;
385 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
386 }
387 pci_dev_put(dev);
388 }
389}
390#endif /* CONFIG_PCI */
391
392TODC_ALLOC();
393
394/* ************************************************************************
395 *
396 * Setup the architecture
397 *
398 */
399static void __init
400mpc85xx_cds_setup_arch(void)
401{
402 bd_t *binfo = (bd_t *) __res;
403 unsigned int freq;
404 struct gianfar_platform_data *pdata;
405 struct gianfar_mdio_data *mdata;
406
407 /* get the core frequency */
408 freq = binfo->bi_intfreq;
409
410 printk("mpc85xx_cds_setup_arch\n");
411
412#ifdef CONFIG_CPM2
413 cpm2_reset();
414#endif
415
416 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
417 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
418 printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
419
420 /* Setup TODC access */
421 TODC_INIT(TODC_TYPE_DS1743,
422 0,
423 0,
424 ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
425 8);
426
427 /* Set loops_per_jiffy to a half-way reasonable value,
428 for use until calibrate_delay gets called. */
429 loops_per_jiffy = freq / HZ;
430
431#ifdef CONFIG_PCI
432 /* VIA IDE configuration */
433 ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
434
435 /* setup PCI host bridges */
436 mpc85xx_setup_hose();
437#endif
438
439#ifdef CONFIG_SERIAL_8250
440 mpc85xx_early_serial_map();
441#endif
442
443#ifdef CONFIG_SERIAL_TEXT_DEBUG
444 /* Invalidate the entry we stole earlier the serial ports
445 * should be properly mapped */
446 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
447#endif
448
449 /* setup the board related info for the MDIO bus */
450 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
451
452 mdata->irq[0] = MPC85xx_IRQ_EXT5;
453 mdata->irq[1] = MPC85xx_IRQ_EXT5;
454 mdata->irq[2] = PHY_POLL;
455 mdata->irq[3] = PHY_POLL;
456 mdata->irq[31] = PHY_POLL;
457
458 /* setup the board related information for the enet controllers */
459 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
460 if (pdata) {
461 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
462 pdata->bus_id = 0;
463 pdata->phy_id = 0;
464 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
465 }
466
467 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
468 if (pdata) {
469 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
470 pdata->bus_id = 0;
471 pdata->phy_id = 1;
472 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
473 }
474
475 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);
476 if (pdata) {
477 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
478 pdata->bus_id = 0;
479 pdata->phy_id = 0;
480 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
481 }
482
483 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);
484 if (pdata) {
485 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
486 pdata->bus_id = 0;
487 pdata->phy_id = 1;
488 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
489 }
490
491 ppc_sys_device_remove(MPC85xx_eTSEC3);
492 ppc_sys_device_remove(MPC85xx_eTSEC4);
493
494#ifdef CONFIG_BLK_DEV_INITRD
495 if (initrd_start)
496 ROOT_DEV = Root_RAM0;
497 else
498#endif
499#ifdef CONFIG_ROOT_NFS
500 ROOT_DEV = Root_NFS;
501#else
502 ROOT_DEV = Root_HDA1;
503#endif
504}
505
506/* ************************************************************************ */
507void __init
508platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
509 unsigned long r6, unsigned long r7)
510{
511 /* parse_bootinfo must always be called first */
512 parse_bootinfo(find_bootinfo());
513
514 /*
515 * If we were passed in a board information, copy it into the
516 * residual data area.
517 */
518 if (r3) {
519 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
520 sizeof (bd_t));
521
522 }
523#ifdef CONFIG_SERIAL_TEXT_DEBUG
524 {
525 bd_t *binfo = (bd_t *) __res;
526 struct uart_port p;
527
528 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
529 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
530 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
531
532 memset(&p, 0, sizeof (p));
533 p.iotype = UPIO_MEM;
534 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
535 p.uartclk = binfo->bi_busfreq;
536
537 gen550_init(0, &p);
538
539 memset(&p, 0, sizeof (p));
540 p.iotype = UPIO_MEM;
541 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
542 p.uartclk = binfo->bi_busfreq;
543
544 gen550_init(1, &p);
545 }
546#endif
547
548#if defined(CONFIG_BLK_DEV_INITRD)
549 /*
550 * If the init RAM disk has been configured in, and there's a valid
551 * starting address for it, set it up.
552 */
553 if (r4) {
554 initrd_start = r4 + KERNELBASE;
555 initrd_end = r5 + KERNELBASE;
556 }
557#endif /* CONFIG_BLK_DEV_INITRD */
558
559 /* Copy the kernel command line arguments to a safe place. */
560
561 if (r6) {
562 *(char *) (r7 + KERNELBASE) = 0;
563 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
564 }
565
566 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
567
568 /* setup the PowerPC module struct */
569 ppc_md.setup_arch = mpc85xx_cds_setup_arch;
570 ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
571
572 ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
573 ppc_md.get_irq = openpic_get_irq;
574
575 ppc_md.restart = mpc85xx_restart;
576 ppc_md.power_off = mpc85xx_power_off;
577 ppc_md.halt = mpc85xx_halt;
578
579 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
580
581 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
582
583 ppc_md.time_init = todc_time_init;
584 ppc_md.set_rtc_time = todc_set_rtc_time;
585 ppc_md.get_rtc_time = todc_get_rtc_time;
586
587 ppc_md.nvram_read_val = todc_direct_read_val;
588 ppc_md.nvram_write_val = todc_direct_write_val;
589
590#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
591 ppc_md.progress = gen550_progress;
592#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
593#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
594 ppc_md.early_serial_map = mpc85xx_early_serial_map;
595#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
596
597 if (ppc_md.progress)
598 ppc_md.progress("mpc85xx_cds_init(): exit", 0);
599
600 return;
601}
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
deleted file mode 100644
index 32c5455c8b82..000000000000
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * MPC85xx CDS board definitions
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2004 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MACH_MPC85XX_CDS_H__
16#define __MACH_MPC85XX_CDS_H__
17
18#include <linux/serial.h>
19#include <asm/ppcboot.h>
20#include <linux/initrd.h>
21#include <syslib/ppc85xx_setup.h>
22
23#define BOARD_CCSRBAR ((uint)0xe0000000)
24#define CCSRBAR_SIZE ((uint)1024*1024)
25
26/* CADMUS info */
27#define CADMUS_BASE (0xf8004000)
28#define CADMUS_SIZE (256)
29#define CM_VER (0)
30#define CM_CSR (1)
31#define CM_RST (2)
32
33/* CDS NVRAM/RTC */
34#define CDS_RTC_ADDR (0xf8000000)
35#define CDS_RTC_SIZE (8 * 1024)
36
37/* PCI config */
38#define PCI1_CFG_ADDR_OFFSET (0x8000)
39#define PCI1_CFG_DATA_OFFSET (0x8004)
40
41#define PCI2_CFG_ADDR_OFFSET (0x9000)
42#define PCI2_CFG_DATA_OFFSET (0x9004)
43
44/* PCI interrupt controller */
45#define PIRQ0A MPC85xx_IRQ_EXT0
46#define PIRQ0B MPC85xx_IRQ_EXT1
47#define PIRQ0C MPC85xx_IRQ_EXT2
48#define PIRQ0D MPC85xx_IRQ_EXT3
49#define PIRQ1A MPC85xx_IRQ_EXT11
50
51/* PCI 1 memory map */
52#define MPC85XX_PCI1_LOWER_IO 0x00000000
53#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
54
55#define MPC85XX_PCI1_LOWER_MEM 0x80000000
56#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
57
58#define MPC85XX_PCI1_IO_BASE 0xe2000000
59#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
60
61#define MPC85XX_PCI1_IO_SIZE 0x01000000
62
63/* PCI 2 memory map */
64/* Note: the standard PPC fixups will cause IO space to get bumped by
65 * hose->io_base_virt - isa_io_base => MPC85XX_PCI1_IO_SIZE */
66#define MPC85XX_PCI2_LOWER_IO 0x00000000
67#define MPC85XX_PCI2_UPPER_IO 0x00ffffff
68
69#define MPC85XX_PCI2_LOWER_MEM 0xa0000000
70#define MPC85XX_PCI2_UPPER_MEM 0xbfffffff
71
72#define MPC85XX_PCI2_IO_BASE 0xe3000000
73#define MPC85XX_PCI2_MEM_OFFSET 0x00000000
74
75#define MPC85XX_PCI2_IO_SIZE 0x01000000
76
77#define NR_8259_INTS 16
78#define CPM_IRQ_OFFSET NR_8259_INTS
79
80#endif /* __MACH_MPC85XX_CDS_H__ */
diff --git a/arch/ppc/platforms/85xx/sbc8560.c b/arch/ppc/platforms/85xx/sbc8560.c
deleted file mode 100644
index 3d7addbdecfd..000000000000
--- a/arch/ppc/platforms/85xx/sbc8560.c
+++ /dev/null
@@ -1,234 +0,0 @@
1/*
2 * Wind River SBC8560 board specific routines
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright 2004 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/stddef.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/reboot.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/major.h>
22#include <linux/console.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/root_dev.h>
26#include <linux/serial.h>
27#include <linux/tty.h> /* for linux/serial_core.h */
28#include <linux/serial_core.h>
29#include <linux/serial_8250.h>
30#include <linux/initrd.h>
31#include <linux/module.h>
32#include <linux/fsl_devices.h>
33
34#include <asm/system.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/atomic.h>
38#include <asm/time.h>
39#include <asm/io.h>
40#include <asm/machdep.h>
41#include <asm/open_pic.h>
42#include <asm/bootinfo.h>
43#include <asm/pci-bridge.h>
44#include <asm/mpc85xx.h>
45#include <asm/irq.h>
46#include <asm/immap_85xx.h>
47#include <asm/kgdb.h>
48#include <asm/ppc_sys.h>
49#include <mm/mmu_decl.h>
50
51#include <syslib/ppc85xx_common.h>
52#include <syslib/ppc85xx_setup.h>
53
54#ifdef CONFIG_SERIAL_8250
55static void __init
56sbc8560_early_serial_map(void)
57{
58 struct uart_port uart_req;
59
60 /* Setup serial port access */
61 memset(&uart_req, 0, sizeof (uart_req));
62 uart_req.irq = MPC85xx_IRQ_EXT9;
63 uart_req.flags = STD_COM_FLAGS;
64 uart_req.uartclk = BASE_BAUD * 16;
65 uart_req.iotype = UPIO_MEM;
66 uart_req.mapbase = UARTA_ADDR;
67 uart_req.membase = ioremap(uart_req.mapbase, MPC85xx_UART0_SIZE);
68 uart_req.type = PORT_16650;
69
70#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
71 gen550_init(0, &uart_req);
72#endif
73
74 if (early_serial_setup(&uart_req) != 0)
75 printk("Early serial init of port 0 failed\n");
76
77 /* Assume early_serial_setup() doesn't modify uart_req */
78 uart_req.line = 1;
79 uart_req.mapbase = UARTB_ADDR;
80 uart_req.membase = ioremap(uart_req.mapbase, MPC85xx_UART1_SIZE);
81 uart_req.irq = MPC85xx_IRQ_EXT10;
82
83#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
84 gen550_init(1, &uart_req);
85#endif
86
87 if (early_serial_setup(&uart_req) != 0)
88 printk("Early serial init of port 1 failed\n");
89}
90#endif
91
92/* ************************************************************************
93 *
94 * Setup the architecture
95 *
96 */
97static void __init
98sbc8560_setup_arch(void)
99{
100 bd_t *binfo = (bd_t *) __res;
101 unsigned int freq;
102 struct gianfar_platform_data *pdata;
103 struct gianfar_mdio_data *mdata;
104
105 /* get the core frequency */
106 freq = binfo->bi_intfreq;
107
108 if (ppc_md.progress)
109 ppc_md.progress("sbc8560_setup_arch()", 0);
110
111 /* Set loops_per_jiffy to a half-way reasonable value,
112 for use until calibrate_delay gets called. */
113 loops_per_jiffy = freq / HZ;
114
115#ifdef CONFIG_PCI
116 /* setup PCI host bridges */
117 mpc85xx_setup_hose();
118#endif
119#ifdef CONFIG_SERIAL_8250
120 sbc8560_early_serial_map();
121#endif
122#ifdef CONFIG_SERIAL_TEXT_DEBUG
123 /* Invalidate the entry we stole earlier the serial ports
124 * should be properly mapped */
125 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
126#endif
127
128 /* setup the board related info for the MDIO bus */
129 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
130
131 mdata->irq[25] = MPC85xx_IRQ_EXT6;
132 mdata->irq[26] = MPC85xx_IRQ_EXT7;
133 mdata->irq[31] = PHY_POLL;
134
135 /* setup the board related information for the enet controllers */
136 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
137 if (pdata) {
138 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
139 pdata->bus_id = 0;
140 pdata->phy_id = 25;
141 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
142 }
143
144 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
145 if (pdata) {
146 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
147 pdata->bus_id = 0;
148 pdata->phy_id = 26;
149 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
150 }
151
152#ifdef CONFIG_BLK_DEV_INITRD
153 if (initrd_start)
154 ROOT_DEV = Root_RAM0;
155 else
156#endif
157#ifdef CONFIG_ROOT_NFS
158 ROOT_DEV = Root_NFS;
159#else
160 ROOT_DEV = Root_HDA1;
161#endif
162}
163
164/* ************************************************************************ */
165void __init
166platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
167 unsigned long r6, unsigned long r7)
168{
169 /* parse_bootinfo must always be called first */
170 parse_bootinfo(find_bootinfo());
171
172 /*
173 * If we were passed in a board information, copy it into the
174 * residual data area.
175 */
176 if (r3) {
177 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
178 sizeof (bd_t));
179 }
180
181#ifdef CONFIG_SERIAL_TEXT_DEBUG
182 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
183 settlbcam(num_tlbcam_entries - 1, UARTA_ADDR,
184 UARTA_ADDR, 0x1000, _PAGE_IO, 0);
185#endif
186
187#if defined(CONFIG_BLK_DEV_INITRD)
188 /*
189 * If the init RAM disk has been configured in, and there's a valid
190 * starting address for it, set it up.
191 */
192 if (r4) {
193 initrd_start = r4 + KERNELBASE;
194 initrd_end = r5 + KERNELBASE;
195 }
196#endif /* CONFIG_BLK_DEV_INITRD */
197
198 /* Copy the kernel command line arguments to a safe place. */
199
200 if (r6) {
201 *(char *) (r7 + KERNELBASE) = 0;
202 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
203 }
204
205 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
206
207 /* setup the PowerPC module struct */
208 ppc_md.setup_arch = sbc8560_setup_arch;
209 ppc_md.show_cpuinfo = sbc8560_show_cpuinfo;
210
211 ppc_md.init_IRQ = sbc8560_init_IRQ;
212 ppc_md.get_irq = openpic_get_irq;
213
214 ppc_md.restart = mpc85xx_restart;
215 ppc_md.power_off = mpc85xx_power_off;
216 ppc_md.halt = mpc85xx_halt;
217
218 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
219
220 ppc_md.time_init = NULL;
221 ppc_md.set_rtc_time = NULL;
222 ppc_md.get_rtc_time = NULL;
223 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
224
225#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
226 ppc_md.progress = gen550_progress;
227#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
228#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
229 ppc_md.early_serial_map = sbc8560_early_serial_map;
230#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
231
232 if (ppc_md.progress)
233 ppc_md.progress("sbc8560_init(): exit", 0);
234}
diff --git a/arch/ppc/platforms/85xx/sbc8560.h b/arch/ppc/platforms/85xx/sbc8560.h
deleted file mode 100644
index e5e156f60100..000000000000
--- a/arch/ppc/platforms/85xx/sbc8560.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * Wind River SBC8560 board definitions
3 *
4 * Copyright 2003 Motorola Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifndef __MACH_SBC8560_H__
14#define __MACH_SBC8560_H__
15
16#include <platforms/85xx/sbc85xx.h>
17#include <asm/irq.h>
18
19#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
20
21#ifdef CONFIG_SERIAL_MANY_PORTS
22#define RS_TABLE_SIZE 64
23#else
24#define RS_TABLE_SIZE 2
25#endif
26
27/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
28#define BASE_BAUD ( 1843200 / 16 )
29
30#ifdef CONFIG_SERIAL_DETECT_IRQ
31#define STD_COM_FLAGS (ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
32#else
33#define STD_COM_FLAGS (ASYNC_SKIP_TEST)
34#endif
35
36#define STD_SERIAL_PORT_DFNS \
37 { 0, BASE_BAUD, UARTA_ADDR, MPC85xx_IRQ_EXT9, STD_COM_FLAGS, /* ttyS0 */ \
38 iomem_base: (u8 *)UARTA_ADDR, \
39 io_type: SERIAL_IO_MEM }, \
40 { 0, BASE_BAUD, UARTB_ADDR, MPC85xx_IRQ_EXT10, STD_COM_FLAGS, /* ttyS1 */ \
41 iomem_base: (u8 *)UARTB_ADDR, \
42 io_type: SERIAL_IO_MEM },
43
44#define SERIAL_PORT_DFNS \
45 STD_SERIAL_PORT_DFNS
46
47#endif /* __MACH_SBC8560_H__ */
diff --git a/arch/ppc/platforms/85xx/sbc85xx.c b/arch/ppc/platforms/85xx/sbc85xx.c
deleted file mode 100644
index 2c587ca97bce..000000000000
--- a/arch/ppc/platforms/85xx/sbc85xx.c
+++ /dev/null
@@ -1,166 +0,0 @@
1/*
2 * WindRiver PowerQUICC III SBC85xx board common routines
3 *
4 * Copyright 2002, 2003 Motorola Inc.
5 * Copyright 2004 Red Hat, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/stddef.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/errno.h>
17#include <linux/reboot.h>
18#include <linux/pci.h>
19#include <linux/kdev_t.h>
20#include <linux/major.h>
21#include <linux/console.h>
22#include <linux/delay.h>
23#include <linux/seq_file.h>
24#include <linux/serial.h>
25#include <linux/module.h>
26
27#include <asm/system.h>
28#include <asm/pgtable.h>
29#include <asm/page.h>
30#include <asm/atomic.h>
31#include <asm/time.h>
32#include <asm/io.h>
33#include <asm/machdep.h>
34#include <asm/open_pic.h>
35#include <asm/bootinfo.h>
36#include <asm/pci-bridge.h>
37#include <asm/mpc85xx.h>
38#include <asm/irq.h>
39#include <asm/immap_85xx.h>
40#include <asm/ppc_sys.h>
41
42#include <mm/mmu_decl.h>
43
44#include <platforms/85xx/sbc85xx.h>
45
46unsigned char __res[sizeof (bd_t)];
47
48#ifndef CONFIG_PCI
49unsigned long isa_io_base = 0;
50unsigned long isa_mem_base = 0;
51unsigned long pci_dram_offset = 0;
52#endif
53
54extern unsigned long total_memory; /* in mm/init */
55
56/* Internal interrupts are all Level Sensitive, and Positive Polarity */
57static u_char sbc8560_openpic_initsenses[] __initdata = {
58 MPC85XX_INTERNAL_IRQ_SENSES,
59 0x0, /* External 0: */
60 0x0, /* External 1: */
61#if defined(CONFIG_PCI)
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 0 */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 1 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 2 */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PCI slot 3 */
66#else
67 0x0, /* External 2: */
68 0x0, /* External 3: */
69 0x0, /* External 4: */
70 0x0, /* External 5: */
71#endif
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 6: PHY */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
74 0x0, /* External 8: */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: PHY */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 10: PHY */
77 0x0, /* External 11: */
78};
79
80/* ************************************************************************ */
81int
82sbc8560_show_cpuinfo(struct seq_file *m)
83{
84 uint pvid, svid, phid1;
85 uint memsize = total_memory;
86 bd_t *binfo = (bd_t *) __res;
87 unsigned int freq;
88
89 /* get the core frequency */
90 freq = binfo->bi_intfreq;
91
92 pvid = mfspr(SPRN_PVR);
93 svid = mfspr(SPRN_SVR);
94
95 seq_printf(m, "Vendor\t\t: Wind River\n");
96 seq_printf(m, "Machine\t\t: SBC%s\n", cur_ppc_sys_spec->ppc_sys_name);
97 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
98 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
99 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
100
101 /* Display cpu Pll setting */
102 phid1 = mfspr(SPRN_HID1);
103 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
104
105 /* Display the amount of memory */
106 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
107
108 return 0;
109}
110
111void __init
112sbc8560_init_IRQ(void)
113{
114 bd_t *binfo = (bd_t *) __res;
115 /* Determine the Physical Address of the OpenPIC regs */
116 phys_addr_t OpenPIC_PAddr =
117 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
118 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
119 OpenPIC_InitSenses = sbc8560_openpic_initsenses;
120 OpenPIC_NumInitSenses = sizeof (sbc8560_openpic_initsenses);
121
122 /* Skip reserved space and internal sources */
123 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
124 /* Map PIC IRQs 0-11 */
125 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
126
127 /* we let openpic interrupts starting from an offset, to
128 * leave space for cascading interrupts underneath.
129 */
130 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
131
132 return;
133}
134
135/*
136 * interrupt routing
137 */
138
139#ifdef CONFIG_PCI
140int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
141 unsigned char pin)
142{
143 static char pci_irq_table[][4] =
144 /*
145 * PCI IDSEL/INTPIN->INTLINE
146 * A B C D
147 */
148 {
149 {PIRQA, PIRQB, PIRQC, PIRQD},
150 {PIRQD, PIRQA, PIRQB, PIRQC},
151 {PIRQC, PIRQD, PIRQA, PIRQB},
152 {PIRQB, PIRQC, PIRQD, PIRQA},
153 };
154
155 const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
156 return PCI_IRQ_TABLE_LOOKUP;
157}
158
159int mpc85xx_exclude_device(u_char bus, u_char devfn)
160{
161 if (bus == 0 && PCI_SLOT(devfn) == 0)
162 return PCIBIOS_DEVICE_NOT_FOUND;
163 else
164 return PCIBIOS_SUCCESSFUL;
165}
166#endif /* CONFIG_PCI */
diff --git a/arch/ppc/platforms/85xx/sbc85xx.h b/arch/ppc/platforms/85xx/sbc85xx.h
deleted file mode 100644
index 51df4dc04e22..000000000000
--- a/arch/ppc/platforms/85xx/sbc85xx.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * WindRiver PowerQUICC III SBC85xx common board definitions
3 *
4 * Copyright 2003 Motorola Inc.
5 * Copyright 2004 Red Hat, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#ifndef __PLATFORMS_85XX_SBC85XX_H__
15#define __PLATFORMS_85XX_SBC85XX_H__
16
17#include <linux/init.h>
18#include <linux/seq_file.h>
19#include <asm/ppcboot.h>
20
21#define BOARD_CCSRBAR ((uint)0xff700000)
22#define CCSRBAR_SIZE ((uint)1024*1024)
23
24#define BCSR_ADDR ((uint)0xfc000000)
25#define BCSR_SIZE ((uint)(16 * 1024 * 1024))
26
27#define UARTA_ADDR (BCSR_ADDR + 0x00700000)
28#define UARTB_ADDR (BCSR_ADDR + 0x00800000)
29#define RTC_DEVICE_ADDR (BCSR_ADDR + 0x00900000)
30#define EEPROM_ADDR (BCSR_ADDR + 0x00b00000)
31
32extern int sbc8560_show_cpuinfo(struct seq_file *m);
33extern void sbc8560_init_IRQ(void) __init;
34
35/* PCI interrupt controller */
36#define PIRQA MPC85xx_IRQ_EXT1
37#define PIRQB MPC85xx_IRQ_EXT2
38#define PIRQC MPC85xx_IRQ_EXT3
39#define PIRQD MPC85xx_IRQ_EXT4
40
41#define MPC85XX_PCI1_LOWER_IO 0x00000000
42#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
43
44#define MPC85XX_PCI1_LOWER_MEM 0x80000000
45#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
46
47#define MPC85XX_PCI1_IO_BASE 0xe2000000
48#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
49
50#define MPC85XX_PCI1_IO_SIZE 0x01000000
51
52/* FCC1 Clock Source Configuration. These can be
53 * redefined in the board specific file.
54 * Can only choose from CLK9-12 */
55#define F1_RXCLK 12
56#define F1_TXCLK 11
57
58/* FCC2 Clock Source Configuration. These can be
59 * redefined in the board specific file.
60 * Can only choose from CLK13-16 */
61#define F2_RXCLK 13
62#define F2_TXCLK 14
63
64/* FCC3 Clock Source Configuration. These can be
65 * redefined in the board specific file.
66 * Can only choose from CLK13-16 */
67#define F3_RXCLK 15
68#define F3_TXCLK 16
69
70#endif /* __PLATFORMS_85XX_SBC85XX_H__ */
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
deleted file mode 100644
index 8748da3b3e0e..000000000000
--- a/arch/ppc/platforms/85xx/stx_gp3.c
+++ /dev/null
@@ -1,339 +0,0 @@
1/*
2 * STx GP3 board specific routines
3 *
4 * Dan Malek <dan@embeddededge.com>
5 * Copyright 2004 Embedded Edge, LLC
6 *
7 * Copied from mpc8560_ads.c
8 * Copyright 2002, 2003 Motorola Inc.
9 *
10 * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
11 * Copyright 2004-2005 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/stddef.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/reboot.h>
24#include <linux/pci.h>
25#include <linux/kdev_t.h>
26#include <linux/major.h>
27#include <linux/blkdev.h>
28#include <linux/console.h>
29#include <linux/delay.h>
30#include <linux/root_dev.h>
31#include <linux/seq_file.h>
32#include <linux/serial.h>
33#include <linux/initrd.h>
34#include <linux/module.h>
35#include <linux/fsl_devices.h>
36#include <linux/interrupt.h>
37#include <linux/rio.h>
38
39#include <asm/system.h>
40#include <asm/pgtable.h>
41#include <asm/page.h>
42#include <asm/atomic.h>
43#include <asm/time.h>
44#include <asm/io.h>
45#include <asm/machdep.h>
46#include <asm/open_pic.h>
47#include <asm/bootinfo.h>
48#include <asm/pci-bridge.h>
49#include <asm/mpc85xx.h>
50#include <asm/irq.h>
51#include <asm/immap_85xx.h>
52#include <asm/cpm2.h>
53#include <asm/ppc_sys.h>
54
55#include <syslib/cpm2_pic.h>
56#include <syslib/ppc85xx_common.h>
57
58
59unsigned char __res[sizeof(bd_t)];
60
61#ifndef CONFIG_PCI
62unsigned long isa_io_base = 0;
63unsigned long isa_mem_base = 0;
64unsigned long pci_dram_offset = 0;
65#endif
66
67/* Internal interrupts are all Level Sensitive, and Positive Polarity */
68static u8 gp3_openpic_initsenses[] __initdata = {
69 MPC85XX_INTERNAL_IRQ_SENSES,
70 0x0, /* External 0: */
71#if defined(CONFIG_PCI)
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 1 */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 2 */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 3 */
76#else
77 0x0, /* External 1: */
78 0x0, /* External 2: */
79 0x0, /* External 3: */
80 0x0, /* External 4: */
81#endif
82 0x0, /* External 5: */
83 0x0, /* External 6: */
84 0x0, /* External 7: */
85 0x0, /* External 8: */
86 0x0, /* External 9: */
87 0x0, /* External 10: */
88 0x0, /* External 11: */
89};
90
91/*
92 * Setup the architecture
93 */
94static void __init
95gp3_setup_arch(void)
96{
97 bd_t *binfo = (bd_t *) __res;
98 unsigned int freq;
99 struct gianfar_platform_data *pdata;
100 struct gianfar_mdio_data *mdata;
101
102 cpm2_reset();
103
104 /* get the core frequency */
105 freq = binfo->bi_intfreq;
106
107 if (ppc_md.progress)
108 ppc_md.progress("gp3_setup_arch()", 0);
109
110 /* Set loops_per_jiffy to a half-way reasonable value,
111 for use until calibrate_delay gets called. */
112 loops_per_jiffy = freq / HZ;
113
114#ifdef CONFIG_PCI
115 /* setup PCI host bridges */
116 mpc85xx_setup_hose();
117#endif
118
119 /* setup the board related info for the MDIO bus */
120 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
121
122 mdata->irq[2] = MPC85xx_IRQ_EXT5;
123 mdata->irq[4] = MPC85xx_IRQ_EXT5;
124 mdata->irq[31] = PHY_POLL;
125
126 /* setup the board related information for the enet controllers */
127 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
128 if (pdata) {
129 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
130 pdata->bus_id = 0;
131 pdata->phy_id = 2;
132 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
133 }
134
135 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
136 if (pdata) {
137 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
138 pdata->bus_id = 0;
139 pdata->phy_id = 4;
140 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
141 }
142
143#ifdef CONFIG_BLK_DEV_INITRD
144 if (initrd_start)
145 ROOT_DEV = Root_RAM0;
146 else
147#endif
148#ifdef CONFIG_ROOT_NFS
149 ROOT_DEV = Root_NFS;
150#else
151 ROOT_DEV = Root_HDA1;
152#endif
153
154 printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);
155}
156
157static irqreturn_t cpm2_cascade(int irq, void *dev_id)
158{
159 while ((irq = cpm2_get_irq()) >= 0)
160 __do_IRQ(irq);
161
162 return IRQ_HANDLED;
163}
164
165static struct irqaction cpm2_irqaction = {
166 .handler = cpm2_cascade,
167 .flags = IRQF_DISABLED,
168 .mask = CPU_MASK_NONE,
169 .name = "cpm2_cascade",
170};
171
172static void __init
173gp3_init_IRQ(void)
174{
175 bd_t *binfo = (bd_t *) __res;
176
177 /*
178 * Setup OpenPIC
179 */
180
181 /* Determine the Physical Address of the OpenPIC regs */
182 phys_addr_t OpenPIC_PAddr =
183 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
184 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
185 OpenPIC_InitSenses = gp3_openpic_initsenses;
186 OpenPIC_NumInitSenses = sizeof (gp3_openpic_initsenses);
187
188 /* Skip reserved space and internal sources */
189 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
190
191 /* Map PIC IRQs 0-11 */
192 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
193
194 /*
195 * Let openpic interrupts starting from an offset, to
196 * leave space for cascading interrupts underneath.
197 */
198 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
199
200 /* Setup CPM2 PIC */
201 cpm2_init_IRQ();
202
203 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
204
205 return;
206}
207
208static int
209gp3_show_cpuinfo(struct seq_file *m)
210{
211 uint pvid, svid, phid1;
212 bd_t *binfo = (bd_t *) __res;
213 uint memsize;
214 unsigned int freq;
215 extern unsigned long total_memory; /* in mm/init */
216
217 /* get the core frequency */
218 freq = binfo->bi_intfreq;
219
220 pvid = mfspr(SPRN_PVR);
221 svid = mfspr(SPRN_SVR);
222
223 memsize = total_memory;
224
225 seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
226 seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
227 seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
228 freq % 1000000);
229 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
230 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
231
232 /* Display cpu Pll setting */
233 phid1 = mfspr(SPRN_HID1);
234 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
235
236 /* Display the amount of memory */
237 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
238
239 return 0;
240}
241
242#ifdef CONFIG_PCI
243int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
244 unsigned char pin)
245{
246 static char pci_irq_table[][4] =
247 /*
248 * PCI IDSEL/INTPIN->INTLINE
249 * A B C D
250 */
251 {
252 {PIRQA, PIRQB, PIRQC, PIRQD},
253 {PIRQD, PIRQA, PIRQB, PIRQC},
254 {PIRQC, PIRQD, PIRQA, PIRQB},
255 {PIRQB, PIRQC, PIRQD, PIRQA},
256 };
257
258 const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
259 return PCI_IRQ_TABLE_LOOKUP;
260}
261
262int mpc85xx_exclude_device(u_char bus, u_char devfn)
263{
264 if (bus == 0 && PCI_SLOT(devfn) == 0)
265 return PCIBIOS_DEVICE_NOT_FOUND;
266 else
267 return PCIBIOS_SUCCESSFUL;
268}
269#endif /* CONFIG_PCI */
270
271#ifdef CONFIG_RAPIDIO
272extern void mpc85xx_rio_setup(int law_start, int law_size);
273void
274platform_rio_init(void)
275{
276 /*
277 * The STx firmware configures the RapidIO Local Access Window
278 * at 0xc0000000 with a size of 512MB.
279 */
280 mpc85xx_rio_setup(0xc0000000, 0x20000000);
281}
282#endif /* CONFIG_RAPIDIO */
283
284void __init
285platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
286 unsigned long r6, unsigned long r7)
287{
288 /* parse_bootinfo must always be called first */
289 parse_bootinfo(find_bootinfo());
290
291 /*
292 * If we were passed in a board information, copy it into the
293 * residual data area.
294 */
295 if (r3) {
296 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
297 sizeof (bd_t));
298
299 }
300#if defined(CONFIG_BLK_DEV_INITRD)
301 /*
302 * If the init RAM disk has been configured in, and there's a valid
303 * starting address for it, set it up.
304 */
305 if (r4) {
306 initrd_start = r4 + KERNELBASE;
307 initrd_end = r5 + KERNELBASE;
308 }
309#endif /* CONFIG_BLK_DEV_INITRD */
310
311 /* Copy the kernel command line arguments to a safe place. */
312
313 if (r6) {
314 *(char *) (r7 + KERNELBASE) = 0;
315 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
316 }
317
318 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
319
320 /* setup the PowerPC module struct */
321 ppc_md.setup_arch = gp3_setup_arch;
322 ppc_md.show_cpuinfo = gp3_show_cpuinfo;
323
324 ppc_md.init_IRQ = gp3_init_IRQ;
325 ppc_md.get_irq = openpic_get_irq;
326
327 ppc_md.restart = mpc85xx_restart;
328 ppc_md.power_off = mpc85xx_power_off;
329 ppc_md.halt = mpc85xx_halt;
330
331 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
332
333 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
334
335 if (ppc_md.progress)
336 ppc_md.progress("platform_init(): exit", 0);
337
338 return;
339}
diff --git a/arch/ppc/platforms/85xx/stx_gp3.h b/arch/ppc/platforms/85xx/stx_gp3.h
deleted file mode 100644
index c6e34c09e979..000000000000
--- a/arch/ppc/platforms/85xx/stx_gp3.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * STx GP3 board definitions
3 *
4 * Dan Malek (dan@embeddededge.com)
5 * Copyright 2004 Embedded Edge, LLC
6 *
7 * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2004-2005 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifndef __MACH_STX_GP3_H
18#define __MACH_STX_GP3_H
19
20#include <linux/init.h>
21#include <asm/ppcboot.h>
22
23#define BOARD_CCSRBAR ((uint)0xe0000000)
24#define CCSRBAR_SIZE ((uint)1024*1024)
25
26#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
27
28#define BCSR_ADDR ((uint)0xfc000000)
29#define BCSR_SIZE ((uint)(16 * 1024))
30
31#define BCSR_TSEC1_RESET 0x00000080
32#define BCSR_TSEC2_RESET 0x00000040
33#define BCSR_LED1 0x00000008
34#define BCSR_LED2 0x00000004
35#define BCSR_LED3 0x00000002
36#define BCSR_LED4 0x00000001
37
38extern void mpc85xx_setup_hose(void) __init;
39extern void mpc85xx_restart(char *cmd);
40extern void mpc85xx_power_off(void);
41extern void mpc85xx_halt(void);
42extern void mpc85xx_init_IRQ(void) __init;
43extern unsigned long mpc85xx_find_end_of_memory(void) __init;
44extern void mpc85xx_calibrate_decr(void) __init;
45
46#define PCI_CFG_ADDR_OFFSET (0x8000)
47#define PCI_CFG_DATA_OFFSET (0x8004)
48
49/* PCI interrupt controller */
50#define PIRQA MPC85xx_IRQ_EXT1
51#define PIRQB MPC85xx_IRQ_EXT2
52#define PIRQC MPC85xx_IRQ_EXT3
53#define PIRQD MPC85xx_IRQ_EXT4
54#define PCI_MIN_IDSEL 16
55#define PCI_MAX_IDSEL 19
56#define PCI_IRQ_SLOT 4
57
58#define MPC85XX_PCI1_LOWER_IO 0x00000000
59#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
60
61#define MPC85XX_PCI1_LOWER_MEM 0x80000000
62#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
63
64#define MPC85XX_PCI1_IO_BASE 0xe2000000
65#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
66
67#define MPC85XX_PCI1_IO_SIZE 0x01000000
68
69#endif /* __MACH_STX_GP3_H */
diff --git a/arch/ppc/platforms/85xx/tqm85xx.c b/arch/ppc/platforms/85xx/tqm85xx.c
deleted file mode 100644
index 2a863a83d4c8..000000000000
--- a/arch/ppc/platforms/85xx/tqm85xx.c
+++ /dev/null
@@ -1,412 +0,0 @@
1/*
2 * TQM85xx (40/41/55/60) board specific routines
3 *
4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
6 *
7 * Based on original work by
8 * Kumar Gala <galak@kernel.crashing.org>
9 * Copyright 2004 Freescale Semiconductor Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/major.h>
25#include <linux/console.h>
26#include <linux/delay.h>
27#include <linux/seq_file.h>
28#include <linux/root_dev.h>
29#include <linux/serial.h>
30#include <linux/tty.h> /* for linux/serial_core.h */
31#include <linux/serial_core.h>
32#include <linux/initrd.h>
33#include <linux/module.h>
34#include <linux/fsl_devices.h>
35
36#include <asm/system.h>
37#include <asm/pgtable.h>
38#include <asm/page.h>
39#include <asm/atomic.h>
40#include <asm/time.h>
41#include <asm/io.h>
42#include <asm/machdep.h>
43#include <asm/open_pic.h>
44#include <asm/bootinfo.h>
45#include <asm/pci-bridge.h>
46#include <asm/mpc85xx.h>
47#include <asm/irq.h>
48#include <asm/immap_85xx.h>
49#include <asm/kgdb.h>
50#include <asm/ppc_sys.h>
51#include <asm/cpm2.h>
52#include <mm/mmu_decl.h>
53
54#include <syslib/ppc85xx_setup.h>
55#include <syslib/cpm2_pic.h>
56#include <syslib/ppc85xx_common.h>
57
58#ifndef CONFIG_PCI
59unsigned long isa_io_base = 0;
60unsigned long isa_mem_base = 0;
61#endif
62
63
64extern unsigned long total_memory; /* in mm/init */
65
66unsigned char __res[sizeof (bd_t)];
67
68/* Internal interrupts are all Level Sensitive, and Positive Polarity */
69static u_char tqm85xx_openpic_initsenses[] __initdata = {
70 MPC85XX_INTERNAL_IRQ_SENSES,
71 0x0, /* External 0: */
72 0x0, /* External 1: */
73#if defined(CONFIG_PCI)
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI INTA */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI INTB */
76#else
77 0x0, /* External 2: */
78 0x0, /* External 3: */
79#endif
80 0x0, /* External 4: */
81 0x0, /* External 5: */
82 0x0, /* External 6: */
83 0x0, /* External 7: */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: PHY */
85 0x0, /* External 9: */
86 0x0, /* External 10: */
87 0x0, /* External 11: */
88};
89
90/* ************************************************************************
91 *
92 * Setup the architecture
93 *
94 */
95static void __init
96tqm85xx_setup_arch(void)
97{
98 bd_t *binfo = (bd_t *) __res;
99 unsigned int freq;
100 struct gianfar_platform_data *pdata;
101 struct gianfar_mdio_data *mdata;
102
103#ifdef CONFIG_MPC8560
104 cpm2_reset();
105#endif
106
107 /* get the core frequency */
108 freq = binfo->bi_intfreq;
109
110 if (ppc_md.progress)
111 ppc_md.progress("tqm85xx_setup_arch()", 0);
112
113 /* Set loops_per_jiffy to a half-way reasonable value,
114 for use until calibrate_delay gets called. */
115 loops_per_jiffy = freq / HZ;
116
117#ifdef CONFIG_PCI
118 /* setup PCI host bridges */
119 mpc85xx_setup_hose();
120#endif
121
122#ifndef CONFIG_MPC8560
123#if defined(CONFIG_SERIAL_8250)
124 mpc85xx_early_serial_map();
125#endif
126
127#ifdef CONFIG_SERIAL_TEXT_DEBUG
128 /* Invalidate the entry we stole earlier the serial ports
129 * should be properly mapped */
130 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
131#endif
132#endif /* CONFIG_MPC8560 */
133
134 /* setup the board related info for the MDIO bus */
135 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
136
137 mdata->irq[0] = MPC85xx_IRQ_EXT8;
138 mdata->irq[1] = MPC85xx_IRQ_EXT8;
139 mdata->irq[2] = PHY_POLL;
140 mdata->irq[3] = MPC85xx_IRQ_EXT8;
141 mdata->irq[31] = PHY_POLL;
142
143 /* setup the board related information for the enet controllers */
144 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
145 if (pdata) {
146 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
147 pdata->bus_id = 0;
148 pdata->phy_id = 2;
149 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
150 }
151
152 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
153 if (pdata) {
154 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
155 pdata->bus_id = 0;
156 pdata->phy_id = 1;
157 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
158 }
159
160#ifdef CONFIG_MPC8540
161 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);
162 if (pdata) {
163 pdata->board_flags = 0;
164 pdata->bus_id = 0;
165 pdata->phy_id = 3;
166 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);
167 }
168#endif
169
170#ifdef CONFIG_BLK_DEV_INITRD
171 if (initrd_start)
172 ROOT_DEV = Root_RAM0;
173 else
174#endif
175#ifdef CONFIG_ROOT_NFS
176 ROOT_DEV = Root_NFS;
177#else
178 ROOT_DEV = Root_HDA1;
179#endif
180}
181
182#ifdef CONFIG_MPC8560
183static irqreturn_t cpm2_cascade(int irq, void *dev_id)
184{
185 while ((irq = cpm2_get_irq()) >= 0)
186 __do_IRQ(irq);
187 return IRQ_HANDLED;
188}
189
190static struct irqaction cpm2_irqaction = {
191 .handler = cpm2_cascade,
192 .flags = IRQF_DISABLED,
193 .mask = CPU_MASK_NONE,
194 .name = "cpm2_cascade",
195};
196#endif /* CONFIG_MPC8560 */
197
198void __init
199tqm85xx_init_IRQ(void)
200{
201 bd_t *binfo = (bd_t *) __res;
202
203 /* Determine the Physical Address of the OpenPIC regs */
204 phys_addr_t OpenPIC_PAddr =
205 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
206 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
207 OpenPIC_InitSenses = tqm85xx_openpic_initsenses;
208 OpenPIC_NumInitSenses = sizeof (tqm85xx_openpic_initsenses);
209
210 /* Skip reserved space and internal sources */
211 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
212
213 /* Map PIC IRQs 0-11 */
214 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
215
216 /* we let openpic interrupts starting from an offset, to
217 * leave space for cascading interrupts underneath.
218 */
219 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
220
221#ifdef CONFIG_MPC8560
222 /* Setup CPM2 PIC */
223 cpm2_init_IRQ();
224
225 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
226#endif /* CONFIG_MPC8560 */
227
228 return;
229}
230
231int tqm85xx_show_cpuinfo(struct seq_file *m)
232{
233 uint pvid, svid, phid1;
234 uint memsize = total_memory;
235 bd_t *binfo = (bd_t *) __res;
236 unsigned int freq;
237
238 /* get the core frequency */
239 freq = binfo->bi_intfreq;
240
241 pvid = mfspr(SPRN_PVR);
242 svid = mfspr(SPRN_SVR);
243
244 seq_printf(m, "Vendor\t\t: TQ Components\n");
245 seq_printf(m, "Machine\t\t: TQM%s\n", cur_ppc_sys_spec->ppc_sys_name);
246 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
247 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
248 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
249
250 /* Display cpu Pll setting */
251 phid1 = mfspr(SPRN_HID1);
252 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
253
254 /* Display the amount of memory */
255 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
256
257 return 0;
258}
259
260#if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_DS1337)
261extern ulong ds1337_get_rtc_time(void);
262extern int ds1337_set_rtc_time(unsigned long nowtime);
263
264static int __init
265tqm85xx_rtc_hookup(void)
266{
267 struct timespec tv;
268
269 ppc_md.set_rtc_time = ds1337_set_rtc_time;
270 ppc_md.get_rtc_time = ds1337_get_rtc_time;
271
272 tv.tv_nsec = 0;
273 tv.tv_sec = (ppc_md.get_rtc_time)();
274 do_settimeofday(&tv);
275
276 return 0;
277}
278late_initcall(tqm85xx_rtc_hookup);
279#endif
280
281#ifdef CONFIG_PCI
282/*
283 * interrupt routing
284 */
285int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
286{
287 static char pci_irq_table[][4] =
288 /*
289 * PCI IDSEL/INTPIN->INTLINE
290 * A B C D
291 */
292 {
293 {PIRQA, PIRQB, 0, 0},
294 };
295
296 const long min_idsel = 0x1c, max_idsel = 0x1c, irqs_per_slot = 4;
297 return PCI_IRQ_TABLE_LOOKUP;
298}
299
300int mpc85xx_exclude_device(u_char bus, u_char devfn)
301{
302 if (bus == 0 && PCI_SLOT(devfn) == 0)
303 return PCIBIOS_DEVICE_NOT_FOUND;
304 else
305 return PCIBIOS_SUCCESSFUL;
306}
307
308#endif /* CONFIG_PCI */
309
310#ifdef CONFIG_RAPIDIO
311extern void mpc85xx_rio_setup(int law_start, int law_size);
312void platform_rio_init(void)
313{
314 /* 512MB RIO LAW at 0xc0000000 */
315 mpc85xx_rio_setup(0xc0000000, 0x20000000);
316}
317#endif /* CONFIG_RAPIDIO */
318
319/* ************************************************************************ */
320void __init
321platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
322 unsigned long r6, unsigned long r7)
323{
324 /* parse_bootinfo must always be called first */
325 parse_bootinfo(find_bootinfo());
326
327 /*
328 * If we were passed in a board information, copy it into the
329 * residual data area.
330 */
331 if (r3) {
332 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
333 sizeof (bd_t));
334 }
335
336#if defined(CONFIG_SERIAL_TEXT_DEBUG) && !defined(CONFIG_MPC8560)
337 {
338 bd_t *binfo = (bd_t *) __res;
339 struct uart_port p;
340
341 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
342 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
343 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
344
345 memset(&p, 0, sizeof (p));
346 p.iotype = UPIO_MEM;
347 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
348 p.uartclk = binfo->bi_busfreq;
349
350 gen550_init(0, &p);
351
352 memset(&p, 0, sizeof (p));
353 p.iotype = UPIO_MEM;
354 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
355 p.uartclk = binfo->bi_busfreq;
356
357 gen550_init(1, &p);
358 }
359#endif
360
361#if defined(CONFIG_BLK_DEV_INITRD)
362 /*
363 * If the init RAM disk has been configured in, and there's a valid
364 * starting address for it, set it up.
365 */
366 if (r4) {
367 initrd_start = r4 + KERNELBASE;
368 initrd_end = r5 + KERNELBASE;
369 }
370#endif /* CONFIG_BLK_DEV_INITRD */
371
372 /* Copy the kernel command line arguments to a safe place. */
373
374 if (r6) {
375 *(char *) (r7 + KERNELBASE) = 0;
376 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
377 }
378
379 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
380
381 /* setup the PowerPC module struct */
382 ppc_md.setup_arch = tqm85xx_setup_arch;
383 ppc_md.show_cpuinfo = tqm85xx_show_cpuinfo;
384
385 ppc_md.init_IRQ = tqm85xx_init_IRQ;
386 ppc_md.get_irq = openpic_get_irq;
387
388 ppc_md.restart = mpc85xx_restart;
389 ppc_md.power_off = mpc85xx_power_off;
390 ppc_md.halt = mpc85xx_halt;
391
392 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
393
394 ppc_md.time_init = NULL;
395 ppc_md.set_rtc_time = NULL;
396 ppc_md.get_rtc_time = NULL;
397 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
398
399#ifndef CONFIG_MPC8560
400#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
401 ppc_md.progress = gen550_progress;
402#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
403#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
404 ppc_md.early_serial_map = mpc85xx_early_serial_map;
405#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
406#endif /* CONFIG_MPC8560 */
407
408 if (ppc_md.progress)
409 ppc_md.progress("tqm85xx_init(): exit", 0);
410
411 return;
412}
diff --git a/arch/ppc/platforms/85xx/tqm85xx.h b/arch/ppc/platforms/85xx/tqm85xx.h
deleted file mode 100644
index 57284e68f676..000000000000
--- a/arch/ppc/platforms/85xx/tqm85xx.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * TQM85xx (40/41/55/60) board definitions
3 *
4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#ifndef __MACH_TQM85XX_H
15#define __MACH_TQM85XX_H
16
17#include <linux/init.h>
18#include <asm/ppcboot.h>
19
20#define BOARD_CCSRBAR ((uint)0xe0000000)
21#define CCSRBAR_SIZE ((uint)1024*1024)
22
23#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
24
25#define PCI_CFG_ADDR_OFFSET (0x8000)
26#define PCI_CFG_DATA_OFFSET (0x8004)
27
28/* PCI interrupt controller */
29#define PIRQA MPC85xx_IRQ_EXT2
30#define PIRQB MPC85xx_IRQ_EXT3
31
32#define MPC85XX_PCI1_LOWER_IO 0x00000000
33#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
34
35#define MPC85XX_PCI1_LOWER_MEM 0x80000000
36#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
37
38#define MPC85XX_PCI1_IO_BASE 0xe2000000
39#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
40
41#define MPC85XX_PCI1_IO_SIZE 0x01000000
42
43#define BASE_BAUD 115200
44
45extern void mpc85xx_setup_hose(void) __init;
46extern void mpc85xx_restart(char *cmd);
47extern void mpc85xx_power_off(void);
48extern void mpc85xx_halt(void);
49extern void mpc85xx_init_IRQ(void) __init;
50extern unsigned long mpc85xx_find_end_of_memory(void) __init;
51extern void mpc85xx_calibrate_decr(void) __init;
52
53#endif /* __MACH_TQM85XX_H */
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