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authorKumar Gala <galak@freescale.com>2005-09-03 18:55:20 -0400
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 03:05:52 -0400
commita3800d8ffa0a91f3047cbfa82e435d483ffc8dd4 (patch)
tree9f21eecb73886b4fe6b53d2427e2ad7f43005e40 /arch/ppc/platforms
parent4b4dc82247184504ba6d0689566a25d03eb1095c (diff)
[PATCH] ppc32: Remove board support for ADIR
Support for the ADIR board is no longer maintained and thus being removed Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r--arch/ppc/platforms/Makefile1
-rw-r--r--arch/ppc/platforms/adir.h95
-rw-r--r--arch/ppc/platforms/adir_pci.c247
-rw-r--r--arch/ppc/platforms/adir_pic.c130
-rw-r--r--arch/ppc/platforms/adir_setup.c210
5 files changed, 0 insertions, 683 deletions
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
index 5488a053f415..fcd03e52f602 100644
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o
21endif 21endif
22obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o 22obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o
23obj-$(CONFIG_PREP_RESIDUAL) += residual.o 23obj-$(CONFIG_PREP_RESIDUAL) += residual.o
24obj-$(CONFIG_ADIR) += adir_setup.o adir_pic.o adir_pci.o
25obj-$(CONFIG_PQ2ADS) += pq2ads.o 24obj-$(CONFIG_PQ2ADS) += pq2ads.o
26obj-$(CONFIG_TQM8260) += tqm8260_setup.o 25obj-$(CONFIG_TQM8260) += tqm8260_setup.o
27obj-$(CONFIG_CPCI690) += cpci690.o 26obj-$(CONFIG_CPCI690) += cpci690.o
diff --git a/arch/ppc/platforms/adir.h b/arch/ppc/platforms/adir.h
deleted file mode 100644
index 13a748b46956..000000000000
--- a/arch/ppc/platforms/adir.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * arch/ppc/platforms/adir.h
3 *
4 * Definitions for SBS Adirondack board support
5 *
6 * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
7 */
8
9#ifndef __PPC_PLATFORMS_ADIR_H
10#define __PPC_PLATFORMS_ADIR_H
11
12/*
13 * SBS Adirondack definitions
14 */
15
16/* PPC physical address space layout. We use the one set up by the firmware. */
17#define ADIR_PCI32_MEM_BASE 0x80000000
18#define ADIR_PCI32_MEM_SIZE 0x20000000
19#define ADIR_PCI64_MEM_BASE 0xA0000000
20#define ADIR_PCI64_MEM_SIZE 0x20000000
21#define ADIR_PCI32_IO_BASE 0xC0000000
22#define ADIR_PCI32_IO_SIZE 0x10000000
23#define ADIR_PCI64_IO_BASE 0xD0000000
24#define ADIR_PCI64_IO_SIZE 0x10000000
25#define ADIR_PCI64_PHB 0xFF400000
26#define ADIR_PCI32_PHB 0xFF500000
27
28#define ADIR_PCI64_CONFIG_ADDR (ADIR_PCI64_PHB + 0x000f8000)
29#define ADIR_PCI64_CONFIG_DATA (ADIR_PCI64_PHB + 0x000f8010)
30
31#define ADIR_PCI32_CONFIG_ADDR (ADIR_PCI32_PHB + 0x000f8000)
32#define ADIR_PCI32_CONFIG_DATA (ADIR_PCI32_PHB + 0x000f8010)
33
34/* System memory as seen from PCI */
35#define ADIR_PCI_SYS_MEM_BASE 0x80000000
36
37/* Static virtual mapping of PCI I/O */
38#define ADIR_PCI32_VIRT_IO_BASE 0xFE000000
39#define ADIR_PCI32_VIRT_IO_SIZE 0x01000000
40#define ADIR_PCI64_VIRT_IO_BASE 0xFF000000
41#define ADIR_PCI64_VIRT_IO_SIZE 0x01000000
42
43/* Registers */
44#define ADIR_NVRAM_RTC_ADDR 0x74
45#define ADIR_NVRAM_RTC_DATA 0x75
46
47#define ADIR_BOARD_ID_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF0)
48#define ADIR_CPLD1REV_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF1)
49#define ADIR_CPLD2REV_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF2)
50#define ADIR_FLASHCTL_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF3)
51#define ADIR_CPC710_STAT_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF4)
52#define ADIR_CLOCK_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF5)
53#define ADIR_GPIO_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF8)
54#define ADIR_MISC_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF9)
55#define ADIR_LED_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFFA)
56
57#define ADIR_CLOCK_REG_PD 0x10
58#define ADIR_CLOCK_REG_SPREAD 0x08
59#define ADIR_CLOCK_REG_SEL133 0x04
60#define ADIR_CLOCK_REG_SEL1 0x02
61#define ADIR_CLOCK_REG_SEL0 0x01
62
63#define ADIR_PROCA_INT_MASK (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF0)
64#define ADIR_PROCB_INT_MASK (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF2)
65#define ADIR_PROCA_INT_STAT (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF4)
66#define ADIR_PROCB_INT_STAT (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF6)
67
68/* Linux IRQ numbers */
69#define ADIR_IRQ_NONE -1
70#define ADIR_IRQ_SERIAL2 3
71#define ADIR_IRQ_SERIAL1 4
72#define ADIR_IRQ_FDC 6
73#define ADIR_IRQ_PARALLEL 7
74#define ADIR_IRQ_VIA_AUDIO 10
75#define ADIR_IRQ_VIA_USB 11
76#define ADIR_IRQ_IDE0 14
77#define ADIR_IRQ_IDE1 15
78#define ADIR_IRQ_PCI0_INTA 16
79#define ADIR_IRQ_PCI0_INTB 17
80#define ADIR_IRQ_PCI0_INTC 18
81#define ADIR_IRQ_PCI0_INTD 19
82#define ADIR_IRQ_PCI1_INTA 20
83#define ADIR_IRQ_PCI1_INTB 21
84#define ADIR_IRQ_PCI1_INTC 22
85#define ADIR_IRQ_PCI1_INTD 23
86#define ADIR_IRQ_MBSCSI 24 /* motherboard SCSI */
87#define ADIR_IRQ_MBETH1 25 /* motherboard Ethernet 1 */
88#define ADIR_IRQ_MBETH0 26 /* motherboard Ethernet 0 */
89#define ADIR_IRQ_CPC710_INT1 27
90#define ADIR_IRQ_CPC710_INT2 28
91#define ADIR_IRQ_VT82C686_NMI 29
92#define ADIR_IRQ_VT82C686_INTR 30
93#define ADIR_IRQ_INTERPROC 31
94
95#endif /* __PPC_PLATFORMS_ADIR_H */
diff --git a/arch/ppc/platforms/adir_pci.c b/arch/ppc/platforms/adir_pci.c
deleted file mode 100644
index f94ac53e0711..000000000000
--- a/arch/ppc/platforms/adir_pci.c
+++ /dev/null
@@ -1,247 +0,0 @@
1/*
2 * arch/ppc/platforms/adir_pci.c
3 *
4 * PCI support for SBS Adirondack
5 *
6 * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
7 * based on the K2 version by Matt Porter <mporter@mvista.com>
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/pci.h>
13#include <linux/slab.h>
14
15#include <asm/byteorder.h>
16#include <asm/io.h>
17#include <asm/uaccess.h>
18#include <asm/machdep.h>
19#include <asm/pci-bridge.h>
20
21#include <syslib/cpc710.h>
22#include "adir.h"
23
24#undef DEBUG
25#ifdef DEBUG
26#define DBG(x...) printk(x)
27#else
28#define DBG(x...)
29#endif /* DEBUG */
30
31static inline int __init
32adir_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
33{
34#define PCIIRQ(a,b,c,d) {ADIR_IRQ_##a,ADIR_IRQ_##b,ADIR_IRQ_##c,ADIR_IRQ_##d},
35 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
36 /*
37 * The three PCI devices on the motherboard have dedicated lines to the
38 * CPLD interrupt controller, bypassing the standard PCI INTA-D and the
39 * PC interrupt controller. All other PCI devices (slots) have usual
40 * staggered INTA-D lines, resulting in 8 lines total (PCI0 INTA-D and
41 * PCI1 INTA-D). All 8 go to the CPLD interrupt controller. PCI0 INTA-D
42 * also go to the south bridge, so we have the option of taking them
43 * via the CPLD interrupt controller or via the south bridge 8259
44 * 8258 thingy. PCI1 INTA-D can only be taken via the CPLD interrupt
45 * controller. We take all PCI interrupts via the CPLD interrupt
46 * controller as recommended by SBS.
47 *
48 * We also have some monkey business with the PCI devices within the
49 * VT82C686B south bridge itself. This chip actually has 7 functions on
50 * its IDSEL. Function 0 is the actual south bridge, function 1 is IDE,
51 * and function 4 is some special stuff. The other 4 functions are just
52 * regular PCI devices bundled in the chip. 2 and 3 are USB UHCIs and 5
53 * and 6 are audio (not supported on the Adirondack).
54 *
55 * This is where the monkey business begins. PCI devices are supposed
56 * to signal normal PCI interrupts. But the 4 functions in question are
57 * located in the south bridge chip, which is designed with the
58 * assumption that it will be fielding PCI INTA-D interrupts rather
59 * than generating them. Here's what it does. Each of the functions in
60 * question routes its interrupt to one of the IRQs on the 8259 thingy.
61 * Which one? It looks at the Interrupt Line register in the PCI config
62 * space, even though the PCI spec says it's for BIOS/OS interaction
63 * only.
64 *
65 * How do we deal with this? We take these interrupts via 8259 IRQs as
66 * we have to. We return the desired IRQ numbers from this routine when
67 * called for the functions in question. The PCI scan code will then
68 * stick our return value into the Interrupt Line register in the PCI
69 * config space, and the interrupt will actually go there. We identify
70 * these functions within the south bridge IDSEL by their interrupt pin
71 * numbers, as the VT82C686B has 04 in the Interrupt Pin register for
72 * USB and 03 for audio.
73 */
74 if (!hose->index) {
75 static char pci_irq_table[][4] =
76 /*
77 * PCI IDSEL/INTPIN->INTLINE
78 * A B C D
79 */
80 {
81 /* south bridge */ PCIIRQ(IDE0, NONE, VIA_AUDIO, VIA_USB)
82 /* Ethernet 0 */ PCIIRQ(MBETH0, MBETH0, MBETH0, MBETH0)
83 /* PCI0 slot 1 */ PCIIRQ(PCI0_INTB, PCI0_INTC, PCI0_INTD, PCI0_INTA)
84 /* PCI0 slot 2 */ PCIIRQ(PCI0_INTC, PCI0_INTD, PCI0_INTA, PCI0_INTB)
85 /* PCI0 slot 3 */ PCIIRQ(PCI0_INTD, PCI0_INTA, PCI0_INTB, PCI0_INTC)
86 };
87 const long min_idsel = 3, max_idsel = 7, irqs_per_slot = 4;
88 return PCI_IRQ_TABLE_LOOKUP;
89 } else {
90 static char pci_irq_table[][4] =
91 /*
92 * PCI IDSEL/INTPIN->INTLINE
93 * A B C D
94 */
95 {
96 /* Ethernet 1 */ PCIIRQ(MBETH1, MBETH1, MBETH1, MBETH1)
97 /* SCSI */ PCIIRQ(MBSCSI, MBSCSI, MBSCSI, MBSCSI)
98 /* PCI1 slot 1 */ PCIIRQ(PCI1_INTB, PCI1_INTC, PCI1_INTD, PCI1_INTA)
99 /* PCI1 slot 2 */ PCIIRQ(PCI1_INTC, PCI1_INTD, PCI1_INTA, PCI1_INTB)
100 /* PCI1 slot 3 */ PCIIRQ(PCI1_INTD, PCI1_INTA, PCI1_INTB, PCI1_INTC)
101 };
102 const long min_idsel = 3, max_idsel = 7, irqs_per_slot = 4;
103 return PCI_IRQ_TABLE_LOOKUP;
104 }
105#undef PCIIRQ
106}
107
108static void
109adir_pcibios_fixup_resources(struct pci_dev *dev)
110{
111 int i;
112
113 if ((dev->vendor == PCI_VENDOR_ID_IBM) &&
114 (dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64))
115 {
116 DBG("Fixup CPC710 resources\n");
117 for (i=0; i<DEVICE_COUNT_RESOURCE; i++)
118 {
119 dev->resource[i].start = 0;
120 dev->resource[i].end = 0;
121 }
122 }
123}
124
125/*
126 * CPC710 DD3 has an errata causing it to hang the system if a type 0 config
127 * cycle is attempted on its PCI32 interface with a device number > 21.
128 * CPC710's PCI bridges map device numbers 1 through 21 to AD11 through AD31.
129 * Per the PCI spec it MUST accept all other device numbers and do nothing, and
130 * software MUST scan all device numbers without assuming how IDSELs are
131 * mapped. However, as the CPC710 DD3's errata causes such correct scanning
132 * procedure to hang the system, we have no choice but to introduce this hack
133 * of knowingly avoiding device numbers > 21 on PCI0,
134 */
135static int
136adir_exclude_device(u_char bus, u_char devfn)
137{
138 if ((bus == 0) && (PCI_SLOT(devfn) > 21))
139 return PCIBIOS_DEVICE_NOT_FOUND;
140 else
141 return PCIBIOS_SUCCESSFUL;
142}
143
144void adir_find_bridges(void)
145{
146 struct pci_controller *hose_a, *hose_b;
147
148 /* Setup PCI32 hose */
149 hose_a = pcibios_alloc_controller();
150 if (!hose_a)
151 return;
152
153 hose_a->first_busno = 0;
154 hose_a->last_busno = 0xff;
155 hose_a->pci_mem_offset = ADIR_PCI32_MEM_BASE;
156 hose_a->io_space.start = 0;
157 hose_a->io_space.end = ADIR_PCI32_VIRT_IO_SIZE - 1;
158 hose_a->mem_space.start = 0;
159 hose_a->mem_space.end = ADIR_PCI32_MEM_SIZE - 1;
160 hose_a->io_resource.start = 0;
161 hose_a->io_resource.end = ADIR_PCI32_VIRT_IO_SIZE - 1;
162 hose_a->io_resource.flags = IORESOURCE_IO;
163 hose_a->mem_resources[0].start = ADIR_PCI32_MEM_BASE;
164 hose_a->mem_resources[0].end = ADIR_PCI32_MEM_BASE +
165 ADIR_PCI32_MEM_SIZE - 1;
166 hose_a->mem_resources[0].flags = IORESOURCE_MEM;
167 hose_a->io_base_phys = ADIR_PCI32_IO_BASE;
168 hose_a->io_base_virt = (void *) ADIR_PCI32_VIRT_IO_BASE;
169
170 ppc_md.pci_exclude_device = adir_exclude_device;
171 setup_indirect_pci(hose_a, ADIR_PCI32_CONFIG_ADDR,
172 ADIR_PCI32_CONFIG_DATA);
173
174 /* Initialize PCI32 bus registers */
175 early_write_config_byte(hose_a,
176 hose_a->first_busno,
177 PCI_DEVFN(0, 0),
178 CPC710_BUS_NUMBER,
179 hose_a->first_busno);
180 early_write_config_byte(hose_a,
181 hose_a->first_busno,
182 PCI_DEVFN(0, 0),
183 CPC710_SUB_BUS_NUMBER,
184 hose_a->last_busno);
185
186 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
187
188 /* Write out correct max subordinate bus number for hose A */
189 early_write_config_byte(hose_a,
190 hose_a->first_busno,
191 PCI_DEVFN(0, 0),
192 CPC710_SUB_BUS_NUMBER,
193 hose_a->last_busno);
194
195 /* Setup PCI64 hose */
196 hose_b = pcibios_alloc_controller();
197 if (!hose_b)
198 return;
199
200 hose_b->first_busno = hose_a->last_busno + 1;
201 hose_b->last_busno = 0xff;
202 hose_b->pci_mem_offset = ADIR_PCI64_MEM_BASE;
203 hose_b->io_space.start = 0;
204 hose_b->io_space.end = ADIR_PCI64_VIRT_IO_SIZE - 1;
205 hose_b->mem_space.start = 0;
206 hose_b->mem_space.end = ADIR_PCI64_MEM_SIZE - 1;
207 hose_b->io_resource.start = 0;
208 hose_b->io_resource.end = ADIR_PCI64_VIRT_IO_SIZE - 1;
209 hose_b->io_resource.flags = IORESOURCE_IO;
210 hose_b->mem_resources[0].start = ADIR_PCI64_MEM_BASE;
211 hose_b->mem_resources[0].end = ADIR_PCI64_MEM_BASE +
212 ADIR_PCI64_MEM_SIZE - 1;
213 hose_b->mem_resources[0].flags = IORESOURCE_MEM;
214 hose_b->io_base_phys = ADIR_PCI64_IO_BASE;
215 hose_b->io_base_virt = (void *) ADIR_PCI64_VIRT_IO_BASE;
216
217 setup_indirect_pci(hose_b, ADIR_PCI64_CONFIG_ADDR,
218 ADIR_PCI64_CONFIG_DATA);
219
220 /* Initialize PCI64 bus registers */
221 early_write_config_byte(hose_b,
222 0,
223 PCI_DEVFN(0, 0),
224 CPC710_SUB_BUS_NUMBER,
225 0xff);
226
227 early_write_config_byte(hose_b,
228 0,
229 PCI_DEVFN(0, 0),
230 CPC710_BUS_NUMBER,
231 hose_b->first_busno);
232
233 hose_b->last_busno = pciauto_bus_scan(hose_b,
234 hose_b->first_busno);
235
236 /* Write out correct max subordinate bus number for hose B */
237 early_write_config_byte(hose_b,
238 hose_b->first_busno,
239 PCI_DEVFN(0, 0),
240 CPC710_SUB_BUS_NUMBER,
241 hose_b->last_busno);
242
243 ppc_md.pcibios_fixup = NULL;
244 ppc_md.pcibios_fixup_resources = adir_pcibios_fixup_resources;
245 ppc_md.pci_swizzle = common_swizzle;
246 ppc_md.pci_map_irq = adir_map_irq;
247}
diff --git a/arch/ppc/platforms/adir_pic.c b/arch/ppc/platforms/adir_pic.c
deleted file mode 100644
index 9947cba52af5..000000000000
--- a/arch/ppc/platforms/adir_pic.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 * arch/ppc/platforms/adir_pic.c
3 *
4 * Interrupt controller support for SBS Adirondack
5 *
6 * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
7 * based on the K2 and SCM versions by Matt Porter <mporter@mvista.com>
8 */
9
10#include <linux/stddef.h>
11#include <linux/init.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/interrupt.h>
15
16#include <asm/io.h>
17#include <asm/i8259.h>
18#include "adir.h"
19
20static void adir_onboard_pic_enable(unsigned int irq);
21static void adir_onboard_pic_disable(unsigned int irq);
22
23__init static void
24adir_onboard_pic_init(void)
25{
26 volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK;
27
28 /* Disable all Adirondack onboard interrupts */
29 out_be16(maskreg, 0xFFFF);
30}
31
32static int
33adir_onboard_pic_get_irq(void)
34{
35 volatile u_short *statreg = (volatile u_short *) ADIR_PROCA_INT_STAT;
36 int irq;
37 u_short int_status, int_test;
38
39 int_status = in_be16(statreg);
40 for (irq = 0, int_test = 1; irq < 16; irq++, int_test <<= 1) {
41 if (int_status & int_test)
42 break;
43 }
44
45 if (irq == 16)
46 return -1;
47
48 return (irq+16);
49}
50
51static void
52adir_onboard_pic_enable(unsigned int irq)
53{
54 volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK;
55
56 /* Change irq to Adirondack onboard native value */
57 irq -= 16;
58
59 /* Enable requested irq number */
60 out_be16(maskreg, in_be16(maskreg) & ~(1 << irq));
61}
62
63static void
64adir_onboard_pic_disable(unsigned int irq)
65{
66 volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK;
67
68 /* Change irq to Adirondack onboard native value */
69 irq -= 16;
70
71 /* Disable requested irq number */
72 out_be16(maskreg, in_be16(maskreg) | (1 << irq));
73}
74
75static struct hw_interrupt_type adir_onboard_pic = {
76 " ADIR PIC ",
77 NULL,
78 NULL,
79 adir_onboard_pic_enable, /* unmask */
80 adir_onboard_pic_disable, /* mask */
81 adir_onboard_pic_disable, /* mask and ack */
82 NULL,
83 NULL
84};
85
86static struct irqaction noop_action = {
87 .handler = no_action,
88 .flags = SA_INTERRUPT,
89 .mask = CPU_MASK_NONE,
90 .name = "82c59 primary cascade",
91};
92
93/*
94 * Linux interrupt values are assigned as follows:
95 *
96 * 0-15 VT82C686 8259 interrupts
97 * 16-31 Adirondack CPLD interrupts
98 */
99__init void
100adir_init_IRQ(void)
101{
102 int i;
103
104 /* Initialize the cascaded 8259's on the VT82C686 */
105 for (i=0; i<16; i++)
106 irq_desc[i].handler = &i8259_pic;
107 i8259_init(NULL);
108
109 /* Initialize Adirondack CPLD PIC and enable 8259 interrupt cascade */
110 for (i=16; i<32; i++)
111 irq_desc[i].handler = &adir_onboard_pic;
112 adir_onboard_pic_init();
113
114 /* Enable 8259 interrupt cascade */
115 setup_irq(ADIR_IRQ_VT82C686_INTR, &noop_action);
116}
117
118int
119adir_get_irq(struct pt_regs *regs)
120{
121 int irq;
122
123 if ((irq = adir_onboard_pic_get_irq()) < 0)
124 return irq;
125
126 if (irq == ADIR_IRQ_VT82C686_INTR)
127 irq = i8259_irq(regs);
128
129 return irq;
130}
diff --git a/arch/ppc/platforms/adir_setup.c b/arch/ppc/platforms/adir_setup.c
deleted file mode 100644
index 6a6754ee0617..000000000000
--- a/arch/ppc/platforms/adir_setup.c
+++ /dev/null
@@ -1,210 +0,0 @@
1/*
2 * arch/ppc/platforms/adir_setup.c
3 *
4 * Board setup routines for SBS Adirondack
5 *
6 * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
7 * based on the K2 version by Matt Porter <mporter@mvista.com>
8 */
9
10#include <linux/config.h>
11#include <linux/stddef.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/errno.h>
15#include <linux/reboot.h>
16#include <linux/pci.h>
17#include <linux/kdev_t.h>
18#include <linux/types.h>
19#include <linux/major.h>
20#include <linux/initrd.h>
21#include <linux/console.h>
22#include <linux/delay.h>
23#include <linux/ide.h>
24#include <linux/seq_file.h>
25#include <linux/root_dev.h>
26
27#include <asm/system.h>
28#include <asm/pgtable.h>
29#include <asm/page.h>
30#include <asm/dma.h>
31#include <asm/io.h>
32#include <asm/machdep.h>
33#include <asm/time.h>
34#include <asm/todc.h>
35#include <asm/bootinfo.h>
36
37#include "adir.h"
38
39extern void adir_init_IRQ(void);
40extern int adir_get_irq(struct pt_regs *);
41extern void adir_find_bridges(void);
42extern unsigned long loops_per_jiffy;
43
44static unsigned int cpu_750cx[16] = {
45 5, 15, 14, 0, 4, 13, 0, 9, 6, 11, 8, 10, 16, 12, 7, 0
46};
47
48static int
49adir_get_bus_speed(void)
50{
51 if (!(*((u_char *) ADIR_CLOCK_REG) & ADIR_CLOCK_REG_SEL133))
52 return 100000000;
53 else
54 return 133333333;
55}
56
57static int
58adir_get_cpu_speed(void)
59{
60 unsigned long hid1;
61 int cpu_speed;
62
63 hid1 = mfspr(SPRN_HID1) >> 28;
64
65 hid1 = cpu_750cx[hid1];
66
67 cpu_speed = adir_get_bus_speed()*hid1/2;
68 return cpu_speed;
69}
70
71static void __init
72adir_calibrate_decr(void)
73{
74 int freq, divisor = 4;
75
76 /* determine processor bus speed */
77 freq = adir_get_bus_speed();
78 tb_ticks_per_jiffy = freq / HZ / divisor;
79 tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
80}
81
82static int
83adir_show_cpuinfo(struct seq_file *m)
84{
85 seq_printf(m, "vendor\t\t: SBS\n");
86 seq_printf(m, "machine\t\t: Adirondack\n");
87 seq_printf(m, "cpu speed\t: %dMhz\n", adir_get_cpu_speed()/1000000);
88 seq_printf(m, "bus speed\t: %dMhz\n", adir_get_bus_speed()/1000000);
89 seq_printf(m, "memory type\t: SDRAM\n");
90
91 return 0;
92}
93
94extern char cmd_line[];
95
96TODC_ALLOC();
97
98static void __init
99adir_setup_arch(void)
100{
101 unsigned int cpu;
102
103 /* Setup TODC access */
104 TODC_INIT(TODC_TYPE_MC146818, ADIR_NVRAM_RTC_ADDR, 0,
105 ADIR_NVRAM_RTC_DATA, 8);
106
107 /* init to some ~sane value until calibrate_delay() runs */
108 loops_per_jiffy = 50000000/HZ;
109
110 /* Setup PCI host bridges */
111 adir_find_bridges();
112
113#ifdef CONFIG_BLK_DEV_INITRD
114 if (initrd_start)
115 ROOT_DEV = Root_RAM0;
116 else
117#endif
118#ifdef CONFIG_ROOT_NFS
119 ROOT_DEV = Root_NFS;
120#else
121 ROOT_DEV = Root_SDA1;
122#endif
123
124 /* Identify the system */
125 printk("System Identification: SBS Adirondack - PowerPC 750CXe @ %d Mhz\n", adir_get_cpu_speed()/1000000);
126 printk("SBS Adirondack port (C) 2001 SBS Technologies, Inc.\n");
127
128 /* Identify the CPU manufacturer */
129 cpu = mfspr(SPRN_PVR);
130 printk("CPU manufacturer: IBM [rev=%04x]\n", (cpu & 0xffff));
131}
132
133static void
134adir_restart(char *cmd)
135{
136 local_irq_disable();
137 /* SRR0 has system reset vector, SRR1 has default MSR value */
138 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
139 __asm__ __volatile__
140 ("lis 3,0xfff0\n\t"
141 "ori 3,3,0x0100\n\t"
142 "mtspr 26,3\n\t"
143 "li 3,0\n\t"
144 "mtspr 27,3\n\t"
145 "rfi\n\t");
146 for(;;);
147}
148
149static void
150adir_power_off(void)
151{
152 for(;;);
153}
154
155static void
156adir_halt(void)
157{
158 adir_restart(NULL);
159}
160
161static unsigned long __init
162adir_find_end_of_memory(void)
163{
164 return boot_mem_size;
165}
166
167static void __init
168adir_map_io(void)
169{
170 io_block_mapping(ADIR_PCI32_VIRT_IO_BASE, ADIR_PCI32_IO_BASE,
171 ADIR_PCI32_VIRT_IO_SIZE, _PAGE_IO);
172 io_block_mapping(ADIR_PCI64_VIRT_IO_BASE, ADIR_PCI64_IO_BASE,
173 ADIR_PCI64_VIRT_IO_SIZE, _PAGE_IO);
174}
175
176void __init
177platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
178 unsigned long r6, unsigned long r7)
179{
180 /*
181 * On the Adirondack we use bi_recs and pass the pointer to them in R3.
182 */
183 parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
184
185 /* Remember, isa_io_base is virtual but isa_mem_base is physical! */
186 isa_io_base = ADIR_PCI32_VIRT_IO_BASE;
187 isa_mem_base = ADIR_PCI32_MEM_BASE;
188 pci_dram_offset = ADIR_PCI_SYS_MEM_BASE;
189
190 ppc_md.setup_arch = adir_setup_arch;
191 ppc_md.show_cpuinfo = adir_show_cpuinfo;
192 ppc_md.irq_canonicalize = NULL;
193 ppc_md.init_IRQ = adir_init_IRQ;
194 ppc_md.get_irq = adir_get_irq;
195 ppc_md.init = NULL;
196
197 ppc_md.find_end_of_memory = adir_find_end_of_memory;
198 ppc_md.setup_io_mappings = adir_map_io;
199
200 ppc_md.restart = adir_restart;
201 ppc_md.power_off = adir_power_off;
202 ppc_md.halt = adir_halt;
203
204 ppc_md.time_init = todc_time_init;
205 ppc_md.set_rtc_time = todc_set_rtc_time;
206 ppc_md.get_rtc_time = todc_get_rtc_time;
207 ppc_md.nvram_read_val = todc_mc146818_read_val;
208 ppc_md.nvram_write_val = todc_mc146818_write_val;
209 ppc_md.calibrate_decr = adir_calibrate_decr;
210}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 01:31:43 -0500