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authorKumar Gala <galak@freescale.com>2005-09-03 18:55:21 -0400
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 03:05:53 -0400
commitf4f1269cb36adfb452c04dcb3d40f51b8a1956bb (patch)
treef078687fe13c314dabb8c68e1f50f8d99632b500 /arch/ppc/platforms
parenta3800d8ffa0a91f3047cbfa82e435d483ffc8dd4 (diff)
[PATCH] ppc32: Remove board support for ASH
Support for the ASH board is no longer maintained and thus being removed Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r--arch/ppc/platforms/4xx/Kconfig5
-rw-r--r--arch/ppc/platforms/4xx/Makefile1
-rw-r--r--arch/ppc/platforms/4xx/ash.c250
-rw-r--r--arch/ppc/platforms/4xx/ash.h83
4 files changed, 0 insertions, 339 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index 805dd98908a3..a7eaba91dfbf 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -16,11 +16,6 @@ choice
16 depends on 40x 16 depends on 40x
17 default WALNUT 17 default WALNUT
18 18
19config ASH
20 bool "Ash"
21 help
22 This option enables support for the IBM NP405H evaluation board.
23
24config BUBINGA 19config BUBINGA
25 bool "Bubinga" 20 bool "Bubinga"
26 select WANT_EARLY_SERIAL 21 select WANT_EARLY_SERIAL
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index 844c3b5066e8..f00e0d02ee2c 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -1,7 +1,6 @@
1# 1#
2# Makefile for the PowerPC 4xx linux kernel. 2# Makefile for the PowerPC 4xx linux kernel.
3 3
4obj-$(CONFIG_ASH) += ash.o
5obj-$(CONFIG_BAMBOO) += bamboo.o 4obj-$(CONFIG_BAMBOO) += bamboo.o
6obj-$(CONFIG_CPCI405) += cpci405.o 5obj-$(CONFIG_CPCI405) += cpci405.o
7obj-$(CONFIG_EBONY) += ebony.o 6obj-$(CONFIG_EBONY) += ebony.o
diff --git a/arch/ppc/platforms/4xx/ash.c b/arch/ppc/platforms/4xx/ash.c
deleted file mode 100644
index ce2911793716..000000000000
--- a/arch/ppc/platforms/4xx/ash.c
+++ /dev/null
@@ -1,250 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/ash.c
3 *
4 * Support for the IBM NP405H ash eval board
5 *
6 * Author: Armin Kuster <akuster@mvista.com>
7 *
8 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/pagemap.h>
16#include <linux/pci.h>
17
18#include <asm/machdep.h>
19#include <asm/pci-bridge.h>
20#include <asm/io.h>
21#include <asm/ocp.h>
22#include <asm/ibm_ocp_pci.h>
23#include <asm/todc.h>
24
25#ifdef DEBUG
26#define DBG(x...) printk(x)
27#else
28#define DBG(x...)
29#endif
30
31void *ash_rtc_base;
32
33/* Some IRQs unique to Walnut.
34 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
35 */
36int __init
37ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
38{
39 static char pci_irq_table[][4] =
40 /*
41 * PCI IDSEL/INTPIN->INTLINE
42 * A B C D
43 */
44 {
45 {24, 24, 24, 24}, /* IDSEL 1 - PCI slot 1 */
46 {25, 25, 25, 25}, /* IDSEL 2 - PCI slot 2 */
47 {26, 26, 26, 26}, /* IDSEL 3 - PCI slot 3 */
48 {27, 27, 27, 27}, /* IDSEL 4 - PCI slot 4 */
49 };
50
51 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
52 return PCI_IRQ_TABLE_LOOKUP;
53}
54
55void __init
56ash_setup_arch(void)
57{
58 ppc4xx_setup_arch();
59
60 ibm_ocp_set_emac(0, 3);
61
62#ifdef CONFIG_DEBUG_BRINGUP
63 int i;
64 printk("\n");
65 printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
66 printk("\n");
67 printk("bi_s_version\t %s\n", bip->bi_s_version);
68 printk("bi_r_version\t %s\n", bip->bi_r_version);
69 printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
70 bip->bi_memsize / (1024 * 1000));
71 for (i = 0; i < EMAC_NUMS; i++) {
72 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", i,
73 bip->bi_enetaddr[i][0], bip->bi_enetaddr[i][1],
74 bip->bi_enetaddr[i][2], bip->bi_enetaddr[i][3],
75 bip->bi_enetaddr[i][4], bip->bi_enetaddr[i][5]);
76 }
77 printk("bi_pci_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
78 bip->bi_pci_enetaddr[0], bip->bi_pci_enetaddr[1],
79 bip->bi_pci_enetaddr[2], bip->bi_pci_enetaddr[3],
80 bip->bi_pci_enetaddr[4], bip->bi_pci_enetaddr[5]);
81
82 printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
83 bip->bi_intfreq, bip->bi_intfreq / 1000000);
84
85 printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
86 bip->bi_busfreq, bip->bi_busfreq / 1000000);
87 printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
88 bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000);
89
90 printk("\n");
91#endif
92 /* RTC step for ash */
93 ash_rtc_base = (void *) ASH_RTC_VADDR;
94 TODC_INIT(TODC_TYPE_DS1743, ash_rtc_base, ash_rtc_base, ash_rtc_base,
95 8);
96}
97
98void __init
99bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
100{
101 /*
102 * Expected PCI mapping:
103 *
104 * PLB addr PCI memory addr
105 * --------------------- ---------------------
106 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
107 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
108 *
109 * PLB addr PCI io addr
110 * --------------------- ---------------------
111 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
112 *
113 * The following code is simplified by assuming that the bootrom
114 * has been well behaved in following this mapping.
115 */
116
117#ifdef DEBUG
118 int i;
119
120 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
121 printk("PCI bridge regs before fixup \n");
122 for (i = 0; i <= 2; i++) {
123 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
124 printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
125 printk(" pmm%dpcila\t0x%x\n", i,
126 in_le32(&(pcip->pmm[i].pcila)));
127 printk(" pmm%dpciha\t0x%x\n", i,
128 in_le32(&(pcip->pmm[i].pciha)));
129 }
130 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
131 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
132 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
133 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
134 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
135 early_read_config_dword(hose, hose->first_busno,
136 PCI_FUNC(hose->first_busno), bar,
137 &bar_response);
138 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
139 hose->first_busno, PCI_SLOT(hose->first_busno),
140 PCI_FUNC(hose->first_busno), bar, bar_response);
141 }
142
143#endif
144 if (ppc_md.progress)
145 ppc_md.progress("bios_fixup(): enter", 0x800);
146
147 /* added for IBM boot rom version 1.15 bios bar changes -AK */
148
149 /* Disable region first */
150 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
151 /* PLB starting addr, PCI: 0x80000000 */
152 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
153 /* PCI start addr, 0x80000000 */
154 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
155 /* 512MB range of PLB to PCI */
156 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
157 /* Enable no pre-fetch, enable region */
158 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
159 (PPC405_PCI_UPPER_MEM -
160 PPC405_PCI_MEM_BASE)) | 0x01));
161
162 /* Disable region one */
163 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
164 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
165 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
166 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
167 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
168
169 /* Disable region two */
170 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
171 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
172 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
173 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
174 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
175
176 /* Enable PTM1 and PTM2, mapped to PLB address 0. */
177
178 out_le32((void *) &(pcip->ptm1la), 0x00000000);
179 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
180 out_le32((void *) &(pcip->ptm2la), 0x00000000);
181 out_le32((void *) &(pcip->ptm2ms), 0x00000001);
182
183 /* Write zero to PTM1 BAR. */
184
185 early_write_config_dword(hose, hose->first_busno,
186 PCI_FUNC(hose->first_busno),
187 PCI_BASE_ADDRESS_1,
188 0x00000000);
189
190 /* Disable PTM2 (unused) */
191
192 out_le32((void *) &(pcip->ptm2la), 0x00000000);
193 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
194
195 /* end work arround */
196 if (ppc_md.progress)
197 ppc_md.progress("bios_fixup(): done", 0x800);
198
199#ifdef DEBUG
200 printk("PCI bridge regs after fixup \n");
201 for (i = 0; i <= 2; i++) {
202 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
203 printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
204 printk(" pmm%dpcila\t0x%x\n", i,
205 in_le32(&(pcip->pmm[i].pcila)));
206 printk(" pmm%dpciha\t0x%x\n", i,
207 in_le32(&(pcip->pmm[i].pciha)));
208 }
209 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
210 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
211 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
212 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
213
214 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
215 early_read_config_dword(hose, hose->first_busno,
216 PCI_FUNC(hose->first_busno), bar,
217 &bar_response);
218 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
219 hose->first_busno, PCI_SLOT(hose->first_busno),
220 PCI_FUNC(hose->first_busno), bar, bar_response);
221 }
222
223
224#endif
225}
226
227void __init
228ash_map_io(void)
229{
230 ppc4xx_map_io();
231 io_block_mapping(ASH_RTC_VADDR, ASH_RTC_PADDR, ASH_RTC_SIZE, _PAGE_IO);
232}
233
234void __init
235platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
236 unsigned long r6, unsigned long r7)
237{
238 ppc4xx_init(r3, r4, r5, r6, r7);
239
240 ppc_md.setup_arch = ash_setup_arch;
241 ppc_md.setup_io_mappings = ash_map_io;
242
243#ifdef CONFIG_PPC_RTC
244 ppc_md.time_init = todc_time_init;
245 ppc_md.set_rtc_time = todc_set_rtc_time;
246 ppc_md.get_rtc_time = todc_get_rtc_time;
247 ppc_md.nvram_read_val = todc_direct_read_val;
248 ppc_md.nvram_write_val = todc_direct_write_val;
249#endif
250}
diff --git a/arch/ppc/platforms/4xx/ash.h b/arch/ppc/platforms/4xx/ash.h
deleted file mode 100644
index 5f7448ea418d..000000000000
--- a/arch/ppc/platforms/4xx/ash.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/ash.h
3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC
5 * Ash eval board.
6 *
7 * Author: Armin Kuster <akuster@mvista.com>
8 *
9 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_ASH_H__
17#define __ASM_ASH_H__
18#include <platforms/4xx/ibmnp405h.h>
19
20#ifndef __ASSEMBLY__
21/*
22 * Data structure defining board information maintained by the boot
23 * ROM on IBM's "Ash" evaluation board. An effort has been made to
24 * keep the field names consistent with the 8xx 'bd_t' board info
25 * structures.
26 */
27
28typedef struct board_info {
29 unsigned char bi_s_version[4]; /* Version of this structure */
30 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
31 unsigned int bi_memsize; /* DRAM installed, in bytes */
32 unsigned char bi_enetaddr[4][6]; /* Local Ethernet MAC address */
33 unsigned char bi_pci_enetaddr[6];
34 unsigned int bi_intfreq; /* Processor speed, in Hz */
35 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
36 unsigned int bi_pci_busfreq; /* PCI speed in Hz */
37} bd_t;
38
39/* Some 4xx parts use a different timebase frequency from the internal clock.
40*/
41#define bi_tbfreq bi_intfreq
42
43/* Memory map for the IBM "Ash" NP405H evaluation board.
44 */
45
46extern void *ash_rtc_base;
47#define ASH_RTC_PADDR ((uint)0xf0000000)
48#define ASH_RTC_VADDR ASH_RTC_PADDR
49#define ASH_RTC_SIZE ((uint)8*1024)
50
51
52/* Early initialization address mapping for block_io.
53 * Standard 405GP map.
54 */
55#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
56#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
57#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
58#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
59#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
60#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
61#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
62#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
63#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
64#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
65#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
66#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
67
68#define NR_BOARD_IRQS 32
69
70#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
71#define BASE_BAUD 201600
72#else
73#define BASE_BAUD 691200
74#endif
75
76#define PPC4xx_MACHINE_NAME "IBM NP405H Ash"
77
78extern char pci_irq_table[][4];
79
80
81#endif /* !__ASSEMBLY__ */
82#endif /* __ASM_ASH_H__ */
83#endif /* __KERNEL__ */
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