[PATCH] ppc32: Fix errata for some G3 CPUs

Some G3 CPUs can crash in funny way if a store from an FPU register
instruction is executed on a register that has never been initialized since
power on.  This patch fixes it by making sure all FP registers have been
properly initialized at kernel boot and when waking from sleep.  It also makes
the code that decides wether HID0_BTIC and HID0_DPM are allowed on a given CPU
smarter (it can actually _clear_ them now if they are not allowed instead of
just setting them when they are allowed in case the firmware got them wrong)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/ppc/platforms/pmac_sleep.S b/arch/ppc/platforms/pmac_sleep.S
index 3139b6766ad3..f459ade1bd63 100644
--- a/arch/ppc/platforms/pmac_sleep.S
+++ b/arch/ppc/platforms/pmac_sleep.S
@@ -267,6 +267,10 @@ grackle_wake_up:
         /* Restore various CPU config stuffs */
         bl      __restore_cpu_setup
 
+        /* Make sure all FPRs have been initialized */
+        bl      reloc_offset
+        bl      __init_fpu_registers
+
         /* Invalidate & enable L1 cache, we don't care about
          * whatever the ROM may have tried to write to memory
          */