diff options
author | Vitaly Bordug <vbordug@ru.mvista.com> | 2006-08-15 02:00:31 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2006-08-19 17:44:31 -0400 |
commit | 2ca2d5e84c19ddbc0126087af6288533a05f1799 (patch) | |
tree | 4d8014f576180e9a689dfcb9d405d412b19471ef /arch/ppc/platforms | |
parent | 5b4b8454344a0391bb0f69fda0f4ec8e1f0d2fed (diff) |
[PATCH] ppc32: board-specific part of fs_enet update
This contains board-specific portion to respect driver changes (for 8272ads ,
885ads and 866ads). Altered platform_data structures as well as initial setup
routines relevant to fs_enet.
Changes to the mpc8560ads ppc/ code are also introduced, but mainly as
reference, since the entire board support is going to appear in arch/powerpc.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r-- | arch/ppc/platforms/85xx/mpc8560_ads.c | 89 | ||||
-rw-r--r-- | arch/ppc/platforms/85xx/mpc85xx_ads_common.h | 19 | ||||
-rw-r--r-- | arch/ppc/platforms/mpc8272ads_setup.c | 154 | ||||
-rw-r--r-- | arch/ppc/platforms/mpc866ads_setup.c | 192 | ||||
-rw-r--r-- | arch/ppc/platforms/mpc885ads_setup.c | 175 | ||||
-rw-r--r-- | arch/ppc/platforms/pq2ads_pd.h | 82 |
6 files changed, 355 insertions, 356 deletions
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c index d90cd24d018e..94badafe4ef1 100644 --- a/arch/ppc/platforms/85xx/mpc8560_ads.c +++ b/arch/ppc/platforms/85xx/mpc8560_ads.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <linux/initrd.h> | 29 | #include <linux/initrd.h> |
30 | #include <linux/module.h> | 30 | #include <linux/module.h> |
31 | #include <linux/fsl_devices.h> | 31 | #include <linux/fsl_devices.h> |
32 | #include <linux/fs_enet_pd.h> | ||
32 | 33 | ||
33 | #include <asm/system.h> | 34 | #include <asm/system.h> |
34 | #include <asm/pgtable.h> | 35 | #include <asm/pgtable.h> |
@@ -58,6 +59,71 @@ | |||
58 | * Setup the architecture | 59 | * Setup the architecture |
59 | * | 60 | * |
60 | */ | 61 | */ |
62 | static void init_fcc_ioports(void) | ||
63 | { | ||
64 | struct immap *immap; | ||
65 | struct io_port *io; | ||
66 | u32 tempval; | ||
67 | |||
68 | immap = cpm2_immr; | ||
69 | |||
70 | io = &immap->im_ioport; | ||
71 | /* FCC2/3 are on the ports B/C. */ | ||
72 | tempval = in_be32(&io->iop_pdirb); | ||
73 | tempval &= ~PB2_DIRB0; | ||
74 | tempval |= PB2_DIRB1; | ||
75 | out_be32(&io->iop_pdirb, tempval); | ||
76 | |||
77 | tempval = in_be32(&io->iop_psorb); | ||
78 | tempval &= ~PB2_PSORB0; | ||
79 | tempval |= PB2_PSORB1; | ||
80 | out_be32(&io->iop_psorb, tempval); | ||
81 | |||
82 | tempval = in_be32(&io->iop_pparb); | ||
83 | tempval |= (PB2_DIRB0 | PB2_DIRB1); | ||
84 | out_be32(&io->iop_pparb, tempval); | ||
85 | |||
86 | tempval = in_be32(&io->iop_pdirb); | ||
87 | tempval &= ~PB3_DIRB0; | ||
88 | tempval |= PB3_DIRB1; | ||
89 | out_be32(&io->iop_pdirb, tempval); | ||
90 | |||
91 | tempval = in_be32(&io->iop_psorb); | ||
92 | tempval &= ~PB3_PSORB0; | ||
93 | tempval |= PB3_PSORB1; | ||
94 | out_be32(&io->iop_psorb, tempval); | ||
95 | |||
96 | tempval = in_be32(&io->iop_pparb); | ||
97 | tempval |= (PB3_DIRB0 | PB3_DIRB1); | ||
98 | out_be32(&io->iop_pparb, tempval); | ||
99 | |||
100 | tempval = in_be32(&io->iop_pdirc); | ||
101 | tempval |= PC3_DIRC1; | ||
102 | out_be32(&io->iop_pdirc, tempval); | ||
103 | |||
104 | tempval = in_be32(&io->iop_pparc); | ||
105 | tempval |= PC3_DIRC1; | ||
106 | out_be32(&io->iop_pparc, tempval); | ||
107 | |||
108 | /* Port C has clocks...... */ | ||
109 | tempval = in_be32(&io->iop_psorc); | ||
110 | tempval &= ~(CLK_TRX); | ||
111 | out_be32(&io->iop_psorc, tempval); | ||
112 | |||
113 | tempval = in_be32(&io->iop_pdirc); | ||
114 | tempval &= ~(CLK_TRX); | ||
115 | out_be32(&io->iop_pdirc, tempval); | ||
116 | tempval = in_be32(&io->iop_pparc); | ||
117 | tempval |= (CLK_TRX); | ||
118 | out_be32(&io->iop_pparc, tempval); | ||
119 | |||
120 | /* Configure Serial Interface clock routing. | ||
121 | * First, clear all FCC bits to zero, | ||
122 | * then set the ones we want. | ||
123 | */ | ||
124 | immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK); | ||
125 | immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE; | ||
126 | } | ||
61 | 127 | ||
62 | static void __init | 128 | static void __init |
63 | mpc8560ads_setup_arch(void) | 129 | mpc8560ads_setup_arch(void) |
@@ -66,6 +132,7 @@ mpc8560ads_setup_arch(void) | |||
66 | unsigned int freq; | 132 | unsigned int freq; |
67 | struct gianfar_platform_data *pdata; | 133 | struct gianfar_platform_data *pdata; |
68 | struct gianfar_mdio_data *mdata; | 134 | struct gianfar_mdio_data *mdata; |
135 | struct fs_platform_info *fpi; | ||
69 | 136 | ||
70 | cpm2_reset(); | 137 | cpm2_reset(); |
71 | 138 | ||
@@ -110,6 +177,28 @@ mpc8560ads_setup_arch(void) | |||
110 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); | 177 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); |
111 | } | 178 | } |
112 | 179 | ||
180 | init_fcc_ioports(); | ||
181 | ppc_sys_device_remove(MPC85xx_CPM_FCC1); | ||
182 | |||
183 | fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2); | ||
184 | if (fpi) { | ||
185 | memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); | ||
186 | fpi->bus_id = "0:02"; | ||
187 | fpi->phy_addr = 2; | ||
188 | fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; | ||
189 | fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1]; | ||
190 | } | ||
191 | |||
192 | fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3); | ||
193 | if (fpi) { | ||
194 | memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); | ||
195 | fpi->macaddr[5] += 1; | ||
196 | fpi->bus_id = "0:03"; | ||
197 | fpi->phy_addr = 3; | ||
198 | fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; | ||
199 | fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2]; | ||
200 | } | ||
201 | |||
113 | #ifdef CONFIG_BLK_DEV_INITRD | 202 | #ifdef CONFIG_BLK_DEV_INITRD |
114 | if (initrd_start) | 203 | if (initrd_start) |
115 | ROOT_DEV = Root_RAM0; | 204 | ROOT_DEV = Root_RAM0; |
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h index abf32281655d..c8c322fe3680 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h +++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h | |||
@@ -45,4 +45,23 @@ extern void mpc85xx_ads_map_io(void) __init; | |||
45 | 45 | ||
46 | #define MPC85XX_PCI1_IO_SIZE 0x01000000 | 46 | #define MPC85XX_PCI1_IO_SIZE 0x01000000 |
47 | 47 | ||
48 | /* FCC1 Clock Source Configuration. These can be | ||
49 | * redefined in the board specific file. | ||
50 | * Can only choose from CLK9-12 */ | ||
51 | #define F1_RXCLK 12 | ||
52 | #define F1_TXCLK 11 | ||
53 | |||
54 | /* FCC2 Clock Source Configuration. These can be | ||
55 | * redefined in the board specific file. | ||
56 | * Can only choose from CLK13-16 */ | ||
57 | #define F2_RXCLK 13 | ||
58 | #define F2_TXCLK 14 | ||
59 | |||
60 | /* FCC3 Clock Source Configuration. These can be | ||
61 | * redefined in the board specific file. | ||
62 | * Can only choose from CLK13-16 */ | ||
63 | #define F3_RXCLK 15 | ||
64 | #define F3_TXCLK 16 | ||
65 | |||
66 | |||
48 | #endif /* __MACH_MPC85XX_ADS_H__ */ | 67 | #endif /* __MACH_MPC85XX_ADS_H__ */ |
diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c index abb7154de2c7..2a35fe2b9b96 100644 --- a/arch/ppc/platforms/mpc8272ads_setup.c +++ b/arch/ppc/platforms/mpc8272ads_setup.c | |||
@@ -56,64 +56,51 @@ static struct fs_uart_platform_info mpc8272_uart_pdata[] = { | |||
56 | }, | 56 | }, |
57 | }; | 57 | }; |
58 | 58 | ||
59 | static struct fs_mii_bus_info mii_bus_info = { | 59 | static struct fs_mii_bb_platform_info m82xx_mii_bb_pdata = { |
60 | .method = fsmii_bitbang, | 60 | .mdio_dat.bit = 18, |
61 | .id = 0, | 61 | .mdio_dir.bit = 18, |
62 | .i.bitbang = { | 62 | .mdc_dat.bit = 19, |
63 | .mdio_port = fsiop_portc, | 63 | .delay = 1, |
64 | .mdio_bit = 18, | ||
65 | .mdc_port = fsiop_portc, | ||
66 | .mdc_bit = 19, | ||
67 | .delay = 1, | ||
68 | }, | ||
69 | }; | ||
70 | |||
71 | static struct fs_platform_info mpc82xx_fcc1_pdata = { | ||
72 | .fs_no = fsid_fcc1, | ||
73 | .cp_page = CPM_CR_FCC1_PAGE, | ||
74 | .cp_block = CPM_CR_FCC1_SBLOCK, | ||
75 | .clk_trx = (PC_F1RXCLK | PC_F1TXCLK), | ||
76 | .clk_route = CMX1_CLK_ROUTE, | ||
77 | .clk_mask = CMX1_CLK_MASK, | ||
78 | .init_ioports = init_fcc1_ioports, | ||
79 | |||
80 | .phy_addr = 0, | ||
81 | #ifdef PHY_INTERRUPT | ||
82 | .phy_irq = PHY_INTERRUPT, | ||
83 | #else | ||
84 | .phy_irq = -1; | ||
85 | #endif | ||
86 | .mem_offset = FCC1_MEM_OFFSET, | ||
87 | .bus_info = &mii_bus_info, | ||
88 | .rx_ring = 32, | ||
89 | .tx_ring = 32, | ||
90 | .rx_copybreak = 240, | ||
91 | .use_napi = 0, | ||
92 | .napi_weight = 17, | ||
93 | }; | 64 | }; |
94 | 65 | ||
95 | static struct fs_platform_info mpc82xx_fcc2_pdata = { | 66 | static struct fs_platform_info mpc82xx_enet_pdata[] = { |
96 | .fs_no = fsid_fcc2, | 67 | [fsid_fcc1] = { |
97 | .cp_page = CPM_CR_FCC2_PAGE, | 68 | .fs_no = fsid_fcc1, |
98 | .cp_block = CPM_CR_FCC2_SBLOCK, | 69 | .cp_page = CPM_CR_FCC1_PAGE, |
99 | .clk_trx = (PC_F2RXCLK | PC_F2TXCLK), | 70 | .cp_block = CPM_CR_FCC1_SBLOCK, |
100 | .clk_route = CMX2_CLK_ROUTE, | 71 | |
101 | .clk_mask = CMX2_CLK_MASK, | 72 | .clk_trx = (PC_F1RXCLK | PC_F1TXCLK), |
102 | .init_ioports = init_fcc2_ioports, | 73 | .clk_route = CMX1_CLK_ROUTE, |
103 | 74 | .clk_mask = CMX1_CLK_MASK, | |
104 | .phy_addr = 3, | 75 | .init_ioports = init_fcc1_ioports, |
105 | #ifdef PHY_INTERRUPT | 76 | |
106 | .phy_irq = PHY_INTERRUPT, | 77 | .mem_offset = FCC1_MEM_OFFSET, |
107 | #else | 78 | |
108 | .phy_irq = -1; | 79 | .rx_ring = 32, |
109 | #endif | 80 | .tx_ring = 32, |
110 | .mem_offset = FCC2_MEM_OFFSET, | 81 | .rx_copybreak = 240, |
111 | .bus_info = &mii_bus_info, | 82 | .use_napi = 0, |
112 | .rx_ring = 32, | 83 | .napi_weight = 17, |
113 | .tx_ring = 32, | 84 | .bus_id = "0:00", |
114 | .rx_copybreak = 240, | 85 | }, |
115 | .use_napi = 0, | 86 | [fsid_fcc2] = { |
116 | .napi_weight = 17, | 87 | .fs_no = fsid_fcc2, |
88 | .cp_page = CPM_CR_FCC2_PAGE, | ||
89 | .cp_block = CPM_CR_FCC2_SBLOCK, | ||
90 | .clk_trx = (PC_F2RXCLK | PC_F2TXCLK), | ||
91 | .clk_route = CMX2_CLK_ROUTE, | ||
92 | .clk_mask = CMX2_CLK_MASK, | ||
93 | .init_ioports = init_fcc2_ioports, | ||
94 | |||
95 | .mem_offset = FCC2_MEM_OFFSET, | ||
96 | |||
97 | .rx_ring = 32, | ||
98 | .tx_ring = 32, | ||
99 | .rx_copybreak = 240, | ||
100 | .use_napi = 0, | ||
101 | .napi_weight = 17, | ||
102 | .bus_id = "0:03", | ||
103 | }, | ||
117 | }; | 104 | }; |
118 | 105 | ||
119 | static void init_fcc1_ioports(void) | 106 | static void init_fcc1_ioports(void) |
@@ -209,20 +196,21 @@ static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev, | |||
209 | bd_t* bi = (void*)__res; | 196 | bd_t* bi = (void*)__res; |
210 | int fs_no = fsid_fcc1+pdev->id-1; | 197 | int fs_no = fsid_fcc1+pdev->id-1; |
211 | 198 | ||
212 | mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase; | 199 | if(fs_no > ARRAY_SIZE(mpc82xx_enet_pdata)) { |
213 | mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c; | 200 | return; |
214 | |||
215 | switch(fs_no) { | ||
216 | case fsid_fcc1: | ||
217 | memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6); | ||
218 | pdev->dev.platform_data = &mpc82xx_fcc1_pdata; | ||
219 | break; | ||
220 | case fsid_fcc2: | ||
221 | memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6); | ||
222 | mpc82xx_fcc2_pdata.macaddr[5] ^= 1; | ||
223 | pdev->dev.platform_data = &mpc82xx_fcc2_pdata; | ||
224 | break; | ||
225 | } | 201 | } |
202 | |||
203 | mpc82xx_enet_pdata[fs_no].dpram_offset= | ||
204 | (u32)cpm2_immr->im_dprambase; | ||
205 | mpc82xx_enet_pdata[fs_no].fcc_regs_c = | ||
206 | (u32)cpm2_immr->im_fcc_c; | ||
207 | memcpy(&mpc82xx_enet_pdata[fs_no].macaddr,bi->bi_enetaddr,6); | ||
208 | |||
209 | /* prevent dup mac */ | ||
210 | if(fs_no == fsid_fcc2) | ||
211 | mpc82xx_enet_pdata[fs_no].macaddr[5] ^= 1; | ||
212 | |||
213 | pdev->dev.platform_data = &mpc82xx_enet_pdata[fs_no]; | ||
226 | } | 214 | } |
227 | 215 | ||
228 | static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev, | 216 | static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev, |
@@ -274,6 +262,29 @@ static void init_scc4_uart_ioports(void) | |||
274 | iounmap(immap); | 262 | iounmap(immap); |
275 | } | 263 | } |
276 | 264 | ||
265 | static void __init mpc8272ads_fixup_mdio_pdata(struct platform_device *pdev, | ||
266 | int idx) | ||
267 | { | ||
268 | m82xx_mii_bb_pdata.irq[0] = PHY_INTERRUPT; | ||
269 | m82xx_mii_bb_pdata.irq[1] = -1; | ||
270 | m82xx_mii_bb_pdata.irq[2] = -1; | ||
271 | m82xx_mii_bb_pdata.irq[3] = PHY_INTERRUPT; | ||
272 | m82xx_mii_bb_pdata.irq[31] = -1; | ||
273 | |||
274 | |||
275 | m82xx_mii_bb_pdata.mdio_dat.offset = | ||
276 | (u32)&cpm2_immr->im_ioport.iop_pdatc; | ||
277 | |||
278 | m82xx_mii_bb_pdata.mdio_dir.offset = | ||
279 | (u32)&cpm2_immr->im_ioport.iop_pdirc; | ||
280 | |||
281 | m82xx_mii_bb_pdata.mdc_dat.offset = | ||
282 | (u32)&cpm2_immr->im_ioport.iop_pdatc; | ||
283 | |||
284 | |||
285 | pdev->dev.platform_data = &m82xx_mii_bb_pdata; | ||
286 | } | ||
287 | |||
277 | static int mpc8272ads_platform_notify(struct device *dev) | 288 | static int mpc8272ads_platform_notify(struct device *dev) |
278 | { | 289 | { |
279 | static const struct platform_notify_dev_map dev_map[] = { | 290 | static const struct platform_notify_dev_map dev_map[] = { |
@@ -286,6 +297,10 @@ static int mpc8272ads_platform_notify(struct device *dev) | |||
286 | .rtn = mpc8272ads_fixup_uart_pdata, | 297 | .rtn = mpc8272ads_fixup_uart_pdata, |
287 | }, | 298 | }, |
288 | { | 299 | { |
300 | .bus_id = "fsl-bb-mdio", | ||
301 | .rtn = mpc8272ads_fixup_mdio_pdata, | ||
302 | }, | ||
303 | { | ||
289 | .bus_id = NULL | 304 | .bus_id = NULL |
290 | } | 305 | } |
291 | }; | 306 | }; |
@@ -319,6 +334,7 @@ int __init mpc8272ads_init(void) | |||
319 | ppc_sys_device_enable(MPC82xx_CPM_SCC4); | 334 | ppc_sys_device_enable(MPC82xx_CPM_SCC4); |
320 | #endif | 335 | #endif |
321 | 336 | ||
337 | ppc_sys_device_enable(MPC82xx_MDIO_BB); | ||
322 | 338 | ||
323 | return 0; | 339 | return 0; |
324 | } | 340 | } |
diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c index f19b6167c770..e12cece4c9fd 100644 --- a/arch/ppc/platforms/mpc866ads_setup.c +++ b/arch/ppc/platforms/mpc866ads_setup.c | |||
@@ -1,10 +1,10 @@ | |||
1 | /*arch/ppc/platforms/mpc885ads-setup.c | 1 | /*arch/ppc/platforms/mpc866ads-setup.c |
2 | * | 2 | * |
3 | * Platform setup for the Freescale mpc885ads board | 3 | * Platform setup for the Freescale mpc866ads board |
4 | * | 4 | * |
5 | * Vitaly Bordug <vbordug@ru.mvista.com> | 5 | * Vitaly Bordug <vbordug@ru.mvista.com> |
6 | * | 6 | * |
7 | * Copyright 2005 MontaVista Software Inc. | 7 | * Copyright 2005-2006 MontaVista Software Inc. |
8 | * | 8 | * |
9 | * This file is licensed under the terms of the GNU General Public License | 9 | * This file is licensed under the terms of the GNU General Public License |
10 | * version 2. This program is licensed "as is" without any warranty of any | 10 | * version 2. This program is licensed "as is" without any warranty of any |
@@ -42,49 +42,36 @@ static void setup_scc1_ioports(void); | |||
42 | static void setup_smc1_ioports(void); | 42 | static void setup_smc1_ioports(void); |
43 | static void setup_smc2_ioports(void); | 43 | static void setup_smc2_ioports(void); |
44 | 44 | ||
45 | static struct fs_mii_bus_info fec_mii_bus_info = { | 45 | static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata; |
46 | .method = fsmii_fec, | ||
47 | .id = 0, | ||
48 | }; | ||
49 | |||
50 | static struct fs_mii_bus_info scc_mii_bus_info = { | ||
51 | .method = fsmii_fixed, | ||
52 | .id = 0, | ||
53 | .i.fixed.speed = 10, | ||
54 | .i.fixed.duplex = 0, | ||
55 | }; | ||
56 | 46 | ||
57 | static struct fs_platform_info mpc8xx_fec_pdata[] = { | 47 | static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata; |
58 | { | ||
59 | .rx_ring = 128, | ||
60 | .tx_ring = 16, | ||
61 | .rx_copybreak = 240, | ||
62 | 48 | ||
63 | .use_napi = 1, | 49 | static struct fs_platform_info mpc8xx_enet_pdata[] = { |
64 | .napi_weight = 17, | 50 | [fsid_fec1] = { |
51 | .rx_ring = 128, | ||
52 | .tx_ring = 16, | ||
53 | .rx_copybreak = 240, | ||
65 | 54 | ||
66 | .phy_addr = 15, | 55 | .use_napi = 1, |
67 | .phy_irq = -1, | 56 | .napi_weight = 17, |
68 | 57 | ||
69 | .use_rmii = 0, | 58 | .init_ioports = setup_fec1_ioports, |
70 | 59 | ||
71 | .bus_info = &fec_mii_bus_info, | 60 | .bus_id = "0:0f", |
72 | } | 61 | .has_phy = 1, |
73 | }; | 62 | }, |
63 | [fsid_scc1] = { | ||
64 | .rx_ring = 64, | ||
65 | .tx_ring = 8, | ||
66 | .rx_copybreak = 240, | ||
67 | .use_napi = 1, | ||
68 | .napi_weight = 17, | ||
74 | 69 | ||
75 | static struct fs_platform_info mpc8xx_scc_pdata = { | ||
76 | .rx_ring = 64, | ||
77 | .tx_ring = 8, | ||
78 | .rx_copybreak = 240, | ||
79 | 70 | ||
80 | .use_napi = 1, | 71 | .init_ioports = setup_scc1_ioports, |
81 | .napi_weight = 17, | ||
82 | |||
83 | .phy_addr = -1, | ||
84 | .phy_irq = -1, | ||
85 | |||
86 | .bus_info = &scc_mii_bus_info, | ||
87 | 72 | ||
73 | .bus_id = "fixed@100:1", | ||
74 | }, | ||
88 | }; | 75 | }; |
89 | 76 | ||
90 | static struct fs_uart_platform_info mpc866_uart_pdata[] = { | 77 | static struct fs_uart_platform_info mpc866_uart_pdata[] = { |
@@ -207,63 +194,6 @@ static void setup_scc1_ioports(void) | |||
207 | 194 | ||
208 | } | 195 | } |
209 | 196 | ||
210 | static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) | ||
211 | { | ||
212 | struct fs_platform_info *fpi = pdev->dev.platform_data; | ||
213 | |||
214 | volatile cpm8xx_t *cp; | ||
215 | bd_t *bd = (bd_t *) __res; | ||
216 | char *e; | ||
217 | int i; | ||
218 | |||
219 | /* Get pointer to Communication Processor */ | ||
220 | cp = cpmp; | ||
221 | switch (fs_no) { | ||
222 | case fsid_fec1: | ||
223 | fpi = &mpc8xx_fec_pdata[0]; | ||
224 | fpi->init_ioports = &setup_fec1_ioports; | ||
225 | |||
226 | break; | ||
227 | case fsid_scc1: | ||
228 | fpi = &mpc8xx_scc_pdata; | ||
229 | fpi->init_ioports = &setup_scc1_ioports; | ||
230 | |||
231 | break; | ||
232 | default: | ||
233 | printk(KERN_WARNING"Device %s is not supported!\n", pdev->name); | ||
234 | return; | ||
235 | } | ||
236 | |||
237 | pdev->dev.platform_data = fpi; | ||
238 | fpi->fs_no = fs_no; | ||
239 | |||
240 | e = (unsigned char *)&bd->bi_enetaddr; | ||
241 | for (i = 0; i < 6; i++) | ||
242 | fpi->macaddr[i] = *e++; | ||
243 | |||
244 | fpi->macaddr[5 - pdev->id]++; | ||
245 | |||
246 | } | ||
247 | |||
248 | static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev, | ||
249 | int idx) | ||
250 | { | ||
251 | /* This is for FEC devices only */ | ||
252 | if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec"))) | ||
253 | return; | ||
254 | mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1); | ||
255 | } | ||
256 | |||
257 | static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev, | ||
258 | int idx) | ||
259 | { | ||
260 | /* This is for SCC devices only */ | ||
261 | if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc"))) | ||
262 | return; | ||
263 | |||
264 | mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); | ||
265 | } | ||
266 | |||
267 | static void setup_smc1_ioports(void) | 197 | static void setup_smc1_ioports(void) |
268 | { | 198 | { |
269 | immap_t *immap = (immap_t *) IMAP_ADDR; | 199 | immap_t *immap = (immap_t *) IMAP_ADDR; |
@@ -315,6 +245,56 @@ static void setup_smc2_ioports(void) | |||
315 | 245 | ||
316 | } | 246 | } |
317 | 247 | ||
248 | static int ma_count = 0; | ||
249 | |||
250 | static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) | ||
251 | { | ||
252 | struct fs_platform_info *fpi; | ||
253 | |||
254 | volatile cpm8xx_t *cp; | ||
255 | bd_t *bd = (bd_t *) __res; | ||
256 | char *e; | ||
257 | int i; | ||
258 | |||
259 | /* Get pointer to Communication Processor */ | ||
260 | cp = cpmp; | ||
261 | |||
262 | if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) { | ||
263 | printk(KERN_ERR"No network-suitable #%d device on bus", fs_no); | ||
264 | return; | ||
265 | } | ||
266 | |||
267 | |||
268 | fpi = &mpc8xx_enet_pdata[fs_no]; | ||
269 | fpi->fs_no = fs_no; | ||
270 | pdev->dev.platform_data = fpi; | ||
271 | |||
272 | e = (unsigned char *)&bd->bi_enetaddr; | ||
273 | for (i = 0; i < 6; i++) | ||
274 | fpi->macaddr[i] = *e++; | ||
275 | |||
276 | fpi->macaddr[5] += ma_count++; | ||
277 | } | ||
278 | |||
279 | static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev, | ||
280 | int idx) | ||
281 | { | ||
282 | /* This is for FEC devices only */ | ||
283 | if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec"))) | ||
284 | return; | ||
285 | mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1); | ||
286 | } | ||
287 | |||
288 | static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev, | ||
289 | int idx) | ||
290 | { | ||
291 | /* This is for SCC devices only */ | ||
292 | if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc"))) | ||
293 | return; | ||
294 | |||
295 | mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); | ||
296 | } | ||
297 | |||
318 | static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev, | 298 | static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev, |
319 | int idx) | 299 | int idx) |
320 | { | 300 | { |
@@ -359,6 +339,9 @@ static int mpc866ads_platform_notify(struct device *dev) | |||
359 | 339 | ||
360 | int __init mpc866ads_init(void) | 340 | int __init mpc866ads_init(void) |
361 | { | 341 | { |
342 | bd_t *bd = (bd_t *) __res; | ||
343 | struct fs_mii_fec_platform_info* fmpi; | ||
344 | |||
362 | printk(KERN_NOTICE "mpc866ads: Init\n"); | 345 | printk(KERN_NOTICE "mpc866ads: Init\n"); |
363 | 346 | ||
364 | platform_notify = mpc866ads_platform_notify; | 347 | platform_notify = mpc866ads_platform_notify; |
@@ -366,11 +349,20 @@ int __init mpc866ads_init(void) | |||
366 | ppc_sys_device_initfunc(); | 349 | ppc_sys_device_initfunc(); |
367 | ppc_sys_device_disable_all(); | 350 | ppc_sys_device_disable_all(); |
368 | 351 | ||
369 | #ifdef MPC8xx_SECOND_ETH_SCC1 | 352 | #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC1 |
370 | ppc_sys_device_enable(MPC8xx_CPM_SCC1); | 353 | ppc_sys_device_enable(MPC8xx_CPM_SCC1); |
371 | #endif | 354 | #endif |
372 | ppc_sys_device_enable(MPC8xx_CPM_FEC1); | 355 | ppc_sys_device_enable(MPC8xx_CPM_FEC1); |
373 | 356 | ||
357 | ppc_sys_device_enable(MPC8xx_MDIO_FEC); | ||
358 | |||
359 | fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data = | ||
360 | &mpc8xx_mdio_fec_pdata; | ||
361 | |||
362 | fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1; | ||
363 | /* No PHY interrupt line here */ | ||
364 | fmpi->irq[0xf] = -1; | ||
365 | |||
374 | /* Since either of the uarts could be used as console, they need to ready */ | 366 | /* Since either of the uarts could be used as console, they need to ready */ |
375 | #ifdef CONFIG_SERIAL_CPM_SMC1 | 367 | #ifdef CONFIG_SERIAL_CPM_SMC1 |
376 | ppc_sys_device_enable(MPC8xx_CPM_SMC1); | 368 | ppc_sys_device_enable(MPC8xx_CPM_SMC1); |
@@ -381,6 +373,14 @@ int __init mpc866ads_init(void) | |||
381 | ppc_sys_device_enable(MPC8xx_CPM_SMC2); | 373 | ppc_sys_device_enable(MPC8xx_CPM_SMC2); |
382 | ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART); | 374 | ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART); |
383 | #endif | 375 | #endif |
376 | ppc_sys_device_enable(MPC8xx_MDIO_FEC); | ||
377 | |||
378 | fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data = | ||
379 | &mpc8xx_mdio_fec_pdata; | ||
380 | |||
381 | fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1; | ||
382 | /* No PHY interrupt line here */ | ||
383 | fmpi->irq[0xf] = -1; | ||
384 | 384 | ||
385 | return 0; | 385 | return 0; |
386 | } | 386 | } |
diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c index c1fc4a16fea9..5dfa4e6c2af0 100644 --- a/arch/ppc/platforms/mpc885ads_setup.c +++ b/arch/ppc/platforms/mpc885ads_setup.c | |||
@@ -38,7 +38,10 @@ extern unsigned char __res[]; | |||
38 | static void setup_smc1_ioports(void); | 38 | static void setup_smc1_ioports(void); |
39 | static void setup_smc2_ioports(void); | 39 | static void setup_smc2_ioports(void); |
40 | 40 | ||
41 | static void __init mpc885ads_scc_phy_init(char); | 41 | static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata; |
42 | static void setup_fec1_ioports(void); | ||
43 | static void setup_fec2_ioports(void); | ||
44 | static void setup_scc3_ioports(void); | ||
42 | 45 | ||
43 | static struct fs_uart_platform_info mpc885_uart_pdata[] = { | 46 | static struct fs_uart_platform_info mpc885_uart_pdata[] = { |
44 | [fsid_smc1_uart] = { | 47 | [fsid_smc1_uart] = { |
@@ -61,23 +64,8 @@ static struct fs_uart_platform_info mpc885_uart_pdata[] = { | |||
61 | }, | 64 | }, |
62 | }; | 65 | }; |
63 | 66 | ||
64 | static struct fs_mii_bus_info fec_mii_bus_info = { | 67 | static struct fs_platform_info mpc8xx_enet_pdata[] = { |
65 | .method = fsmii_fec, | 68 | [fsid_fec1] = { |
66 | .id = 0, | ||
67 | }; | ||
68 | |||
69 | static struct fs_mii_bus_info scc_mii_bus_info = { | ||
70 | #ifdef CONFIG_SCC_ENET_8xx_FIXED | ||
71 | .method = fsmii_fixed, | ||
72 | #else | ||
73 | .method = fsmii_fec, | ||
74 | #endif | ||
75 | |||
76 | .id = 0, | ||
77 | }; | ||
78 | |||
79 | static struct fs_platform_info mpc8xx_fec_pdata[] = { | ||
80 | { | ||
81 | .rx_ring = 128, | 69 | .rx_ring = 128, |
82 | .tx_ring = 16, | 70 | .tx_ring = 16, |
83 | .rx_copybreak = 240, | 71 | .rx_copybreak = 240, |
@@ -85,11 +73,12 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = { | |||
85 | .use_napi = 1, | 73 | .use_napi = 1, |
86 | .napi_weight = 17, | 74 | .napi_weight = 17, |
87 | 75 | ||
88 | .phy_addr = 0, | 76 | .init_ioports = setup_fec1_ioports, |
89 | .phy_irq = SIU_IRQ7, | ||
90 | 77 | ||
91 | .bus_info = &fec_mii_bus_info, | 78 | .bus_id = "0:00", |
92 | }, { | 79 | .has_phy = 1, |
80 | }, | ||
81 | [fsid_fec2] = { | ||
93 | .rx_ring = 128, | 82 | .rx_ring = 128, |
94 | .tx_ring = 16, | 83 | .tx_ring = 16, |
95 | .rx_copybreak = 240, | 84 | .rx_copybreak = 240, |
@@ -97,35 +86,32 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = { | |||
97 | .use_napi = 1, | 86 | .use_napi = 1, |
98 | .napi_weight = 17, | 87 | .napi_weight = 17, |
99 | 88 | ||
100 | .phy_addr = 1, | 89 | .init_ioports = setup_fec2_ioports, |
101 | .phy_irq = SIU_IRQ7, | ||
102 | |||
103 | .bus_info = &fec_mii_bus_info, | ||
104 | } | ||
105 | }; | ||
106 | 90 | ||
107 | static struct fs_platform_info mpc8xx_scc_pdata = { | 91 | .bus_id = "0:01", |
108 | .rx_ring = 64, | 92 | .has_phy = 1, |
109 | .tx_ring = 8, | 93 | }, |
110 | .rx_copybreak = 240, | 94 | [fsid_scc3] = { |
95 | .rx_ring = 64, | ||
96 | .tx_ring = 8, | ||
97 | .rx_copybreak = 240, | ||
111 | 98 | ||
112 | .use_napi = 1, | 99 | .use_napi = 1, |
113 | .napi_weight = 17, | 100 | .napi_weight = 17, |
114 | 101 | ||
115 | .phy_addr = 2, | 102 | .init_ioports = setup_scc3_ioports, |
116 | #ifdef CONFIG_MPC8xx_SCC_ENET_FIXED | 103 | #ifdef CONFIG_FIXED_MII_10_FDX |
117 | .phy_irq = -1, | 104 | .bus_id = "fixed@100:1", |
118 | #else | 105 | #else |
119 | .phy_irq = SIU_IRQ7, | 106 | .bus_id = "0:02", |
120 | #endif | 107 | #endif |
121 | 108 | }, | |
122 | .bus_info = &scc_mii_bus_info, | ||
123 | }; | 109 | }; |
124 | 110 | ||
125 | void __init board_init(void) | 111 | void __init board_init(void) |
126 | { | 112 | { |
127 | volatile cpm8xx_t *cp = cpmp; | 113 | cpm8xx_t *cp = cpmp; |
128 | unsigned int *bcsr_io; | 114 | unsigned int *bcsr_io; |
129 | 115 | ||
130 | #ifdef CONFIG_FS_ENET | 116 | #ifdef CONFIG_FS_ENET |
131 | immap_t *immap = (immap_t *) IMAP_ADDR; | 117 | immap_t *immap = (immap_t *) IMAP_ADDR; |
@@ -164,6 +150,14 @@ void __init board_init(void) | |||
164 | /* use MDC for MII (common) */ | 150 | /* use MDC for MII (common) */ |
165 | setbits16(&immap->im_ioport.iop_pdpar, 0x0080); | 151 | setbits16(&immap->im_ioport.iop_pdpar, 0x0080); |
166 | clrbits16(&immap->im_ioport.iop_pddir, 0x0080); | 152 | clrbits16(&immap->im_ioport.iop_pddir, 0x0080); |
153 | bcsr_io = ioremap(BCSR5, sizeof(unsigned long)); | ||
154 | clrbits32(bcsr_io,BCSR5_MII1_EN); | ||
155 | clrbits32(bcsr_io,BCSR5_MII1_RST); | ||
156 | #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 | ||
157 | clrbits32(bcsr_io,BCSR5_MII2_EN); | ||
158 | clrbits32(bcsr_io,BCSR5_MII2_RST); | ||
159 | #endif | ||
160 | iounmap(bcsr_io); | ||
167 | #endif | 161 | #endif |
168 | } | 162 | } |
169 | 163 | ||
@@ -194,8 +188,8 @@ static void setup_fec2_ioports(void) | |||
194 | /* configure FEC2 pins */ | 188 | /* configure FEC2 pins */ |
195 | setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc); | 189 | setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc); |
196 | setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc); | 190 | setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc); |
197 | setbits32(&immap->im_cpm.cp_peso, 0x00037800); | ||
198 | clrbits32(&immap->im_cpm.cp_peso, 0x000087fc); | 191 | clrbits32(&immap->im_cpm.cp_peso, 0x000087fc); |
192 | setbits32(&immap->im_cpm.cp_peso, 0x00037800); | ||
199 | clrbits32(&immap->im_cpm.cp_cptr, 0x00000080); | 193 | clrbits32(&immap->im_cpm.cp_cptr, 0x00000080); |
200 | } | 194 | } |
201 | 195 | ||
@@ -213,6 +207,8 @@ static void setup_scc3_ioports(void) | |||
213 | 207 | ||
214 | /* Enable the PHY. | 208 | /* Enable the PHY. |
215 | */ | 209 | */ |
210 | clrbits32(bcsr_io+4, BCSR4_ETH10_RST); | ||
211 | udelay(1000); | ||
216 | setbits32(bcsr_io+4, BCSR4_ETH10_RST); | 212 | setbits32(bcsr_io+4, BCSR4_ETH10_RST); |
217 | /* Configure port A pins for Txd and Rxd. | 213 | /* Configure port A pins for Txd and Rxd. |
218 | */ | 214 | */ |
@@ -254,37 +250,38 @@ static void setup_scc3_ioports(void) | |||
254 | clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA); | 250 | clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA); |
255 | setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA); | 251 | setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA); |
256 | 252 | ||
257 | setbits32(bcsr_io+1, BCSR1_ETHEN); | 253 | setbits32(bcsr_io+4, BCSR1_ETHEN); |
258 | iounmap(bcsr_io); | 254 | iounmap(bcsr_io); |
259 | } | 255 | } |
260 | 256 | ||
257 | static int mac_count = 0; | ||
258 | |||
261 | static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) | 259 | static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) |
262 | { | 260 | { |
263 | struct fs_platform_info *fpi = pdev->dev.platform_data; | 261 | struct fs_platform_info *fpi; |
264 | |||
265 | volatile cpm8xx_t *cp; | ||
266 | bd_t *bd = (bd_t *) __res; | 262 | bd_t *bd = (bd_t *) __res; |
267 | char *e; | 263 | char *e; |
268 | int i; | 264 | int i; |
269 | 265 | ||
270 | /* Get pointer to Communication Processor */ | 266 | if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) { |
271 | cp = cpmp; | 267 | printk(KERN_ERR"No network-suitable #%d device on bus", fs_no); |
268 | return; | ||
269 | } | ||
270 | |||
271 | fpi = &mpc8xx_enet_pdata[fs_no]; | ||
272 | |||
272 | switch (fs_no) { | 273 | switch (fs_no) { |
273 | case fsid_fec1: | 274 | case fsid_fec1: |
274 | fpi = &mpc8xx_fec_pdata[0]; | ||
275 | fpi->init_ioports = &setup_fec1_ioports; | 275 | fpi->init_ioports = &setup_fec1_ioports; |
276 | break; | 276 | break; |
277 | case fsid_fec2: | 277 | case fsid_fec2: |
278 | fpi = &mpc8xx_fec_pdata[1]; | ||
279 | fpi->init_ioports = &setup_fec2_ioports; | 278 | fpi->init_ioports = &setup_fec2_ioports; |
280 | break; | 279 | break; |
281 | case fsid_scc3: | 280 | case fsid_scc3: |
282 | fpi = &mpc8xx_scc_pdata; | ||
283 | fpi->init_ioports = &setup_scc3_ioports; | 281 | fpi->init_ioports = &setup_scc3_ioports; |
284 | mpc885ads_scc_phy_init(fpi->phy_addr); | ||
285 | break; | 282 | break; |
286 | default: | 283 | default: |
287 | printk(KERN_WARNING"Device %s is not supported!\n", pdev->name); | 284 | printk(KERN_WARNING "Device %s is not supported!\n", pdev->name); |
288 | return; | 285 | return; |
289 | } | 286 | } |
290 | 287 | ||
@@ -295,7 +292,7 @@ static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) | |||
295 | for (i = 0; i < 6; i++) | 292 | for (i = 0; i < 6; i++) |
296 | fpi->macaddr[i] = *e++; | 293 | fpi->macaddr[i] = *e++; |
297 | 294 | ||
298 | fpi->macaddr[5 - pdev->id]++; | 295 | fpi->macaddr[5] += mac_count++; |
299 | 296 | ||
300 | } | 297 | } |
301 | 298 | ||
@@ -318,58 +315,6 @@ static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev, | |||
318 | mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); | 315 | mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); |
319 | } | 316 | } |
320 | 317 | ||
321 | /* SCC ethernet controller does not have MII management channel. FEC1 MII | ||
322 | * channel is used to communicate with the 10Mbit PHY. | ||
323 | */ | ||
324 | |||
325 | #define MII_ECNTRL_PINMUX 0x4 | ||
326 | #define FEC_ECNTRL_PINMUX 0x00000004 | ||
327 | #define FEC_RCNTRL_MII_MODE 0x00000004 | ||
328 | |||
329 | /* Make MII read/write commands. | ||
330 | */ | ||
331 | #define mk_mii_write(REG, VAL, PHY_ADDR) (0x50020000 | (((REG) & 0x1f) << 18) | \ | ||
332 | ((VAL) & 0xffff) | ((PHY_ADDR) << 23)) | ||
333 | |||
334 | static void mpc885ads_scc_phy_init(char phy_addr) | ||
335 | { | ||
336 | volatile immap_t *immap; | ||
337 | volatile fec_t *fecp; | ||
338 | bd_t *bd; | ||
339 | |||
340 | bd = (bd_t *) __res; | ||
341 | immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */ | ||
342 | fecp = &(immap->im_cpm.cp_fec); | ||
343 | |||
344 | /* Enable MII pins of the FEC1 | ||
345 | */ | ||
346 | setbits16(&immap->im_ioport.iop_pdpar, 0x0080); | ||
347 | clrbits16(&immap->im_ioport.iop_pddir, 0x0080); | ||
348 | /* Set MII speed to 2.5 MHz | ||
349 | */ | ||
350 | out_be32(&fecp->fec_mii_speed, | ||
351 | ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1); | ||
352 | |||
353 | /* Enable FEC pin MUX | ||
354 | */ | ||
355 | setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX); | ||
356 | setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE); | ||
357 | |||
358 | out_be32(&fecp->fec_mii_data, | ||
359 | mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr)); | ||
360 | udelay(100); | ||
361 | out_be32(&fecp->fec_mii_data, | ||
362 | mk_mii_write(MII_ADVERTISE, | ||
363 | ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr)); | ||
364 | udelay(100); | ||
365 | |||
366 | /* Disable FEC MII settings | ||
367 | */ | ||
368 | clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX); | ||
369 | clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE); | ||
370 | out_be32(&fecp->fec_mii_speed, 0); | ||
371 | } | ||
372 | |||
373 | static void setup_smc1_ioports(void) | 318 | static void setup_smc1_ioports(void) |
374 | { | 319 | { |
375 | immap_t *immap = (immap_t *) IMAP_ADDR; | 320 | immap_t *immap = (immap_t *) IMAP_ADDR; |
@@ -462,6 +407,9 @@ static int mpc885ads_platform_notify(struct device *dev) | |||
462 | 407 | ||
463 | int __init mpc885ads_init(void) | 408 | int __init mpc885ads_init(void) |
464 | { | 409 | { |
410 | struct fs_mii_fec_platform_info* fmpi; | ||
411 | bd_t *bd = (bd_t *) __res; | ||
412 | |||
465 | printk(KERN_NOTICE "mpc885ads: Init\n"); | 413 | printk(KERN_NOTICE "mpc885ads: Init\n"); |
466 | 414 | ||
467 | platform_notify = mpc885ads_platform_notify; | 415 | platform_notify = mpc885ads_platform_notify; |
@@ -471,8 +419,17 @@ int __init mpc885ads_init(void) | |||
471 | 419 | ||
472 | ppc_sys_device_enable(MPC8xx_CPM_FEC1); | 420 | ppc_sys_device_enable(MPC8xx_CPM_FEC1); |
473 | 421 | ||
422 | ppc_sys_device_enable(MPC8xx_MDIO_FEC); | ||
423 | fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data = | ||
424 | &mpc8xx_mdio_fec_pdata; | ||
425 | |||
426 | fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1; | ||
427 | |||
428 | /* No PHY interrupt line here */ | ||
429 | fmpi->irq[0xf] = SIU_IRQ7; | ||
430 | |||
474 | #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 | 431 | #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 |
475 | ppc_sys_device_enable(MPC8xx_CPM_SCC1); | 432 | ppc_sys_device_enable(MPC8xx_CPM_SCC3); |
476 | 433 | ||
477 | #endif | 434 | #endif |
478 | #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 | 435 | #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 |
diff --git a/arch/ppc/platforms/pq2ads_pd.h b/arch/ppc/platforms/pq2ads_pd.h index 8f14a43eafec..672483df8079 100644 --- a/arch/ppc/platforms/pq2ads_pd.h +++ b/arch/ppc/platforms/pq2ads_pd.h | |||
@@ -29,86 +29,4 @@ | |||
29 | #define F3_RXCLK 13 | 29 | #define F3_RXCLK 13 |
30 | #define F3_TXCLK 14 | 30 | #define F3_TXCLK 14 |
31 | 31 | ||
32 | /* Automatically generates register configurations */ | ||
33 | #define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ | ||
34 | |||
35 | #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ | ||
36 | #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ | ||
37 | #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ | ||
38 | #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ | ||
39 | #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ | ||
40 | #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ | ||
41 | |||
42 | #define PC_F1RXCLK PC_CLK(F1_RXCLK) | ||
43 | #define PC_F1TXCLK PC_CLK(F1_TXCLK) | ||
44 | #define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) | ||
45 | #define CMX1_CLK_MASK ((uint)0xff000000) | ||
46 | |||
47 | #define PC_F2RXCLK PC_CLK(F2_RXCLK) | ||
48 | #define PC_F2TXCLK PC_CLK(F2_TXCLK) | ||
49 | #define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) | ||
50 | #define CMX2_CLK_MASK ((uint)0x00ff0000) | ||
51 | |||
52 | #define PC_F3RXCLK PC_CLK(F3_RXCLK) | ||
53 | #define PC_F3TXCLK PC_CLK(F3_TXCLK) | ||
54 | #define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) | ||
55 | #define CMX3_CLK_MASK ((uint)0x0000ff00) | ||
56 | |||
57 | /* I/O Pin assignment for FCC1. I don't yet know the best way to do this, | ||
58 | * but there is little variation among the choices. | ||
59 | */ | ||
60 | #define PA1_COL 0x00000001U | ||
61 | #define PA1_CRS 0x00000002U | ||
62 | #define PA1_TXER 0x00000004U | ||
63 | #define PA1_TXEN 0x00000008U | ||
64 | #define PA1_RXDV 0x00000010U | ||
65 | #define PA1_RXER 0x00000020U | ||
66 | #define PA1_TXDAT 0x00003c00U | ||
67 | #define PA1_RXDAT 0x0003c000U | ||
68 | #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) | ||
69 | #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ | ||
70 | PA1_RXDV | PA1_RXER) | ||
71 | #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) | ||
72 | #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) | ||
73 | |||
74 | |||
75 | /* I/O Pin assignment for FCC2. I don't yet know the best way to do this, | ||
76 | * but there is little variation among the choices. | ||
77 | */ | ||
78 | #define PB2_TXER 0x00000001U | ||
79 | #define PB2_RXDV 0x00000002U | ||
80 | #define PB2_TXEN 0x00000004U | ||
81 | #define PB2_RXER 0x00000008U | ||
82 | #define PB2_COL 0x00000010U | ||
83 | #define PB2_CRS 0x00000020U | ||
84 | #define PB2_TXDAT 0x000003c0U | ||
85 | #define PB2_RXDAT 0x00003c00U | ||
86 | #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ | ||
87 | PB2_RXER | PB2_RXDV | PB2_TXER) | ||
88 | #define PB2_PSORB1 (PB2_TXEN) | ||
89 | #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) | ||
90 | #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) | ||
91 | |||
92 | |||
93 | /* I/O Pin assignment for FCC3. I don't yet know the best way to do this, | ||
94 | * but there is little variation among the choices. | ||
95 | */ | ||
96 | #define PB3_RXDV 0x00004000U | ||
97 | #define PB3_RXER 0x00008000U | ||
98 | #define PB3_TXER 0x00010000U | ||
99 | #define PB3_TXEN 0x00020000U | ||
100 | #define PB3_COL 0x00040000U | ||
101 | #define PB3_CRS 0x00080000U | ||
102 | #define PB3_TXDAT 0x0f000000U | ||
103 | #define PB3_RXDAT 0x00f00000U | ||
104 | #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ | ||
105 | PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) | ||
106 | #define PB3_PSORB1 0 | ||
107 | #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) | ||
108 | #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) | ||
109 | |||
110 | #define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) | ||
111 | #define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) | ||
112 | #define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) | ||
113 | |||
114 | #endif | 32 | #endif |