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authorMatthias Fuchs <matthias.fuchs@esd-electronics.com>2006-06-14 09:35:05 -0400
committerPaul Mackerras <paulus@samba.org>2006-06-15 05:31:27 -0400
commit2ba73b1d6fa62ddaa235c3c5fdf6095cae6ba748 (patch)
treecd1d84913a99e685fbc2a6a088ca86afc7d25501 /arch/ppc/platforms
parent4312dc76a88146c4f1d693fc4643d1df12aaf755 (diff)
[POWERPC] ppc32: fix CPCI405 board support
Hi, this patch brings the CPCI405 board support up to date and fixes several outstanding issues: -add bios_fixup() -enable RTC only when CONFIG_GEN_RTC defined -corrected CompactPCI interrupt map -added cpci405_early_serial_map for correct UART clocking -removed unused code Matthias Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r--arch/ppc/platforms/4xx/Kconfig2
-rw-r--r--arch/ppc/platforms/4xx/cpci405.c139
-rw-r--r--arch/ppc/platforms/4xx/cpci405.h30
3 files changed, 140 insertions, 31 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index 174ddbc9758b..293bd489e7d9 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -183,7 +183,7 @@ config IBM_EMAC4
183 183
184config BIOS_FIXUP 184config BIOS_FIXUP
185 bool 185 bool
186 depends on BUBINGA || EP405 || SYCAMORE || WALNUT 186 depends on BUBINGA || EP405 || SYCAMORE || WALNUT || CPCI405
187 default y 187 default y
188 188
189# OAK doesn't exist but wanted to keep this around for any future 403GCX boards 189# OAK doesn't exist but wanted to keep this around for any future 403GCX boards
diff --git a/arch/ppc/platforms/4xx/cpci405.c b/arch/ppc/platforms/4xx/cpci405.c
index 6571e39fbe48..970b69831e6f 100644
--- a/arch/ppc/platforms/4xx/cpci405.c
+++ b/arch/ppc/platforms/4xx/cpci405.c
@@ -1,10 +1,12 @@
1/* 1/*
2 * Board setup routines for the esd CPCI-405 cPCI Board. 2 * Board setup routines for the esd CPCI-405 cPCI Board.
3 * 3 *
4 * Author: Stefan Roese 4 * Copyright 2001-2006 esd electronic system design - hannover germany
5 * stefan.roese@esd-electronics.com
6 * 5 *
7 * Copyright 2001 esd electronic system design - hannover germany 6 * Authors: Matthias Fuchs
7 * matthias.fuchs@esd-electronics.com
8 * Stefan Roese
9 * stefan.roese@esd-electronics.com
8 * 10 *
9 * This program is free software; you can redistribute it and/or modify it 11 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 12 * under the terms of the GNU General Public License as published by the
@@ -20,9 +22,17 @@
20#include <asm/pci-bridge.h> 22#include <asm/pci-bridge.h>
21#include <asm/machdep.h> 23#include <asm/machdep.h>
22#include <asm/todc.h> 24#include <asm/todc.h>
25#include <linux/serial.h>
26#include <linux/serial_core.h>
23#include <asm/ocp.h> 27#include <asm/ocp.h>
28#include <asm/ibm_ocp_pci.h>
29#include <platforms/4xx/ibm405gp.h>
24 30
31#ifdef CONFIG_GEN_RTC
25void *cpci405_nvram; 32void *cpci405_nvram;
33#endif
34
35extern bd_t __res;
26 36
27/* 37/*
28 * Some IRQs unique to CPCI-405. 38 * Some IRQs unique to CPCI-405.
@@ -36,18 +46,69 @@ ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
36 * A B C D 46 * A B C D
37 */ 47 */
38 { 48 {
39 {28, 28, 28, 28}, /* IDSEL 15 - cPCI slot 8 */ 49 {28, 29, 30, 27}, /* IDSEL 15 - cPCI slot 8 */
40 {29, 29, 29, 29}, /* IDSEL 16 - cPCI slot 7 */ 50 {29, 30, 27, 28}, /* IDSEL 16 - cPCI slot 7 */
41 {30, 30, 30, 30}, /* IDSEL 17 - cPCI slot 6 */ 51 {30, 27, 28, 29}, /* IDSEL 17 - cPCI slot 6 */
42 {27, 27, 27, 27}, /* IDSEL 18 - cPCI slot 5 */ 52 {27, 28, 29, 30}, /* IDSEL 18 - cPCI slot 5 */
43 {28, 28, 28, 28}, /* IDSEL 19 - cPCI slot 4 */ 53 {28, 29, 30, 27}, /* IDSEL 19 - cPCI slot 4 */
44 {29, 29, 29, 29}, /* IDSEL 20 - cPCI slot 3 */ 54 {29, 30, 27, 28}, /* IDSEL 20 - cPCI slot 3 */
45 {30, 30, 30, 30}, /* IDSEL 21 - cPCI slot 2 */ 55 {30, 27, 28, 29}, /* IDSEL 21 - cPCI slot 2 */
46 }; 56 };
47 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4; 57 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
48 return PCI_IRQ_TABLE_LOOKUP; 58 return PCI_IRQ_TABLE_LOOKUP;
49}; 59};
50 60
61/* The serial clock for the chip is an internal clock determined by
62 * different clock speeds/dividers.
63 * Calculate the proper input baud rate and setup the serial driver.
64 */
65static void __init
66cpci405_early_serial_map(void)
67{
68 u32 uart_div;
69 int uart_clock;
70 struct uart_port port;
71
72 /* Calculate the serial clock input frequency
73 *
74 * The uart clock is the cpu frequency (provided in the board info
75 * structure) divided by the external UART Divisor.
76 */
77 uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
78 uart_clock = __res.bi_procfreq / uart_div;
79
80 /* Setup serial port access */
81 memset(&port, 0, sizeof(port));
82#if defined(CONFIG_UART0_TTYS0)
83 port.membase = (void*)UART0_IO_BASE;
84 port.irq = UART0_INT;
85#else
86 port.membase = (void*)UART1_IO_BASE;
87 port.irq = UART1_INT;
88#endif
89 port.uartclk = uart_clock;
90 port.regshift = 0;
91 port.iotype = UPIO_MEM;
92 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
93 port.line = 0;
94
95 if (early_serial_setup(&port) != 0) {
96 printk("Early serial init of port 0 failed\n");
97 }
98#if defined(CONFIG_UART0_TTYS0)
99 port.membase = (void*)UART1_IO_BASE;
100 port.irq = UART1_INT;
101#else
102 port.membase = (void*)UART0_IO_BASE;
103 port.irq = UART0_INT;
104#endif
105 port.line = 1;
106
107 if (early_serial_setup(&port) != 0) {
108 printk("Early serial init of port 1 failed\n");
109 }
110}
111
51void __init 112void __init
52cpci405_setup_arch(void) 113cpci405_setup_arch(void)
53{ 114{
@@ -55,14 +116,68 @@ cpci405_setup_arch(void)
55 116
56 ibm_ocp_set_emac(0, 0); 117 ibm_ocp_set_emac(0, 0);
57 118
58 TODC_INIT(TODC_TYPE_MK48T35, cpci405_nvram, cpci405_nvram, cpci405_nvram, 8); 119 cpci405_early_serial_map();
120
121#ifdef CONFIG_GEN_RTC
122 TODC_INIT(TODC_TYPE_MK48T35,
123 cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
124#endif
125}
126
127void __init
128bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
129{
130 unsigned int bar_response, bar;
131
132 /* Disable region first */
133 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
134 /* PLB starting addr, PCI: 0x80000000 */
135 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
136 /* PCI start addr, 0x80000000 */
137 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
138 /* 512MB range of PLB to PCI */
139 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
140 /* Enable no pre-fetch, enable region */
141 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
142 (PPC405_PCI_UPPER_MEM -
143 PPC405_PCI_MEM_BASE)) | 0x01));
144
145 /* Disable region one */
146 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
147 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
148 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
149 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
150 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
151 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
152
153 /* Disable region two */
154 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
155 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
156 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
157 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
158 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
159 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
160 out_le32((void *) &(pcip->ptm2la), 0x00000000);
161
162 /* Zero config bars */
163 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
164 early_write_config_dword(hose, hose->first_busno,
165 PCI_FUNC(hose->first_busno), bar,
166 0x00000000);
167 early_read_config_dword(hose, hose->first_busno,
168 PCI_FUNC(hose->first_busno), bar,
169 &bar_response);
170 }
59} 171}
60 172
61void __init 173void __init
62cpci405_map_io(void) 174cpci405_map_io(void)
63{ 175{
64 ppc4xx_map_io(); 176 ppc4xx_map_io();
177
178#ifdef CONFIG_GEN_RTC
65 cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE); 179 cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
180#endif
66} 181}
67 182
68void __init 183void __init
@@ -74,9 +189,11 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
74 ppc_md.setup_arch = cpci405_setup_arch; 189 ppc_md.setup_arch = cpci405_setup_arch;
75 ppc_md.setup_io_mappings = cpci405_map_io; 190 ppc_md.setup_io_mappings = cpci405_map_io;
76 191
192#ifdef CONFIG_GEN_RTC
77 ppc_md.time_init = todc_time_init; 193 ppc_md.time_init = todc_time_init;
78 ppc_md.set_rtc_time = todc_set_rtc_time; 194 ppc_md.set_rtc_time = todc_set_rtc_time;
79 ppc_md.get_rtc_time = todc_get_rtc_time; 195 ppc_md.get_rtc_time = todc_get_rtc_time;
80 ppc_md.nvram_read_val = todc_direct_read_val; 196 ppc_md.nvram_read_val = todc_direct_read_val;
81 ppc_md.nvram_write_val = todc_direct_write_val; 197 ppc_md.nvram_write_val = todc_direct_write_val;
198#endif
82} 199}
diff --git a/arch/ppc/platforms/4xx/cpci405.h b/arch/ppc/platforms/4xx/cpci405.h
index e27f7cb650d8..f5a5c0cd062d 100644
--- a/arch/ppc/platforms/4xx/cpci405.h
+++ b/arch/ppc/platforms/4xx/cpci405.h
@@ -1,37 +1,29 @@
1/* 1/*
2 * CPCI-405 board specific definitions 2 * CPCI-405 board specific definitions
3 * 3 *
4 * Copyright (c) 2001 Stefan Roese (stefan.roese@esd-electronics.com) 4 * Copyright 2001-2006 esd electronic system design - hannover germany
5 *
6 * Authors: Matthias Fuchs
7 * matthias.fuchs@esd-electronics.com
8 * Stefan Roese
9 * stefan.roese@esd-electronics.com
5 */ 10 */
6 11
7#ifdef __KERNEL__ 12#ifdef __KERNEL__
8#ifndef __ASM_CPCI405_H__ 13#ifndef __CPCI405_H__
9#define __ASM_CPCI405_H__ 14#define __CPCI405_H__
10 15
11#include <linux/config.h> 16#include <linux/config.h>
12
13/* We have a 405GP core */
14#include <platforms/4xx/ibm405gp.h> 17#include <platforms/4xx/ibm405gp.h>
15
16#include <asm/ppcboot.h> 18#include <asm/ppcboot.h>
17 19
18#ifndef __ASSEMBLY__
19/* Some 4xx parts use a different timebase frequency from the internal clock.
20*/
21#define bi_tbfreq bi_intfreq
22
23/* Map for the NVRAM space */ 20/* Map for the NVRAM space */
24#define CPCI405_NVRAM_PADDR ((uint)0xf0200000) 21#define CPCI405_NVRAM_PADDR ((uint)0xf0200000)
25#define CPCI405_NVRAM_SIZE ((uint)32*1024) 22#define CPCI405_NVRAM_SIZE ((uint)32*1024)
26 23
27#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK 24#define BASE_BAUD 0
28#define BASE_BAUD 201600
29#else
30#define BASE_BAUD 691200
31#endif
32 25
33#define PPC4xx_MACHINE_NAME "esd CPCI-405" 26#define PPC4xx_MACHINE_NAME "esd CPCI-405"
34 27
35#endif /* !__ASSEMBLY__ */ 28#endif /* __CPCI405_H__ */
36#endif /* __ASM_CPCI405_H__ */
37#endif /* __KERNEL__ */ 29#endif /* __KERNEL__ */