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authorSteve French <sfrench@us.ibm.com>2005-09-06 18:47:31 -0400
committerSteve French <sfrench@us.ibm.com>2005-09-06 18:47:31 -0400
commitc08319a9d50b5c9cb4fdb33728bd16497cf4ddd3 (patch)
tree5fbec9030029da1ec387c18b85f26f19ee50da44 /arch/ppc/platforms
parentbfa0d75a1eee59f0577e3c1697ff570b77581a35 (diff)
parent4706df3d3c42af802597d82c8b1542c3d52eab23 (diff)
Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r--arch/ppc/platforms/4xx/Kconfig15
-rw-r--r--arch/ppc/platforms/4xx/Makefile2
-rw-r--r--arch/ppc/platforms/4xx/ash.c250
-rw-r--r--arch/ppc/platforms/4xx/ash.h83
-rw-r--r--arch/ppc/platforms/4xx/bamboo.c59
-rw-r--r--arch/ppc/platforms/4xx/bamboo.h2
-rw-r--r--arch/ppc/platforms/4xx/ebony.c7
-rw-r--r--arch/ppc/platforms/4xx/ibm405ep.c1
-rw-r--r--arch/ppc/platforms/4xx/ibm405gp.c1
-rw-r--r--arch/ppc/platforms/4xx/ibm405gpr.c1
-rw-r--r--arch/ppc/platforms/4xx/ibm440ep.c1
-rw-r--r--arch/ppc/platforms/4xx/ibm440gp.c1
-rw-r--r--arch/ppc/platforms/4xx/ibm440gx.c1
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.c1
-rw-r--r--arch/ppc/platforms/4xx/ibmnp405h.c7
-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.c52
-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.h4
-rw-r--r--arch/ppc/platforms/4xx/luan.c7
-rw-r--r--arch/ppc/platforms/4xx/luan.h2
-rw-r--r--arch/ppc/platforms/4xx/oak.c255
-rw-r--r--arch/ppc/platforms/4xx/oak.h96
-rw-r--r--arch/ppc/platforms/4xx/oak_setup.h50
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c7
-rw-r--r--arch/ppc/platforms/4xx/redwood5.c13
-rw-r--r--arch/ppc/platforms/83xx/mpc834x_sys.c35
-rw-r--r--arch/ppc/platforms/83xx/mpc834x_sys.h40
-rw-r--r--arch/ppc/platforms/Makefile6
-rw-r--r--arch/ppc/platforms/adir.h95
-rw-r--r--arch/ppc/platforms/adir_pci.c247
-rw-r--r--arch/ppc/platforms/adir_pic.c130
-rw-r--r--arch/ppc/platforms/adir_setup.c210
-rw-r--r--arch/ppc/platforms/cpci690.c177
-rw-r--r--arch/ppc/platforms/cpci690.h2
-rw-r--r--arch/ppc/platforms/ev64360.c510
-rw-r--r--arch/ppc/platforms/ev64360.h116
-rw-r--r--arch/ppc/platforms/k2.c613
-rw-r--r--arch/ppc/platforms/k2.h82
-rw-r--r--arch/ppc/platforms/katana.c253
-rw-r--r--arch/ppc/platforms/katana.h16
-rw-r--r--arch/ppc/platforms/mcpn765.c527
-rw-r--r--arch/ppc/platforms/mcpn765.h122
-rw-r--r--arch/ppc/platforms/pcore.c352
-rw-r--r--arch/ppc/platforms/pcore.h39
-rw-r--r--arch/ppc/platforms/pmac_pic.c2
-rw-r--r--arch/ppc/platforms/spd8xx.h92
-rw-r--r--arch/ppc/platforms/tqm8xx.h23
46 files changed, 1073 insertions, 3534 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index 805dd98908a3..76f4476cab44 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -16,11 +16,6 @@ choice
16 depends on 40x 16 depends on 40x
17 default WALNUT 17 default WALNUT
18 18
19config ASH
20 bool "Ash"
21 help
22 This option enables support for the IBM NP405H evaluation board.
23
24config BUBINGA 19config BUBINGA
25 bool "Bubinga" 20 bool "Bubinga"
26 select WANT_EARLY_SERIAL 21 select WANT_EARLY_SERIAL
@@ -37,11 +32,6 @@ config EP405
37 help 32 help
38 This option enables support for the EP405/EP405PC boards. 33 This option enables support for the EP405/EP405PC boards.
39 34
40config OAK
41 bool "Oak"
42 help
43 This option enables support for the IBM 403GCX evaluation board.
44
45config REDWOOD_5 35config REDWOOD_5
46 bool "Redwood-5" 36 bool "Redwood-5"
47 help 37 help
@@ -152,13 +142,13 @@ config IBM440EP_ERR42
152# All 405-based cores up until the 405GPR and 405EP have this errata. 142# All 405-based cores up until the 405GPR and 405EP have this errata.
153config IBM405_ERR77 143config IBM405_ERR77
154 bool 144 bool
155 depends on 40x && !403GCX && !405GPR 145 depends on 40x && !403GCX && !405GPR && !405EP
156 default y 146 default y
157 147
158# All 40x-based cores, up until the 405GPR and 405EP have this errata. 148# All 40x-based cores, up until the 405GPR and 405EP have this errata.
159config IBM405_ERR51 149config IBM405_ERR51
160 bool 150 bool
161 depends on 40x && !405GPR 151 depends on 40x && !405GPR && !405EP
162 default y 152 default y
163 153
164config BOOKE 154config BOOKE
@@ -186,6 +176,7 @@ config BIOS_FIXUP
186 depends on BUBINGA || EP405 || SYCAMORE || WALNUT 176 depends on BUBINGA || EP405 || SYCAMORE || WALNUT
187 default y 177 default y
188 178
179# OAK doesn't exist but wanted to keep this around for any future 403GCX boards
189config 403GCX 180config 403GCX
190 bool 181 bool
191 depends OAK 182 depends OAK
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index 844c3b5066e8..1dd6d7fd6a9a 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -1,14 +1,12 @@
1# 1#
2# Makefile for the PowerPC 4xx linux kernel. 2# Makefile for the PowerPC 4xx linux kernel.
3 3
4obj-$(CONFIG_ASH) += ash.o
5obj-$(CONFIG_BAMBOO) += bamboo.o 4obj-$(CONFIG_BAMBOO) += bamboo.o
6obj-$(CONFIG_CPCI405) += cpci405.o 5obj-$(CONFIG_CPCI405) += cpci405.o
7obj-$(CONFIG_EBONY) += ebony.o 6obj-$(CONFIG_EBONY) += ebony.o
8obj-$(CONFIG_EP405) += ep405.o 7obj-$(CONFIG_EP405) += ep405.o
9obj-$(CONFIG_BUBINGA) += bubinga.o 8obj-$(CONFIG_BUBINGA) += bubinga.o
10obj-$(CONFIG_LUAN) += luan.o 9obj-$(CONFIG_LUAN) += luan.o
11obj-$(CONFIG_OAK) += oak.o
12obj-$(CONFIG_OCOTEA) += ocotea.o 10obj-$(CONFIG_OCOTEA) += ocotea.o
13obj-$(CONFIG_REDWOOD_5) += redwood5.o 11obj-$(CONFIG_REDWOOD_5) += redwood5.o
14obj-$(CONFIG_REDWOOD_6) += redwood6.o 12obj-$(CONFIG_REDWOOD_6) += redwood6.o
diff --git a/arch/ppc/platforms/4xx/ash.c b/arch/ppc/platforms/4xx/ash.c
deleted file mode 100644
index ce2911793716..000000000000
--- a/arch/ppc/platforms/4xx/ash.c
+++ /dev/null
@@ -1,250 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/ash.c
3 *
4 * Support for the IBM NP405H ash eval board
5 *
6 * Author: Armin Kuster <akuster@mvista.com>
7 *
8 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/pagemap.h>
16#include <linux/pci.h>
17
18#include <asm/machdep.h>
19#include <asm/pci-bridge.h>
20#include <asm/io.h>
21#include <asm/ocp.h>
22#include <asm/ibm_ocp_pci.h>
23#include <asm/todc.h>
24
25#ifdef DEBUG
26#define DBG(x...) printk(x)
27#else
28#define DBG(x...)
29#endif
30
31void *ash_rtc_base;
32
33/* Some IRQs unique to Walnut.
34 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
35 */
36int __init
37ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
38{
39 static char pci_irq_table[][4] =
40 /*
41 * PCI IDSEL/INTPIN->INTLINE
42 * A B C D
43 */
44 {
45 {24, 24, 24, 24}, /* IDSEL 1 - PCI slot 1 */
46 {25, 25, 25, 25}, /* IDSEL 2 - PCI slot 2 */
47 {26, 26, 26, 26}, /* IDSEL 3 - PCI slot 3 */
48 {27, 27, 27, 27}, /* IDSEL 4 - PCI slot 4 */
49 };
50
51 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
52 return PCI_IRQ_TABLE_LOOKUP;
53}
54
55void __init
56ash_setup_arch(void)
57{
58 ppc4xx_setup_arch();
59
60 ibm_ocp_set_emac(0, 3);
61
62#ifdef CONFIG_DEBUG_BRINGUP
63 int i;
64 printk("\n");
65 printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
66 printk("\n");
67 printk("bi_s_version\t %s\n", bip->bi_s_version);
68 printk("bi_r_version\t %s\n", bip->bi_r_version);
69 printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
70 bip->bi_memsize / (1024 * 1000));
71 for (i = 0; i < EMAC_NUMS; i++) {
72 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", i,
73 bip->bi_enetaddr[i][0], bip->bi_enetaddr[i][1],
74 bip->bi_enetaddr[i][2], bip->bi_enetaddr[i][3],
75 bip->bi_enetaddr[i][4], bip->bi_enetaddr[i][5]);
76 }
77 printk("bi_pci_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
78 bip->bi_pci_enetaddr[0], bip->bi_pci_enetaddr[1],
79 bip->bi_pci_enetaddr[2], bip->bi_pci_enetaddr[3],
80 bip->bi_pci_enetaddr[4], bip->bi_pci_enetaddr[5]);
81
82 printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
83 bip->bi_intfreq, bip->bi_intfreq / 1000000);
84
85 printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
86 bip->bi_busfreq, bip->bi_busfreq / 1000000);
87 printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
88 bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000);
89
90 printk("\n");
91#endif
92 /* RTC step for ash */
93 ash_rtc_base = (void *) ASH_RTC_VADDR;
94 TODC_INIT(TODC_TYPE_DS1743, ash_rtc_base, ash_rtc_base, ash_rtc_base,
95 8);
96}
97
98void __init
99bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
100{
101 /*
102 * Expected PCI mapping:
103 *
104 * PLB addr PCI memory addr
105 * --------------------- ---------------------
106 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
107 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
108 *
109 * PLB addr PCI io addr
110 * --------------------- ---------------------
111 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
112 *
113 * The following code is simplified by assuming that the bootrom
114 * has been well behaved in following this mapping.
115 */
116
117#ifdef DEBUG
118 int i;
119
120 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
121 printk("PCI bridge regs before fixup \n");
122 for (i = 0; i <= 2; i++) {
123 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
124 printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
125 printk(" pmm%dpcila\t0x%x\n", i,
126 in_le32(&(pcip->pmm[i].pcila)));
127 printk(" pmm%dpciha\t0x%x\n", i,
128 in_le32(&(pcip->pmm[i].pciha)));
129 }
130 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
131 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
132 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
133 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
134 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
135 early_read_config_dword(hose, hose->first_busno,
136 PCI_FUNC(hose->first_busno), bar,
137 &bar_response);
138 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
139 hose->first_busno, PCI_SLOT(hose->first_busno),
140 PCI_FUNC(hose->first_busno), bar, bar_response);
141 }
142
143#endif
144 if (ppc_md.progress)
145 ppc_md.progress("bios_fixup(): enter", 0x800);
146
147 /* added for IBM boot rom version 1.15 bios bar changes -AK */
148
149 /* Disable region first */
150 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
151 /* PLB starting addr, PCI: 0x80000000 */
152 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
153 /* PCI start addr, 0x80000000 */
154 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
155 /* 512MB range of PLB to PCI */
156 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
157 /* Enable no pre-fetch, enable region */
158 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
159 (PPC405_PCI_UPPER_MEM -
160 PPC405_PCI_MEM_BASE)) | 0x01));
161
162 /* Disable region one */
163 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
164 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
165 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
166 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
167 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
168
169 /* Disable region two */
170 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
171 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
172 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
173 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
174 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
175
176 /* Enable PTM1 and PTM2, mapped to PLB address 0. */
177
178 out_le32((void *) &(pcip->ptm1la), 0x00000000);
179 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
180 out_le32((void *) &(pcip->ptm2la), 0x00000000);
181 out_le32((void *) &(pcip->ptm2ms), 0x00000001);
182
183 /* Write zero to PTM1 BAR. */
184
185 early_write_config_dword(hose, hose->first_busno,
186 PCI_FUNC(hose->first_busno),
187 PCI_BASE_ADDRESS_1,
188 0x00000000);
189
190 /* Disable PTM2 (unused) */
191
192 out_le32((void *) &(pcip->ptm2la), 0x00000000);
193 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
194
195 /* end work arround */
196 if (ppc_md.progress)
197 ppc_md.progress("bios_fixup(): done", 0x800);
198
199#ifdef DEBUG
200 printk("PCI bridge regs after fixup \n");
201 for (i = 0; i <= 2; i++) {
202 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
203 printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
204 printk(" pmm%dpcila\t0x%x\n", i,
205 in_le32(&(pcip->pmm[i].pcila)));
206 printk(" pmm%dpciha\t0x%x\n", i,
207 in_le32(&(pcip->pmm[i].pciha)));
208 }
209 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
210 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
211 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
212 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
213
214 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
215 early_read_config_dword(hose, hose->first_busno,
216 PCI_FUNC(hose->first_busno), bar,
217 &bar_response);
218 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
219 hose->first_busno, PCI_SLOT(hose->first_busno),
220 PCI_FUNC(hose->first_busno), bar, bar_response);
221 }
222
223
224#endif
225}
226
227void __init
228ash_map_io(void)
229{
230 ppc4xx_map_io();
231 io_block_mapping(ASH_RTC_VADDR, ASH_RTC_PADDR, ASH_RTC_SIZE, _PAGE_IO);
232}
233
234void __init
235platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
236 unsigned long r6, unsigned long r7)
237{
238 ppc4xx_init(r3, r4, r5, r6, r7);
239
240 ppc_md.setup_arch = ash_setup_arch;
241 ppc_md.setup_io_mappings = ash_map_io;
242
243#ifdef CONFIG_PPC_RTC
244 ppc_md.time_init = todc_time_init;
245 ppc_md.set_rtc_time = todc_set_rtc_time;
246 ppc_md.get_rtc_time = todc_get_rtc_time;
247 ppc_md.nvram_read_val = todc_direct_read_val;
248 ppc_md.nvram_write_val = todc_direct_write_val;
249#endif
250}
diff --git a/arch/ppc/platforms/4xx/ash.h b/arch/ppc/platforms/4xx/ash.h
deleted file mode 100644
index 5f7448ea418d..000000000000
--- a/arch/ppc/platforms/4xx/ash.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/ash.h
3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC
5 * Ash eval board.
6 *
7 * Author: Armin Kuster <akuster@mvista.com>
8 *
9 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_ASH_H__
17#define __ASM_ASH_H__
18#include <platforms/4xx/ibmnp405h.h>
19
20#ifndef __ASSEMBLY__
21/*
22 * Data structure defining board information maintained by the boot
23 * ROM on IBM's "Ash" evaluation board. An effort has been made to
24 * keep the field names consistent with the 8xx 'bd_t' board info
25 * structures.
26 */
27
28typedef struct board_info {
29 unsigned char bi_s_version[4]; /* Version of this structure */
30 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
31 unsigned int bi_memsize; /* DRAM installed, in bytes */
32 unsigned char bi_enetaddr[4][6]; /* Local Ethernet MAC address */
33 unsigned char bi_pci_enetaddr[6];
34 unsigned int bi_intfreq; /* Processor speed, in Hz */
35 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
36 unsigned int bi_pci_busfreq; /* PCI speed in Hz */
37} bd_t;
38
39/* Some 4xx parts use a different timebase frequency from the internal clock.
40*/
41#define bi_tbfreq bi_intfreq
42
43/* Memory map for the IBM "Ash" NP405H evaluation board.
44 */
45
46extern void *ash_rtc_base;
47#define ASH_RTC_PADDR ((uint)0xf0000000)
48#define ASH_RTC_VADDR ASH_RTC_PADDR
49#define ASH_RTC_SIZE ((uint)8*1024)
50
51
52/* Early initialization address mapping for block_io.
53 * Standard 405GP map.
54 */
55#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
56#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
57#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
58#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
59#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
60#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
61#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
62#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
63#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
64#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
65#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
66#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
67
68#define NR_BOARD_IRQS 32
69
70#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
71#define BASE_BAUD 201600
72#else
73#define BASE_BAUD 691200
74#endif
75
76#define PPC4xx_MACHINE_NAME "IBM NP405H Ash"
77
78extern char pci_irq_table[][4];
79
80
81#endif /* !__ASSEMBLY__ */
82#endif /* __ASM_ASH_H__ */
83#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c
index f116787b0b76..ac391d463d78 100644
--- a/arch/ppc/platforms/4xx/bamboo.c
+++ b/arch/ppc/platforms/4xx/bamboo.c
@@ -52,13 +52,6 @@
52#include <syslib/gen550.h> 52#include <syslib/gen550.h>
53#include <syslib/ibm440gx_common.h> 53#include <syslib/ibm440gx_common.h>
54 54
55/*
56 * This is a horrible kludge, we eventually need to abstract this
57 * generic PHY stuff, so the standard phy mode defines can be
58 * easily used from arch code.
59 */
60#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
61
62bd_t __res; 55bd_t __res;
63 56
64static struct ibm44x_clocks clocks __initdata; 57static struct ibm44x_clocks clocks __initdata;
@@ -123,33 +116,69 @@ bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
123 116
124static void __init bamboo_set_emacdata(void) 117static void __init bamboo_set_emacdata(void)
125{ 118{
126 unsigned char * selection1_base; 119 u8 * base_addr;
127 struct ocp_def *def; 120 struct ocp_def *def;
128 struct ocp_func_emac_data *emacdata; 121 struct ocp_func_emac_data *emacdata;
129 u8 selection1_val; 122 u8 val;
130 int mode; 123 int mode;
124 u32 excluded = 0;
131 125
132 selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16); 126 base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
133 selection1_val = readb(selection1_base); 127 val = readb(base_addr);
134 iounmap((void *) selection1_base); 128 iounmap((void *) base_addr);
135 if (BAMBOO_SEL_MII(selection1_val)) 129 if (BAMBOO_SEL_MII(val))
136 mode = PHY_MODE_MII; 130 mode = PHY_MODE_MII;
137 else if (BAMBOO_SEL_RMII(selection1_val)) 131 else if (BAMBOO_SEL_RMII(val))
138 mode = PHY_MODE_RMII; 132 mode = PHY_MODE_RMII;
139 else 133 else
140 mode = PHY_MODE_SMII; 134 mode = PHY_MODE_SMII;
141 135
142 /* Set mac_addr and phy mode for each EMAC */ 136 /*
137 * SW2 on the Bamboo is used for ethernet configuration and is accessed
138 * via the CONFIG2 register in the FPGA. If the ANEG pin is set,
139 * overwrite the supported features with the settings in SW2.
140 *
141 * This is used as a workaround for the improperly biased RJ-45 sockets
142 * on the Rev. 0 Bamboo. By default only 10baseT is functional.
143 * Removing inductors L17 and L18 from the board allows 100baseT, but
144 * disables 10baseT. The Rev. 1 has no such limitations.
145 */
146
147 base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
148 val = readb(base_addr);
149 iounmap((void *) base_addr);
150 if (!BAMBOO_AUTONEGOTIATE(val)) {
151 excluded |= SUPPORTED_Autoneg;
152 if (BAMBOO_FORCE_100Mbps(val)) {
153 excluded |= SUPPORTED_10baseT_Full;
154 excluded |= SUPPORTED_10baseT_Half;
155 if (BAMBOO_FULL_DUPLEX_EN(val))
156 excluded |= SUPPORTED_100baseT_Half;
157 else
158 excluded |= SUPPORTED_100baseT_Full;
159 } else {
160 excluded |= SUPPORTED_100baseT_Full;
161 excluded |= SUPPORTED_100baseT_Half;
162 if (BAMBOO_FULL_DUPLEX_EN(val))
163 excluded |= SUPPORTED_10baseT_Half;
164 else
165 excluded |= SUPPORTED_10baseT_Full;
166 }
167 }
168
169 /* Set mac_addr, phy mode and unsupported phy features for each EMAC */
143 170
144 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); 171 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
145 emacdata = def->additions; 172 emacdata = def->additions;
146 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); 173 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
147 emacdata->phy_mode = mode; 174 emacdata->phy_mode = mode;
175 emacdata->phy_feat_exc = excluded;
148 176
149 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1); 177 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
150 emacdata = def->additions; 178 emacdata = def->additions;
151 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); 179 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
152 emacdata->phy_mode = mode; 180 emacdata->phy_mode = mode;
181 emacdata->phy_feat_exc = excluded;
153} 182}
154 183
155static int 184static int
diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h
index 63d714504148..5c0192826494 100644
--- a/arch/ppc/platforms/4xx/bamboo.h
+++ b/arch/ppc/platforms/4xx/bamboo.h
@@ -88,7 +88,7 @@
88#define STD_UART_OP(num) \ 88#define STD_UART_OP(num) \
89 { 0, BASE_BAUD, 0, UART##num##_INT, \ 89 { 0, BASE_BAUD, 0, UART##num##_INT, \
90 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 90 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
91 iomem_base: UART##num##_IO_BASE, \ 91 iomem_base: (void*)UART##num##_IO_BASE, \
92 io_type: SERIAL_IO_MEM}, 92 io_type: SERIAL_IO_MEM},
93 93
94#define SERIAL_PORT_DFNS \ 94#define SERIAL_PORT_DFNS \
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
index 509e69a095f0..0fd3442f5131 100644
--- a/arch/ppc/platforms/4xx/ebony.c
+++ b/arch/ppc/platforms/4xx/ebony.c
@@ -55,13 +55,6 @@
55#include <syslib/gen550.h> 55#include <syslib/gen550.h>
56#include <syslib/ibm440gp_common.h> 56#include <syslib/ibm440gp_common.h>
57 57
58/*
59 * This is a horrible kludge, we eventually need to abstract this
60 * generic PHY stuff, so the standard phy mode defines can be
61 * easily used from arch code.
62 */
63#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
64
65bd_t __res; 58bd_t __res;
66 59
67static struct ibm44x_clocks clocks __initdata; 60static struct ibm44x_clocks clocks __initdata;
diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c
index 6d44567f4dd2..093b28d27a41 100644
--- a/arch/ppc/platforms/4xx/ibm405ep.c
+++ b/arch/ppc/platforms/4xx/ibm405ep.c
@@ -33,6 +33,7 @@ static struct ocp_func_mal_data ibm405ep_mal0_def = {
33 .txde_irq = 13, /* TX Descriptor Error IRQ */ 33 .txde_irq = 13, /* TX Descriptor Error IRQ */
34 .rxde_irq = 14, /* RX Descriptor Error IRQ */ 34 .rxde_irq = 14, /* RX Descriptor Error IRQ */
35 .serr_irq = 10, /* MAL System Error IRQ */ 35 .serr_irq = 10, /* MAL System Error IRQ */
36 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
36}; 37};
37OCP_SYSFS_MAL_DATA() 38OCP_SYSFS_MAL_DATA()
38 39
diff --git a/arch/ppc/platforms/4xx/ibm405gp.c b/arch/ppc/platforms/4xx/ibm405gp.c
index dfd7ef3ba5f8..e5700469a682 100644
--- a/arch/ppc/platforms/4xx/ibm405gp.c
+++ b/arch/ppc/platforms/4xx/ibm405gp.c
@@ -46,6 +46,7 @@ static struct ocp_func_mal_data ibm405gp_mal0_def = {
46 .txde_irq = 13, /* TX Descriptor Error IRQ */ 46 .txde_irq = 13, /* TX Descriptor Error IRQ */
47 .rxde_irq = 14, /* RX Descriptor Error IRQ */ 47 .rxde_irq = 14, /* RX Descriptor Error IRQ */
48 .serr_irq = 10, /* MAL System Error IRQ */ 48 .serr_irq = 10, /* MAL System Error IRQ */
49 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
49}; 50};
50OCP_SYSFS_MAL_DATA() 51OCP_SYSFS_MAL_DATA()
51 52
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c
index 01c8ccbc7214..cd0d00d8e8ee 100644
--- a/arch/ppc/platforms/4xx/ibm405gpr.c
+++ b/arch/ppc/platforms/4xx/ibm405gpr.c
@@ -42,6 +42,7 @@ static struct ocp_func_mal_data ibm405gpr_mal0_def = {
42 .txde_irq = 13, /* TX Descriptor Error IRQ */ 42 .txde_irq = 13, /* TX Descriptor Error IRQ */
43 .rxde_irq = 14, /* RX Descriptor Error IRQ */ 43 .rxde_irq = 14, /* RX Descriptor Error IRQ */
44 .serr_irq = 10, /* MAL System Error IRQ */ 44 .serr_irq = 10, /* MAL System Error IRQ */
45 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
45}; 46};
46OCP_SYSFS_MAL_DATA() 47OCP_SYSFS_MAL_DATA()
47 48
diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c
index 284da01f1ffd..4712de8ff80f 100644
--- a/arch/ppc/platforms/4xx/ibm440ep.c
+++ b/arch/ppc/platforms/4xx/ibm440ep.c
@@ -53,6 +53,7 @@ static struct ocp_func_mal_data ibm440ep_mal0_def = {
53 .txde_irq = 33, /* TX Descriptor Error IRQ */ 53 .txde_irq = 33, /* TX Descriptor Error IRQ */
54 .rxde_irq = 34, /* RX Descriptor Error IRQ */ 54 .rxde_irq = 34, /* RX Descriptor Error IRQ */
55 .serr_irq = 32, /* MAL System Error IRQ */ 55 .serr_irq = 32, /* MAL System Error IRQ */
56 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
56}; 57};
57OCP_SYSFS_MAL_DATA() 58OCP_SYSFS_MAL_DATA()
58 59
diff --git a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c
index 27615ef8309c..d926245e8b3e 100644
--- a/arch/ppc/platforms/4xx/ibm440gp.c
+++ b/arch/ppc/platforms/4xx/ibm440gp.c
@@ -56,6 +56,7 @@ static struct ocp_func_mal_data ibm440gp_mal0_def = {
56 .txde_irq = 33, /* TX Descriptor Error IRQ */ 56 .txde_irq = 33, /* TX Descriptor Error IRQ */
57 .rxde_irq = 34, /* RX Descriptor Error IRQ */ 57 .rxde_irq = 34, /* RX Descriptor Error IRQ */
58 .serr_irq = 32, /* MAL System Error IRQ */ 58 .serr_irq = 32, /* MAL System Error IRQ */
59 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
59}; 60};
60OCP_SYSFS_MAL_DATA() 61OCP_SYSFS_MAL_DATA()
61 62
diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c
index 1f38f42835b4..956f45e4ef97 100644
--- a/arch/ppc/platforms/4xx/ibm440gx.c
+++ b/arch/ppc/platforms/4xx/ibm440gx.c
@@ -84,6 +84,7 @@ static struct ocp_func_mal_data ibm440gx_mal0_def = {
84 .txde_irq = 33, /* TX Descriptor Error IRQ */ 84 .txde_irq = 33, /* TX Descriptor Error IRQ */
85 .rxde_irq = 34, /* RX Descriptor Error IRQ */ 85 .rxde_irq = 34, /* RX Descriptor Error IRQ */
86 .serr_irq = 32, /* MAL System Error IRQ */ 86 .serr_irq = 32, /* MAL System Error IRQ */
87 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
87}; 88};
88OCP_SYSFS_MAL_DATA() 89OCP_SYSFS_MAL_DATA()
89 90
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
index fa3e003a0db9..feb17e41ef69 100644
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ b/arch/ppc/platforms/4xx/ibm440sp.c
@@ -43,6 +43,7 @@ static struct ocp_func_mal_data ibm440sp_mal0_def = {
43 .txde_irq = 34, /* TX Descriptor Error IRQ */ 43 .txde_irq = 34, /* TX Descriptor Error IRQ */
44 .rxde_irq = 35, /* RX Descriptor Error IRQ */ 44 .rxde_irq = 35, /* RX Descriptor Error IRQ */
45 .serr_irq = 33, /* MAL System Error IRQ */ 45 .serr_irq = 33, /* MAL System Error IRQ */
46 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
46}; 47};
47OCP_SYSFS_MAL_DATA() 48OCP_SYSFS_MAL_DATA()
48 49
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.c b/arch/ppc/platforms/4xx/ibmnp405h.c
index ecdc5be6ae28..a477a78f4902 100644
--- a/arch/ppc/platforms/4xx/ibmnp405h.c
+++ b/arch/ppc/platforms/4xx/ibmnp405h.c
@@ -34,7 +34,7 @@ static struct ocp_func_emac_data ibmnp405h_emac1_def = {
34 .zmii_mux = 1, /* ZMII input of this EMAC */ 34 .zmii_mux = 1, /* ZMII input of this EMAC */
35 .mal_idx = 0, /* MAL device index */ 35 .mal_idx = 0, /* MAL device index */
36 .mal_rx_chan = 1, /* MAL rx channel number */ 36 .mal_rx_chan = 1, /* MAL rx channel number */
37 .mal_tx_chan = 1, /* MAL tx channel number */ 37 .mal_tx_chan = 2, /* MAL tx channel number */
38 .wol_irq = 41, /* WOL interrupt number */ 38 .wol_irq = 41, /* WOL interrupt number */
39 .mdio_idx = -1, /* No shared MDIO */ 39 .mdio_idx = -1, /* No shared MDIO */
40 .tah_idx = -1, /* No TAH */ 40 .tah_idx = -1, /* No TAH */
@@ -46,7 +46,7 @@ static struct ocp_func_emac_data ibmnp405h_emac2_def = {
46 .zmii_mux = 2, /* ZMII input of this EMAC */ 46 .zmii_mux = 2, /* ZMII input of this EMAC */
47 .mal_idx = 0, /* MAL device index */ 47 .mal_idx = 0, /* MAL device index */
48 .mal_rx_chan = 2, /* MAL rx channel number */ 48 .mal_rx_chan = 2, /* MAL rx channel number */
49 .mal_tx_chan = 2, /* MAL tx channel number */ 49 .mal_tx_chan = 4, /* MAL tx channel number */
50 .wol_irq = 41, /* WOL interrupt number */ 50 .wol_irq = 41, /* WOL interrupt number */
51 .mdio_idx = -1, /* No shared MDIO */ 51 .mdio_idx = -1, /* No shared MDIO */
52 .tah_idx = -1, /* No TAH */ 52 .tah_idx = -1, /* No TAH */
@@ -58,7 +58,7 @@ static struct ocp_func_emac_data ibmnp405h_emac3_def = {
58 .zmii_mux = 3, /* ZMII input of this EMAC */ 58 .zmii_mux = 3, /* ZMII input of this EMAC */
59 .mal_idx = 0, /* MAL device index */ 59 .mal_idx = 0, /* MAL device index */
60 .mal_rx_chan = 3, /* MAL rx channel number */ 60 .mal_rx_chan = 3, /* MAL rx channel number */
61 .mal_tx_chan = 3, /* MAL tx channel number */ 61 .mal_tx_chan = 6, /* MAL tx channel number */
62 .wol_irq = 41, /* WOL interrupt number */ 62 .wol_irq = 41, /* WOL interrupt number */
63 .mdio_idx = -1, /* No shared MDIO */ 63 .mdio_idx = -1, /* No shared MDIO */
64 .tah_idx = -1, /* No TAH */ 64 .tah_idx = -1, /* No TAH */
@@ -73,6 +73,7 @@ static struct ocp_func_mal_data ibmnp405h_mal0_def = {
73 .txde_irq = 46, /* TX Descriptor Error IRQ */ 73 .txde_irq = 46, /* TX Descriptor Error IRQ */
74 .rxde_irq = 47, /* RX Descriptor Error IRQ */ 74 .rxde_irq = 47, /* RX Descriptor Error IRQ */
75 .serr_irq = 45, /* MAL System Error IRQ */ 75 .serr_irq = 45, /* MAL System Error IRQ */
76 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
76}; 77};
77OCP_SYSFS_MAL_DATA() 78OCP_SYSFS_MAL_DATA()
78 79
diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c
index 874d16bab73c..d90627b68faa 100644
--- a/arch/ppc/platforms/4xx/ibmstb4.c
+++ b/arch/ppc/platforms/4xx/ibmstb4.c
@@ -11,6 +11,7 @@
11 11
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/ocp.h> 13#include <asm/ocp.h>
14#include <asm/ppc4xx_pic.h>
14#include <platforms/4xx/ibmstb4.h> 15#include <platforms/4xx/ibmstb4.h>
15 16
16static struct ocp_func_iic_data ibmstb4_iic0_def = { 17static struct ocp_func_iic_data ibmstb4_iic0_def = {
@@ -72,12 +73,51 @@ struct ocp_def core_ocp[] __initdata = {
72 .irq = IDE0_IRQ, 73 .irq = IDE0_IRQ,
73 .pm = OCP_CPM_NA, 74 .pm = OCP_CPM_NA,
74 }, 75 },
75 { .vendor = OCP_VENDOR_IBM,
76 .function = OCP_FUNC_USB,
77 .paddr = USB0_BASE,
78 .irq = USB0_IRQ,
79 .pm = OCP_CPM_NA,
80 },
81 { .vendor = OCP_VENDOR_INVALID, 76 { .vendor = OCP_VENDOR_INVALID,
82 } 77 }
83}; 78};
79
80/* Polarity and triggering settings for internal interrupt sources */
81struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
82 { .polarity = 0x7fffff01,
83 .triggering = 0x00000000,
84 .ext_irq_mask = 0x0000007e, /* IRQ0 - IRQ5 */
85 }
86};
87
88static struct resource ohci_usb_resources[] = {
89 [0] = {
90 .start = USB0_BASE,
91 .end = USB0_BASE + USB0_SIZE - 1,
92 .flags = IORESOURCE_MEM,
93 },
94 [1] = {
95 .start = USB0_IRQ,
96 .end = USB0_IRQ,
97 .flags = IORESOURCE_IRQ,
98 },
99};
100
101static u64 dma_mask = 0xffffffffULL;
102
103static struct platform_device ohci_usb_device = {
104 .name = "ppc-soc-ohci",
105 .id = 0,
106 .num_resources = ARRAY_SIZE(ohci_usb_resources),
107 .resource = ohci_usb_resources,
108 .dev = {
109 .dma_mask = &dma_mask,
110 .coherent_dma_mask = 0xffffffffULL,
111 }
112};
113
114static struct platform_device *ibmstb4_devs[] __initdata = {
115 &ohci_usb_device,
116};
117
118static int __init
119ibmstb4_platform_add_devices(void)
120{
121 return platform_add_devices(ibmstb4_devs, ARRAY_SIZE(ibmstb4_devs));
122}
123arch_initcall(ibmstb4_platform_add_devices);
diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h
index bcb4b1ee71f2..9f21d4c88a3d 100644
--- a/arch/ppc/platforms/4xx/ibmstb4.h
+++ b/arch/ppc/platforms/4xx/ibmstb4.h
@@ -73,9 +73,9 @@
73#define OPB0_BASE 0x40000000 73#define OPB0_BASE 0x40000000
74#define GPIO0_BASE 0x40060000 74#define GPIO0_BASE 0x40060000
75 75
76#define USB0_BASE 0x40010000
77#define USB0_SIZE 0xA0
76#define USB0_IRQ 18 78#define USB0_IRQ 18
77#define USB0_BASE STB04xxx_MAP_IO_ADDR(0x40010000)
78#define USB0_EXTENT 4096
79 79
80#define IIC_NUMS 2 80#define IIC_NUMS 2
81#define UART_NUMS 3 81#define UART_NUMS 3
diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c
index 95359f748e7b..a38e6f9ef858 100644
--- a/arch/ppc/platforms/4xx/luan.c
+++ b/arch/ppc/platforms/4xx/luan.c
@@ -53,13 +53,6 @@
53#include <syslib/ibm440gx_common.h> 53#include <syslib/ibm440gx_common.h>
54#include <syslib/ibm440sp_common.h> 54#include <syslib/ibm440sp_common.h>
55 55
56/*
57 * This is a horrible kludge, we eventually need to abstract this
58 * generic PHY stuff, so the standard phy mode defines can be
59 * easily used from arch code.
60 */
61#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
62
63bd_t __res; 56bd_t __res;
64 57
65static struct ibm44x_clocks clocks __initdata; 58static struct ibm44x_clocks clocks __initdata;
diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h
index 09b444c87816..bbe7d0766db8 100644
--- a/arch/ppc/platforms/4xx/luan.h
+++ b/arch/ppc/platforms/4xx/luan.h
@@ -55,7 +55,7 @@
55#define STD_UART_OP(num) \ 55#define STD_UART_OP(num) \
56 { 0, BASE_BAUD, 0, UART##num##_INT, \ 56 { 0, BASE_BAUD, 0, UART##num##_INT, \
57 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 57 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
58 iomem_base: UART##num##_IO_BASE, \ 58 iomem_base: (void*)UART##num##_IO_BASE, \
59 io_type: SERIAL_IO_MEM}, 59 io_type: SERIAL_IO_MEM},
60 60
61#define SERIAL_PORT_DFNS \ 61#define SERIAL_PORT_DFNS \
diff --git a/arch/ppc/platforms/4xx/oak.c b/arch/ppc/platforms/4xx/oak.c
deleted file mode 100644
index fa25ee1fa733..000000000000
--- a/arch/ppc/platforms/4xx/oak.c
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 *
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
4 *
5 * Module name: oak.c
6 *
7 * Description:
8 * Architecture- / platform-specific boot-time initialization code for
9 * the IBM PowerPC 403GCX "Oak" evaluation board. Adapted from original
10 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
11 * <dan@net4x.com>.
12 *
13 */
14
15#include <linux/config.h>
16#include <linux/init.h>
17#include <linux/smp.h>
18#include <linux/threads.h>
19#include <linux/param.h>
20#include <linux/string.h>
21#include <linux/initrd.h>
22#include <linux/irq.h>
23#include <linux/seq_file.h>
24
25#include <asm/board.h>
26#include <asm/machdep.h>
27#include <asm/page.h>
28#include <asm/bootinfo.h>
29#include <asm/ppc4xx_pic.h>
30#include <asm/time.h>
31
32#include "oak.h"
33
34/* Function Prototypes */
35
36extern void abort(void);
37
38/* Global Variables */
39
40unsigned char __res[sizeof(bd_t)];
41
42
43/*
44 * void __init oak_init()
45 *
46 * Description:
47 * This routine...
48 *
49 * Input(s):
50 * r3 - Optional pointer to a board information structure.
51 * r4 - Optional pointer to the physical starting address of the init RAM
52 * disk.
53 * r5 - Optional pointer to the physical ending address of the init RAM
54 * disk.
55 * r6 - Optional pointer to the physical starting address of any kernel
56 * command-line parameters.
57 * r7 - Optional pointer to the physical ending address of any kernel
58 * command-line parameters.
59 *
60 * Output(s):
61 * N/A
62 *
63 * Returns:
64 * N/A
65 *
66 */
67void __init
68platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
69 unsigned long r6, unsigned long r7)
70{
71 parse_bootinfo(find_bootinfo());
72
73 /*
74 * If we were passed in a board information, copy it into the
75 * residual data area.
76 */
77 if (r3) {
78 memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t));
79 }
80
81#if defined(CONFIG_BLK_DEV_INITRD)
82 /*
83 * If the init RAM disk has been configured in, and there's a valid
84 * starting address for it, set it up.
85 */
86 if (r4) {
87 initrd_start = r4 + KERNELBASE;
88 initrd_end = r5 + KERNELBASE;
89 }
90#endif /* CONFIG_BLK_DEV_INITRD */
91
92 /* Copy the kernel command line arguments to a safe place. */
93
94 if (r6) {
95 *(char *)(r7 + KERNELBASE) = 0;
96 strcpy(cmd_line, (char *)(r6 + KERNELBASE));
97 }
98
99 /* Initialize machine-dependency vectors */
100
101 ppc_md.setup_arch = oak_setup_arch;
102 ppc_md.show_percpuinfo = oak_show_percpuinfo;
103 ppc_md.irq_canonicalize = NULL;
104 ppc_md.init_IRQ = ppc4xx_pic_init;
105 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
106 ppc_md.init = NULL;
107
108 ppc_md.restart = oak_restart;
109 ppc_md.power_off = oak_power_off;
110 ppc_md.halt = oak_halt;
111
112 ppc_md.time_init = oak_time_init;
113 ppc_md.set_rtc_time = oak_set_rtc_time;
114 ppc_md.get_rtc_time = oak_get_rtc_time;
115 ppc_md.calibrate_decr = oak_calibrate_decr;
116}
117
118/*
119 * Document me.
120 */
121void __init
122oak_setup_arch(void)
123{
124 /* XXX - Implement me */
125}
126
127/*
128 * int oak_show_percpuinfo()
129 *
130 * Description:
131 * This routine pretty-prints the platform's internal CPU and bus clock
132 * frequencies into the buffer for usage in /proc/cpuinfo.
133 *
134 * Input(s):
135 * *buffer - Buffer into which CPU and bus clock frequencies are to be
136 * printed.
137 *
138 * Output(s):
139 * *buffer - Buffer with the CPU and bus clock frequencies.
140 *
141 * Returns:
142 * The number of bytes copied into 'buffer' if OK, otherwise zero or less
143 * on error.
144 */
145int
146oak_show_percpuinfo(struct seq_file *m, int i)
147{
148 bd_t *bp = (bd_t *)__res;
149
150 seq_printf(m, "clock\t\t: %dMHz\n"
151 "bus clock\t\t: %dMHz\n",
152 bp->bi_intfreq / 1000000,
153 bp->bi_busfreq / 1000000);
154
155 return 0;
156}
157
158/*
159 * Document me.
160 */
161void
162oak_restart(char *cmd)
163{
164 abort();
165}
166
167/*
168 * Document me.
169 */
170void
171oak_power_off(void)
172{
173 oak_restart(NULL);
174}
175
176/*
177 * Document me.
178 */
179void
180oak_halt(void)
181{
182 oak_restart(NULL);
183}
184
185/*
186 * Document me.
187 */
188long __init
189oak_time_init(void)
190{
191 /* XXX - Implement me */
192 return 0;
193}
194
195/*
196 * Document me.
197 */
198int __init
199oak_set_rtc_time(unsigned long time)
200{
201 /* XXX - Implement me */
202
203 return (0);
204}
205
206/*
207 * Document me.
208 */
209unsigned long __init
210oak_get_rtc_time(void)
211{
212 /* XXX - Implement me */
213
214 return (0);
215}
216
217/*
218 * void __init oak_calibrate_decr()
219 *
220 * Description:
221 * This routine retrieves the internal processor frequency from the board
222 * information structure, sets up the kernel timer decrementer based on
223 * that value, enables the 403 programmable interval timer (PIT) and sets
224 * it up for auto-reload.
225 *
226 * Input(s):
227 * N/A
228 *
229 * Output(s):
230 * N/A
231 *
232 * Returns:
233 * N/A
234 *
235 */
236void __init
237oak_calibrate_decr(void)
238{
239 unsigned int freq;
240 bd_t *bip = (bd_t *)__res;
241
242 freq = bip->bi_intfreq;
243
244 decrementer_count = freq / HZ;
245 count_period_num = 1;
246 count_period_den = freq;
247
248 /* Enable the PIT and set auto-reload of its value */
249
250 mtspr(SPRN_TCR, TCR_PIE | TCR_ARE);
251
252 /* Clear any pending timer interrupts */
253
254 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS);
255}
diff --git a/arch/ppc/platforms/4xx/oak.h b/arch/ppc/platforms/4xx/oak.h
deleted file mode 100644
index 1b86a4c66b04..000000000000
--- a/arch/ppc/platforms/4xx/oak.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 *
3 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
4 *
5 * Module name: oak.h
6 *
7 * Description:
8 * Macros, definitions, and data structures specific to the IBM PowerPC
9 * 403G{A,B,C,CX} "Oak" evaluation board. Anything specific to the pro-
10 * cessor itself is defined elsewhere.
11 *
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_OAK_H__
16#define __ASM_OAK_H__
17
18/* We have an IBM 403G{A,B,C,CX} core */
19#include <asm/ibm403.h>
20
21#define _IO_BASE 0
22#define _ISA_MEM_BASE 0
23#define PCI_DRAM_OFFSET 0
24
25/* Memory map for the "Oak" evaluation board */
26
27#define PPC403SPU_IO_BASE 0x40000000 /* 403 On-chip serial port */
28#define PPC403SPU_IO_SIZE 0x00000008
29#define OAKSERIAL_IO_BASE 0x7E000000 /* NS16550DV serial port */
30#define OAKSERIAL_IO_SIZE 0x00000008
31#define OAKNET_IO_BASE 0xF4000000 /* NS83902AV Ethernet */
32#define OAKNET_IO_SIZE 0x00000040
33#define OAKPROM_IO_BASE 0xFFFE0000 /* AMD 29F010 Flash ROM */
34#define OAKPROM_IO_SIZE 0x00020000
35
36
37/* Interrupt assignments fixed by the hardware implementation */
38
39/* This is annoying kbuild-2.4 problem. -- Tom */
40
41#define PPC403SPU_RX_INT 4 /* AIC_INT4 */
42#define PPC403SPU_TX_INT 5 /* AIC_INT5 */
43#define OAKNET_INT 27 /* AIC_INT27 */
44#define OAKSERIAL_INT 28 /* AIC_INT28 */
45
46#ifndef __ASSEMBLY__
47/*
48 * Data structure defining board information maintained by the boot
49 * ROM on IBM's "Oak" evaluation board. An effort has been made to
50 * keep the field names consistent with the 8xx 'bd_t' board info
51 * structures.
52 */
53
54typedef struct board_info {
55 unsigned char bi_s_version[4]; /* Version of this structure */
56 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
57 unsigned int bi_memsize; /* DRAM installed, in bytes */
58 unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
59 unsigned int bi_intfreq; /* Processor speed, in Hz */
60 unsigned int bi_busfreq; /* Bus speed, in Hz */
61} bd_t;
62
63#ifdef __cplusplus
64extern "C" {
65#endif
66
67extern void oak_init(unsigned long r3,
68 unsigned long ird_start,
69 unsigned long ird_end,
70 unsigned long cline_start,
71 unsigned long cline_end);
72extern void oak_setup_arch(void);
73extern int oak_setup_residual(char *buffer);
74extern void oak_init_IRQ(void);
75extern int oak_get_irq(struct pt_regs *regs);
76extern void oak_restart(char *cmd);
77extern void oak_power_off(void);
78extern void oak_halt(void);
79extern void oak_time_init(void);
80extern int oak_set_rtc_time(unsigned long now);
81extern unsigned long oak_get_rtc_time(void);
82extern void oak_calibrate_decr(void);
83
84#ifdef __cplusplus
85}
86#endif
87
88/* Some 4xx parts use a different timebase frequency from the internal clock.
89*/
90#define bi_tbfreq bi_intfreq
91
92#define PPC4xx_MACHINE_NAME "IBM Oak"
93
94#endif /* !__ASSEMBLY__ */
95#endif /* __ASM_OAK_H__ */
96#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/oak_setup.h b/arch/ppc/platforms/4xx/oak_setup.h
deleted file mode 100644
index 8648bd084df8..000000000000
--- a/arch/ppc/platforms/4xx/oak_setup.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 *
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
4 *
5 * Module name: oak_setup.h
6 *
7 * Description:
8 * Architecture- / platform-specific boot-time initialization code for
9 * the IBM PowerPC 403GCX "Oak" evaluation board. Adapted from original
10 * code by Gary Thomas, Cort Dougan <cort@cs.nmt.edu>, and Dan Malek
11 * <dan@netx4.com>.
12 *
13 */
14
15#ifndef __OAK_SETUP_H__
16#define __OAK_SETUP_H__
17
18#include <asm/ptrace.h>
19#include <asm/board.h>
20
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26extern unsigned char __res[sizeof(bd_t)];
27
28extern void oak_init(unsigned long r3,
29 unsigned long ird_start,
30 unsigned long ird_end,
31 unsigned long cline_start,
32 unsigned long cline_end);
33extern void oak_setup_arch(void);
34extern int oak_setup_residual(char *buffer);
35extern void oak_init_IRQ(void);
36extern int oak_get_irq(struct pt_regs *regs);
37extern void oak_restart(char *cmd);
38extern void oak_power_off(void);
39extern void oak_halt(void);
40extern void oak_time_init(void);
41extern int oak_set_rtc_time(unsigned long now);
42extern unsigned long oak_get_rtc_time(void);
43extern void oak_calibrate_decr(void);
44
45
46#ifdef __cplusplus
47}
48#endif
49
50#endif /* __OAK_SETUP_H__ */
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index 8fc34a344769..80028df1b445 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -53,13 +53,6 @@
53#include <syslib/gen550.h> 53#include <syslib/gen550.h>
54#include <syslib/ibm440gx_common.h> 54#include <syslib/ibm440gx_common.h>
55 55
56/*
57 * This is a horrible kludge, we eventually need to abstract this
58 * generic PHY stuff, so the standard phy mode defines can be
59 * easily used from arch code.
60 */
61#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
62
63bd_t __res; 56bd_t __res;
64 57
65static struct ibm44x_clocks clocks __initdata; 58static struct ibm44x_clocks clocks __initdata;
diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c
index 2f5e410afbc5..bee8b4ac8afd 100644
--- a/arch/ppc/platforms/4xx/redwood5.c
+++ b/arch/ppc/platforms/4xx/redwood5.c
@@ -18,6 +18,19 @@
18#include <linux/ioport.h> 18#include <linux/ioport.h>
19#include <asm/io.h> 19#include <asm/io.h>
20#include <asm/machdep.h> 20#include <asm/machdep.h>
21#include <asm/ppc4xx_pic.h>
22
23/*
24 * Define external IRQ senses and polarities.
25 */
26unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
27 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
28 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
29 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
30 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
31 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
32 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
33};
21 34
22static struct resource smc91x_resources[] = { 35static struct resource smc91x_resources[] = {
23 [0] = { 36 [0] = {
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c
index ddd04d4c1ea9..b38a851a64ec 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.c
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.c
@@ -62,9 +62,29 @@ extern unsigned long total_memory; /* in mm/init */
62unsigned char __res[sizeof (bd_t)]; 62unsigned char __res[sizeof (bd_t)];
63 63
64#ifdef CONFIG_PCI 64#ifdef CONFIG_PCI
65#error "PCI is not supported" 65int
66/* NEED mpc83xx_map_irq & mpc83xx_exclude_device 66mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
67 see platforms/85xx/mpc85xx_ads_common.c */ 67{
68 static char pci_irq_table[][4] =
69 /*
70 * PCI IDSEL/INTPIN->INTLINE
71 * A B C D
72 */
73 {
74 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */
75 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */
76 {PIRQD, PIRQA, PIRQB, PIRQC} /* idsel 0x13 */
77 };
78
79 const long min_idsel = 0x11, max_idsel = 0x13, irqs_per_slot = 4;
80 return PCI_IRQ_TABLE_LOOKUP;
81}
82
83int
84mpc83xx_exclude_device(u_char bus, u_char devfn)
85{
86 return PCIBIOS_SUCCESSFUL;
87}
68#endif /* CONFIG_PCI */ 88#endif /* CONFIG_PCI */
69 89
70/* ************************************************************************ 90/* ************************************************************************
@@ -88,7 +108,7 @@ mpc834x_sys_setup_arch(void)
88 108
89#ifdef CONFIG_PCI 109#ifdef CONFIG_PCI
90 /* setup PCI host bridges */ 110 /* setup PCI host bridges */
91 mpc83xx_sys_setup_hose(); 111 mpc83xx_setup_hose();
92#endif 112#endif
93 mpc83xx_early_serial_map(); 113 mpc83xx_early_serial_map();
94 114
@@ -175,10 +195,17 @@ mpc834x_sys_init_IRQ(void)
175 IRQ_SENSE_LEVEL, /* EXT 1 */ 195 IRQ_SENSE_LEVEL, /* EXT 1 */
176 IRQ_SENSE_LEVEL, /* EXT 2 */ 196 IRQ_SENSE_LEVEL, /* EXT 2 */
177 0, /* EXT 3 */ 197 0, /* EXT 3 */
198#ifdef CONFIG_PCI
199 IRQ_SENSE_LEVEL, /* EXT 4 */
200 IRQ_SENSE_LEVEL, /* EXT 5 */
201 IRQ_SENSE_LEVEL, /* EXT 6 */
202 IRQ_SENSE_LEVEL, /* EXT 7 */
203#else
178 0, /* EXT 4 */ 204 0, /* EXT 4 */
179 0, /* EXT 5 */ 205 0, /* EXT 5 */
180 0, /* EXT 6 */ 206 0, /* EXT 6 */
181 0, /* EXT 7 */ 207 0, /* EXT 7 */
208#endif
182 }; 209 };
183 210
184 ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8); 211 ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8);
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h
index a2f6e49d7151..1584cd77a9ef 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.h
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.h
@@ -26,7 +26,7 @@
26#define VIRT_IMMRBAR ((uint)0xfe000000) 26#define VIRT_IMMRBAR ((uint)0xfe000000)
27 27
28#define BCSR_PHYS_ADDR ((uint)0xf8000000) 28#define BCSR_PHYS_ADDR ((uint)0xf8000000)
29#define BCSR_SIZE ((uint)(32 * 1024)) 29#define BCSR_SIZE ((uint)(128 * 1024))
30 30
31#define BCSR_MISC_REG2_OFF 0x07 31#define BCSR_MISC_REG2_OFF 0x07
32#define BCSR_MISC_REG2_PORESET 0x01 32#define BCSR_MISC_REG2_PORESET 0x01
@@ -34,23 +34,25 @@
34#define BCSR_MISC_REG3_OFF 0x08 34#define BCSR_MISC_REG3_OFF 0x08
35#define BCSR_MISC_REG3_CNFLOCK 0x80 35#define BCSR_MISC_REG3_CNFLOCK 0x80
36 36
37#ifdef CONFIG_PCI 37#define PIRQA MPC83xx_IRQ_EXT4
38/* PCI interrupt controller */ 38#define PIRQB MPC83xx_IRQ_EXT5
39#define PIRQA MPC83xx_IRQ_IRQ4 39#define PIRQC MPC83xx_IRQ_EXT6
40#define PIRQB MPC83xx_IRQ_IRQ5 40#define PIRQD MPC83xx_IRQ_EXT7
41#define PIRQC MPC83xx_IRQ_IRQ6 41
42#define PIRQD MPC83xx_IRQ_IRQ7 42#define MPC83xx_PCI1_LOWER_IO 0x00000000
43 43#define MPC83xx_PCI1_UPPER_IO 0x00ffffff
44#define MPC834x_SYS_PCI1_LOWER_IO 0x00000000 44#define MPC83xx_PCI1_LOWER_MEM 0x80000000
45#define MPC834x_SYS_PCI1_UPPER_IO 0x00ffffff 45#define MPC83xx_PCI1_UPPER_MEM 0x9fffffff
46 46#define MPC83xx_PCI1_IO_BASE 0xe2000000
47#define MPC834x_SYS_PCI1_LOWER_MEM 0x80000000 47#define MPC83xx_PCI1_MEM_OFFSET 0x00000000
48#define MPC834x_SYS_PCI1_UPPER_MEM 0x9fffffff 48#define MPC83xx_PCI1_IO_SIZE 0x01000000
49 49
50#define MPC834x_SYS_PCI1_IO_BASE 0xe2000000 50#define MPC83xx_PCI2_LOWER_IO 0x00000000
51#define MPC834x_SYS_PCI1_MEM_OFFSET 0x00000000 51#define MPC83xx_PCI2_UPPER_IO 0x00ffffff
52 52#define MPC83xx_PCI2_LOWER_MEM 0xa0000000
53#define MPC834x_SYS_PCI1_IO_SIZE 0x01000000 53#define MPC83xx_PCI2_UPPER_MEM 0xbfffffff
54#endif /* CONFIG_PCI */ 54#define MPC83xx_PCI2_IO_BASE 0xe3000000
55#define MPC83xx_PCI2_MEM_OFFSET 0x00000000
56#define MPC83xx_PCI2_IO_SIZE 0x01000000
55 57
56#endif /* __MACH_MPC83XX_SYS_H__ */ 58#endif /* __MACH_MPC83XX_SYS_H__ */
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
index 5488a053f415..ff7452e5d8e5 100644
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -21,22 +21,17 @@ obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o
21endif 21endif
22obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o 22obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o
23obj-$(CONFIG_PREP_RESIDUAL) += residual.o 23obj-$(CONFIG_PREP_RESIDUAL) += residual.o
24obj-$(CONFIG_ADIR) += adir_setup.o adir_pic.o adir_pci.o
25obj-$(CONFIG_PQ2ADS) += pq2ads.o 24obj-$(CONFIG_PQ2ADS) += pq2ads.o
26obj-$(CONFIG_TQM8260) += tqm8260_setup.o 25obj-$(CONFIG_TQM8260) += tqm8260_setup.o
27obj-$(CONFIG_CPCI690) += cpci690.o 26obj-$(CONFIG_CPCI690) += cpci690.o
28obj-$(CONFIG_EV64260) += ev64260.o 27obj-$(CONFIG_EV64260) += ev64260.o
29obj-$(CONFIG_CHESTNUT) += chestnut.o 28obj-$(CONFIG_CHESTNUT) += chestnut.o
30obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o 29obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o
31obj-$(CONFIG_K2) += k2.o
32obj-$(CONFIG_LOPEC) += lopec.o 30obj-$(CONFIG_LOPEC) += lopec.o
33obj-$(CONFIG_KATANA) += katana.o 31obj-$(CONFIG_KATANA) += katana.o
34obj-$(CONFIG_HDPU) += hdpu.o 32obj-$(CONFIG_HDPU) += hdpu.o
35obj-$(CONFIG_MCPN765) += mcpn765.o
36obj-$(CONFIG_MENF1) += menf1_setup.o menf1_pci.o
37obj-$(CONFIG_MVME5100) += mvme5100.o 33obj-$(CONFIG_MVME5100) += mvme5100.o
38obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o 34obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o
39obj-$(CONFIG_PCORE) += pcore.o
40obj-$(CONFIG_POWERPMC250) += powerpmc250.o 35obj-$(CONFIG_POWERPMC250) += powerpmc250.o
41obj-$(CONFIG_PPLUS) += pplus.o 36obj-$(CONFIG_PPLUS) += pplus.o
42obj-$(CONFIG_PRPMC750) += prpmc750.o 37obj-$(CONFIG_PRPMC750) += prpmc750.o
@@ -46,6 +41,7 @@ obj-$(CONFIG_SANDPOINT) += sandpoint.o
46obj-$(CONFIG_SBC82xx) += sbc82xx.o 41obj-$(CONFIG_SBC82xx) += sbc82xx.o
47obj-$(CONFIG_SPRUCE) += spruce.o 42obj-$(CONFIG_SPRUCE) += spruce.o
48obj-$(CONFIG_LITE5200) += lite5200.o 43obj-$(CONFIG_LITE5200) += lite5200.o
44obj-$(CONFIG_EV64360) += ev64360.o
49 45
50ifeq ($(CONFIG_SMP),y) 46ifeq ($(CONFIG_SMP),y)
51obj-$(CONFIG_PPC_PMAC) += pmac_smp.o 47obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
diff --git a/arch/ppc/platforms/adir.h b/arch/ppc/platforms/adir.h
deleted file mode 100644
index 13a748b46956..000000000000
--- a/arch/ppc/platforms/adir.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * arch/ppc/platforms/adir.h
3 *
4 * Definitions for SBS Adirondack board support
5 *
6 * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
7 */
8
9#ifndef __PPC_PLATFORMS_ADIR_H
10#define __PPC_PLATFORMS_ADIR_H
11
12/*
13 * SBS Adirondack definitions
14 */
15
16/* PPC physical address space layout. We use the one set up by the firmware. */
17#define ADIR_PCI32_MEM_BASE 0x80000000
18#define ADIR_PCI32_MEM_SIZE 0x20000000
19#define ADIR_PCI64_MEM_BASE 0xA0000000
20#define ADIR_PCI64_MEM_SIZE 0x20000000
21#define ADIR_PCI32_IO_BASE 0xC0000000
22#define ADIR_PCI32_IO_SIZE 0x10000000
23#define ADIR_PCI64_IO_BASE 0xD0000000
24#define ADIR_PCI64_IO_SIZE 0x10000000
25#define ADIR_PCI64_PHB 0xFF400000
26#define ADIR_PCI32_PHB 0xFF500000
27
28#define ADIR_PCI64_CONFIG_ADDR (ADIR_PCI64_PHB + 0x000f8000)
29#define ADIR_PCI64_CONFIG_DATA (ADIR_PCI64_PHB + 0x000f8010)
30
31#define ADIR_PCI32_CONFIG_ADDR (ADIR_PCI32_PHB + 0x000f8000)
32#define ADIR_PCI32_CONFIG_DATA (ADIR_PCI32_PHB + 0x000f8010)
33
34/* System memory as seen from PCI */
35#define ADIR_PCI_SYS_MEM_BASE 0x80000000
36
37/* Static virtual mapping of PCI I/O */
38#define ADIR_PCI32_VIRT_IO_BASE 0xFE000000
39#define ADIR_PCI32_VIRT_IO_SIZE 0x01000000
40#define ADIR_PCI64_VIRT_IO_BASE 0xFF000000
41#define ADIR_PCI64_VIRT_IO_SIZE 0x01000000
42
43/* Registers */
44#define ADIR_NVRAM_RTC_ADDR 0x74
45#define ADIR_NVRAM_RTC_DATA 0x75
46
47#define ADIR_BOARD_ID_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF0)
48#define ADIR_CPLD1REV_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF1)
49#define ADIR_CPLD2REV_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF2)
50#define ADIR_FLASHCTL_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF3)
51#define ADIR_CPC710_STAT_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF4)
52#define ADIR_CLOCK_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF5)
53#define ADIR_GPIO_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF8)
54#define ADIR_MISC_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFF9)
55#define ADIR_LED_REG (ADIR_PCI32_VIRT_IO_BASE + 0x08FFFA)
56
57#define ADIR_CLOCK_REG_PD 0x10
58#define ADIR_CLOCK_REG_SPREAD 0x08
59#define ADIR_CLOCK_REG_SEL133 0x04
60#define ADIR_CLOCK_REG_SEL1 0x02
61#define ADIR_CLOCK_REG_SEL0 0x01
62
63#define ADIR_PROCA_INT_MASK (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF0)
64#define ADIR_PROCB_INT_MASK (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF2)
65#define ADIR_PROCA_INT_STAT (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF4)
66#define ADIR_PROCB_INT_STAT (ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF6)
67
68/* Linux IRQ numbers */
69#define ADIR_IRQ_NONE -1
70#define ADIR_IRQ_SERIAL2 3
71#define ADIR_IRQ_SERIAL1 4
72#define ADIR_IRQ_FDC 6
73#define ADIR_IRQ_PARALLEL 7
74#define ADIR_IRQ_VIA_AUDIO 10
75#define ADIR_IRQ_VIA_USB 11
76#define ADIR_IRQ_IDE0 14
77#define ADIR_IRQ_IDE1 15
78#define ADIR_IRQ_PCI0_INTA 16
79#define ADIR_IRQ_PCI0_INTB 17
80#define ADIR_IRQ_PCI0_INTC 18
81#define ADIR_IRQ_PCI0_INTD 19
82#define ADIR_IRQ_PCI1_INTA 20
83#define ADIR_IRQ_PCI1_INTB 21
84#define ADIR_IRQ_PCI1_INTC 22
85#define ADIR_IRQ_PCI1_INTD 23
86#define ADIR_IRQ_MBSCSI 24 /* motherboard SCSI */
87#define ADIR_IRQ_MBETH1 25 /* motherboard Ethernet 1 */
88#define ADIR_IRQ_MBETH0 26 /* motherboard Ethernet 0 */
89#define ADIR_IRQ_CPC710_INT1 27
90#define ADIR_IRQ_CPC710_INT2 28
91#define ADIR_IRQ_VT82C686_NMI 29
92#define ADIR_IRQ_VT82C686_INTR 30
93#define ADIR_IRQ_INTERPROC 31
94
95#endif /* __PPC_PLATFORMS_ADIR_H */
diff --git a/arch/ppc/platforms/adir_pci.c b/arch/ppc/platforms/adir_pci.c
deleted file mode 100644
index f94ac53e0711..000000000000
--- a/arch/ppc/platforms/adir_pci.c
+++ /dev/null
@@ -1,247 +0,0 @@
1/*
2 * arch/ppc/platforms/adir_pci.c
3 *
4 * PCI support for SBS Adirondack
5 *
6 * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
7 * based on the K2 version by Matt Porter <mporter@mvista.com>
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/pci.h>
13#include <linux/slab.h>
14
15#include <asm/byteorder.h>
16#include <asm/io.h>
17#include <asm/uaccess.h>
18#include <asm/machdep.h>
19#include <asm/pci-bridge.h>
20
21#include <syslib/cpc710.h>
22#include "adir.h"
23
24#undef DEBUG
25#ifdef DEBUG
26#define DBG(x...) printk(x)
27#else
28#define DBG(x...)
29#endif /* DEBUG */
30
31static inline int __init
32adir_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
33{
34#define PCIIRQ(a,b,c,d) {ADIR_IRQ_##a,ADIR_IRQ_##b,ADIR_IRQ_##c,ADIR_IRQ_##d},
35 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
36 /*
37 * The three PCI devices on the motherboard have dedicated lines to the
38 * CPLD interrupt controller, bypassing the standard PCI INTA-D and the
39 * PC interrupt controller. All other PCI devices (slots) have usual
40 * staggered INTA-D lines, resulting in 8 lines total (PCI0 INTA-D and
41 * PCI1 INTA-D). All 8 go to the CPLD interrupt controller. PCI0 INTA-D
42 * also go to the south bridge, so we have the option of taking them
43 * via the CPLD interrupt controller or via the south bridge 8259
44 * 8258 thingy. PCI1 INTA-D can only be taken via the CPLD interrupt
45 * controller. We take all PCI interrupts via the CPLD interrupt
46 * controller as recommended by SBS.
47 *
48 * We also have some monkey business with the PCI devices within the
49 * VT82C686B south bridge itself. This chip actually has 7 functions on
50 * its IDSEL. Function 0 is the actual south bridge, function 1 is IDE,
51 * and function 4 is some special stuff. The other 4 functions are just
52 * regular PCI devices bundled in the chip. 2 and 3 are USB UHCIs and 5
53 * and 6 are audio (not supported on the Adirondack).
54 *
55 * This is where the monkey business begins. PCI devices are supposed
56 * to signal normal PCI interrupts. But the 4 functions in question are
57 * located in the south bridge chip, which is designed with the
58 * assumption that it will be fielding PCI INTA-D interrupts rather
59 * than generating them. Here's what it does. Each of the functions in
60 * question routes its interrupt to one of the IRQs on the 8259 thingy.
61 * Which one? It looks at the Interrupt Line register in the PCI config
62 * space, even though the PCI spec says it's for BIOS/OS interaction
63 * only.
64 *
65 * How do we deal with this? We take these interrupts via 8259 IRQs as
66 * we have to. We return the desired IRQ numbers from this routine when
67 * called for the functions in question. The PCI scan code will then
68 * stick our return value into the Interrupt Line register in the PCI
69 * config space, and the interrupt will actually go there. We identify
70 * these functions within the south bridge IDSEL by their interrupt pin
71 * numbers, as the VT82C686B has 04 in the Interrupt Pin register for
72 * USB and 03 for audio.
73 */
74 if (!hose->index) {
75 static char pci_irq_table[][4] =
76 /*
77 * PCI IDSEL/INTPIN->INTLINE
78 * A B C D
79 */
80 {
81 /* south bridge */ PCIIRQ(IDE0, NONE, VIA_AUDIO, VIA_USB)
82 /* Ethernet 0 */ PCIIRQ(MBETH0, MBETH0, MBETH0, MBETH0)
83 /* PCI0 slot 1 */ PCIIRQ(PCI0_INTB, PCI0_INTC, PCI0_INTD, PCI0_INTA)
84 /* PCI0 slot 2 */ PCIIRQ(PCI0_INTC, PCI0_INTD, PCI0_INTA, PCI0_INTB)
85 /* PCI0 slot 3 */ PCIIRQ(PCI0_INTD, PCI0_INTA, PCI0_INTB, PCI0_INTC)
86 };
87 const long min_idsel = 3, max_idsel = 7, irqs_per_slot = 4;
88 return PCI_IRQ_TABLE_LOOKUP;
89 } else {
90 static char pci_irq_table[][4] =
91 /*
92 * PCI IDSEL/INTPIN->INTLINE
93 * A B C D
94 */
95 {
96 /* Ethernet 1 */ PCIIRQ(MBETH1, MBETH1, MBETH1, MBETH1)
97 /* SCSI */ PCIIRQ(MBSCSI, MBSCSI, MBSCSI, MBSCSI)
98 /* PCI1 slot 1 */ PCIIRQ(PCI1_INTB, PCI1_INTC, PCI1_INTD, PCI1_INTA)
99 /* PCI1 slot 2 */ PCIIRQ(PCI1_INTC, PCI1_INTD, PCI1_INTA, PCI1_INTB)
100 /* PCI1 slot 3 */ PCIIRQ(PCI1_INTD, PCI1_INTA, PCI1_INTB, PCI1_INTC)
101 };
102 const long min_idsel = 3, max_idsel = 7, irqs_per_slot = 4;
103 return PCI_IRQ_TABLE_LOOKUP;
104 }
105#undef PCIIRQ
106}
107
108static void
109adir_pcibios_fixup_resources(struct pci_dev *dev)
110{
111 int i;
112
113 if ((dev->vendor == PCI_VENDOR_ID_IBM) &&
114 (dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64))
115 {
116 DBG("Fixup CPC710 resources\n");
117 for (i=0; i<DEVICE_COUNT_RESOURCE; i++)
118 {
119 dev->resource[i].start = 0;
120 dev->resource[i].end = 0;
121 }
122 }
123}
124
125/*
126 * CPC710 DD3 has an errata causing it to hang the system if a type 0 config
127 * cycle is attempted on its PCI32 interface with a device number > 21.
128 * CPC710's PCI bridges map device numbers 1 through 21 to AD11 through AD31.
129 * Per the PCI spec it MUST accept all other device numbers and do nothing, and
130 * software MUST scan all device numbers without assuming how IDSELs are
131 * mapped. However, as the CPC710 DD3's errata causes such correct scanning
132 * procedure to hang the system, we have no choice but to introduce this hack
133 * of knowingly avoiding device numbers > 21 on PCI0,
134 */
135static int
136adir_exclude_device(u_char bus, u_char devfn)
137{
138 if ((bus == 0) && (PCI_SLOT(devfn) > 21))
139 return PCIBIOS_DEVICE_NOT_FOUND;
140 else
141 return PCIBIOS_SUCCESSFUL;
142}
143
144void adir_find_bridges(void)
145{
146 struct pci_controller *hose_a, *hose_b;
147
148 /* Setup PCI32 hose */
149 hose_a = pcibios_alloc_controller();
150 if (!hose_a)
151 return;
152
153 hose_a->first_busno = 0;
154 hose_a->last_busno = 0xff;
155 hose_a->pci_mem_offset = ADIR_PCI32_MEM_BASE;
156 hose_a->io_space.start = 0;
157 hose_a->io_space.end = ADIR_PCI32_VIRT_IO_SIZE - 1;
158 hose_a->mem_space.start = 0;
159 hose_a->mem_space.end = ADIR_PCI32_MEM_SIZE - 1;
160 hose_a->io_resource.start = 0;
161 hose_a->io_resource.end = ADIR_PCI32_VIRT_IO_SIZE - 1;
162 hose_a->io_resource.flags = IORESOURCE_IO;
163 hose_a->mem_resources[0].start = ADIR_PCI32_MEM_BASE;
164 hose_a->mem_resources[0].end = ADIR_PCI32_MEM_BASE +
165 ADIR_PCI32_MEM_SIZE - 1;
166 hose_a->mem_resources[0].flags = IORESOURCE_MEM;
167 hose_a->io_base_phys = ADIR_PCI32_IO_BASE;
168 hose_a->io_base_virt = (void *) ADIR_PCI32_VIRT_IO_BASE;
169
170 ppc_md.pci_exclude_device = adir_exclude_device;
171 setup_indirect_pci(hose_a, ADIR_PCI32_CONFIG_ADDR,
172 ADIR_PCI32_CONFIG_DATA);
173
174 /* Initialize PCI32 bus registers */
175 early_write_config_byte(hose_a,
176 hose_a->first_busno,
177 PCI_DEVFN(0, 0),
178 CPC710_BUS_NUMBER,
179 hose_a->first_busno);
180 early_write_config_byte(hose_a,
181 hose_a->first_busno,
182 PCI_DEVFN(0, 0),
183 CPC710_SUB_BUS_NUMBER,
184 hose_a->last_busno);
185
186 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
187
188 /* Write out correct max subordinate bus number for hose A */
189 early_write_config_byte(hose_a,
190 hose_a->first_busno,
191 PCI_DEVFN(0, 0),
192 CPC710_SUB_BUS_NUMBER,
193 hose_a->last_busno);
194
195 /* Setup PCI64 hose */
196 hose_b = pcibios_alloc_controller();
197 if (!hose_b)
198 return;
199
200 hose_b->first_busno = hose_a->last_busno + 1;
201 hose_b->last_busno = 0xff;
202 hose_b->pci_mem_offset = ADIR_PCI64_MEM_BASE;
203 hose_b->io_space.start = 0;
204 hose_b->io_space.end = ADIR_PCI64_VIRT_IO_SIZE - 1;
205 hose_b->mem_space.start = 0;
206 hose_b->mem_space.end = ADIR_PCI64_MEM_SIZE - 1;
207 hose_b->io_resource.start = 0;
208 hose_b->io_resource.end = ADIR_PCI64_VIRT_IO_SIZE - 1;
209 hose_b->io_resource.flags = IORESOURCE_IO;
210 hose_b->mem_resources[0].start = ADIR_PCI64_MEM_BASE;
211 hose_b->mem_resources[0].end = ADIR_PCI64_MEM_BASE +
212 ADIR_PCI64_MEM_SIZE - 1;
213 hose_b->mem_resources[0].flags = IORESOURCE_MEM;
214 hose_b->io_base_phys = ADIR_PCI64_IO_BASE;
215 hose_b->io_base_virt = (void *) ADIR_PCI64_VIRT_IO_BASE;
216
217 setup_indirect_pci(hose_b, ADIR_PCI64_CONFIG_ADDR,
218 ADIR_PCI64_CONFIG_DATA);
219
220 /* Initialize PCI64 bus registers */
221 early_write_config_byte(hose_b,
222 0,
223 PCI_DEVFN(0, 0),
224 CPC710_SUB_BUS_NUMBER,
225 0xff);
226
227 early_write_config_byte(hose_b,
228 0,
229 PCI_DEVFN(0, 0),
230 CPC710_BUS_NUMBER,
231 hose_b->first_busno);
232
233 hose_b->last_busno = pciauto_bus_scan(hose_b,
234 hose_b->first_busno);
235
236 /* Write out correct max subordinate bus number for hose B */
237 early_write_config_byte(hose_b,
238 hose_b->first_busno,
239 PCI_DEVFN(0, 0),
240 CPC710_SUB_BUS_NUMBER,
241 hose_b->last_busno);
242
243 ppc_md.pcibios_fixup = NULL;
244 ppc_md.pcibios_fixup_resources = adir_pcibios_fixup_resources;
245 ppc_md.pci_swizzle = common_swizzle;
246 ppc_md.pci_map_irq = adir_map_irq;
247}
diff --git a/arch/ppc/platforms/adir_pic.c b/arch/ppc/platforms/adir_pic.c
deleted file mode 100644
index 9947cba52af5..000000000000
--- a/arch/ppc/platforms/adir_pic.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 * arch/ppc/platforms/adir_pic.c
3 *
4 * Interrupt controller support for SBS Adirondack
5 *
6 * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
7 * based on the K2 and SCM versions by Matt Porter <mporter@mvista.com>
8 */
9
10#include <linux/stddef.h>
11#include <linux/init.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/interrupt.h>
15
16#include <asm/io.h>
17#include <asm/i8259.h>
18#include "adir.h"
19
20static void adir_onboard_pic_enable(unsigned int irq);
21static void adir_onboard_pic_disable(unsigned int irq);
22
23__init static void
24adir_onboard_pic_init(void)
25{
26 volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK;
27
28 /* Disable all Adirondack onboard interrupts */
29 out_be16(maskreg, 0xFFFF);
30}
31
32static int
33adir_onboard_pic_get_irq(void)
34{
35 volatile u_short *statreg = (volatile u_short *) ADIR_PROCA_INT_STAT;
36 int irq;
37 u_short int_status, int_test;
38
39 int_status = in_be16(statreg);
40 for (irq = 0, int_test = 1; irq < 16; irq++, int_test <<= 1) {
41 if (int_status & int_test)
42 break;
43 }
44
45 if (irq == 16)
46 return -1;
47
48 return (irq+16);
49}
50
51static void
52adir_onboard_pic_enable(unsigned int irq)
53{
54 volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK;
55
56 /* Change irq to Adirondack onboard native value */
57 irq -= 16;
58
59 /* Enable requested irq number */
60 out_be16(maskreg, in_be16(maskreg) & ~(1 << irq));
61}
62
63static void
64adir_onboard_pic_disable(unsigned int irq)
65{
66 volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK;
67
68 /* Change irq to Adirondack onboard native value */
69 irq -= 16;
70
71 /* Disable requested irq number */
72 out_be16(maskreg, in_be16(maskreg) | (1 << irq));
73}
74
75static struct hw_interrupt_type adir_onboard_pic = {
76 " ADIR PIC ",
77 NULL,
78 NULL,
79 adir_onboard_pic_enable, /* unmask */
80 adir_onboard_pic_disable, /* mask */
81 adir_onboard_pic_disable, /* mask and ack */
82 NULL,
83 NULL
84};
85
86static struct irqaction noop_action = {
87 .handler = no_action,
88 .flags = SA_INTERRUPT,
89 .mask = CPU_MASK_NONE,
90 .name = "82c59 primary cascade",
91};
92
93/*
94 * Linux interrupt values are assigned as follows:
95 *
96 * 0-15 VT82C686 8259 interrupts
97 * 16-31 Adirondack CPLD interrupts
98 */
99__init void
100adir_init_IRQ(void)
101{
102 int i;
103
104 /* Initialize the cascaded 8259's on the VT82C686 */
105 for (i=0; i<16; i++)
106 irq_desc[i].handler = &i8259_pic;
107 i8259_init(NULL);
108
109 /* Initialize Adirondack CPLD PIC and enable 8259 interrupt cascade */
110 for (i=16; i<32; i++)
111 irq_desc[i].handler = &adir_onboard_pic;
112 adir_onboard_pic_init();
113
114 /* Enable 8259 interrupt cascade */
115 setup_irq(ADIR_IRQ_VT82C686_INTR, &noop_action);
116}
117
118int
119adir_get_irq(struct pt_regs *regs)
120{
121 int irq;
122
123 if ((irq = adir_onboard_pic_get_irq()) < 0)
124 return irq;
125
126 if (irq == ADIR_IRQ_VT82C686_INTR)
127 irq = i8259_irq(regs);
128
129 return irq;
130}
diff --git a/arch/ppc/platforms/adir_setup.c b/arch/ppc/platforms/adir_setup.c
deleted file mode 100644
index 6a6754ee0617..000000000000
--- a/arch/ppc/platforms/adir_setup.c
+++ /dev/null
@@ -1,210 +0,0 @@
1/*
2 * arch/ppc/platforms/adir_setup.c
3 *
4 * Board setup routines for SBS Adirondack
5 *
6 * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
7 * based on the K2 version by Matt Porter <mporter@mvista.com>
8 */
9
10#include <linux/config.h>
11#include <linux/stddef.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/errno.h>
15#include <linux/reboot.h>
16#include <linux/pci.h>
17#include <linux/kdev_t.h>
18#include <linux/types.h>
19#include <linux/major.h>
20#include <linux/initrd.h>
21#include <linux/console.h>
22#include <linux/delay.h>
23#include <linux/ide.h>
24#include <linux/seq_file.h>
25#include <linux/root_dev.h>
26
27#include <asm/system.h>
28#include <asm/pgtable.h>
29#include <asm/page.h>
30#include <asm/dma.h>
31#include <asm/io.h>
32#include <asm/machdep.h>
33#include <asm/time.h>
34#include <asm/todc.h>
35#include <asm/bootinfo.h>
36
37#include "adir.h"
38
39extern void adir_init_IRQ(void);
40extern int adir_get_irq(struct pt_regs *);
41extern void adir_find_bridges(void);
42extern unsigned long loops_per_jiffy;
43
44static unsigned int cpu_750cx[16] = {
45 5, 15, 14, 0, 4, 13, 0, 9, 6, 11, 8, 10, 16, 12, 7, 0
46};
47
48static int
49adir_get_bus_speed(void)
50{
51 if (!(*((u_char *) ADIR_CLOCK_REG) & ADIR_CLOCK_REG_SEL133))
52 return 100000000;
53 else
54 return 133333333;
55}
56
57static int
58adir_get_cpu_speed(void)
59{
60 unsigned long hid1;
61 int cpu_speed;
62
63 hid1 = mfspr(SPRN_HID1) >> 28;
64
65 hid1 = cpu_750cx[hid1];
66
67 cpu_speed = adir_get_bus_speed()*hid1/2;
68 return cpu_speed;
69}
70
71static void __init
72adir_calibrate_decr(void)
73{
74 int freq, divisor = 4;
75
76 /* determine processor bus speed */
77 freq = adir_get_bus_speed();
78 tb_ticks_per_jiffy = freq / HZ / divisor;
79 tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
80}
81
82static int
83adir_show_cpuinfo(struct seq_file *m)
84{
85 seq_printf(m, "vendor\t\t: SBS\n");
86 seq_printf(m, "machine\t\t: Adirondack\n");
87 seq_printf(m, "cpu speed\t: %dMhz\n", adir_get_cpu_speed()/1000000);
88 seq_printf(m, "bus speed\t: %dMhz\n", adir_get_bus_speed()/1000000);
89 seq_printf(m, "memory type\t: SDRAM\n");
90
91 return 0;
92}
93
94extern char cmd_line[];
95
96TODC_ALLOC();
97
98static void __init
99adir_setup_arch(void)
100{
101 unsigned int cpu;
102
103 /* Setup TODC access */
104 TODC_INIT(TODC_TYPE_MC146818, ADIR_NVRAM_RTC_ADDR, 0,
105 ADIR_NVRAM_RTC_DATA, 8);
106
107 /* init to some ~sane value until calibrate_delay() runs */
108 loops_per_jiffy = 50000000/HZ;
109
110 /* Setup PCI host bridges */
111 adir_find_bridges();
112
113#ifdef CONFIG_BLK_DEV_INITRD
114 if (initrd_start)
115 ROOT_DEV = Root_RAM0;
116 else
117#endif
118#ifdef CONFIG_ROOT_NFS
119 ROOT_DEV = Root_NFS;
120#else
121 ROOT_DEV = Root_SDA1;
122#endif
123
124 /* Identify the system */
125 printk("System Identification: SBS Adirondack - PowerPC 750CXe @ %d Mhz\n", adir_get_cpu_speed()/1000000);
126 printk("SBS Adirondack port (C) 2001 SBS Technologies, Inc.\n");
127
128 /* Identify the CPU manufacturer */
129 cpu = mfspr(SPRN_PVR);
130 printk("CPU manufacturer: IBM [rev=%04x]\n", (cpu & 0xffff));
131}
132
133static void
134adir_restart(char *cmd)
135{
136 local_irq_disable();
137 /* SRR0 has system reset vector, SRR1 has default MSR value */
138 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
139 __asm__ __volatile__
140 ("lis 3,0xfff0\n\t"
141 "ori 3,3,0x0100\n\t"
142 "mtspr 26,3\n\t"
143 "li 3,0\n\t"
144 "mtspr 27,3\n\t"
145 "rfi\n\t");
146 for(;;);
147}
148
149static void
150adir_power_off(void)
151{
152 for(;;);
153}
154
155static void
156adir_halt(void)
157{
158 adir_restart(NULL);
159}
160
161static unsigned long __init
162adir_find_end_of_memory(void)
163{
164 return boot_mem_size;
165}
166
167static void __init
168adir_map_io(void)
169{
170 io_block_mapping(ADIR_PCI32_VIRT_IO_BASE, ADIR_PCI32_IO_BASE,
171 ADIR_PCI32_VIRT_IO_SIZE, _PAGE_IO);
172 io_block_mapping(ADIR_PCI64_VIRT_IO_BASE, ADIR_PCI64_IO_BASE,
173 ADIR_PCI64_VIRT_IO_SIZE, _PAGE_IO);
174}
175
176void __init
177platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
178 unsigned long r6, unsigned long r7)
179{
180 /*
181 * On the Adirondack we use bi_recs and pass the pointer to them in R3.
182 */
183 parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
184
185 /* Remember, isa_io_base is virtual but isa_mem_base is physical! */
186 isa_io_base = ADIR_PCI32_VIRT_IO_BASE;
187 isa_mem_base = ADIR_PCI32_MEM_BASE;
188 pci_dram_offset = ADIR_PCI_SYS_MEM_BASE;
189
190 ppc_md.setup_arch = adir_setup_arch;
191 ppc_md.show_cpuinfo = adir_show_cpuinfo;
192 ppc_md.irq_canonicalize = NULL;
193 ppc_md.init_IRQ = adir_init_IRQ;
194 ppc_md.get_irq = adir_get_irq;
195 ppc_md.init = NULL;
196
197 ppc_md.find_end_of_memory = adir_find_end_of_memory;
198 ppc_md.setup_io_mappings = adir_map_io;
199
200 ppc_md.restart = adir_restart;
201 ppc_md.power_off = adir_power_off;
202 ppc_md.halt = adir_halt;
203
204 ppc_md.time_init = todc_time_init;
205 ppc_md.set_rtc_time = todc_set_rtc_time;
206 ppc_md.get_rtc_time = todc_get_rtc_time;
207 ppc_md.nvram_read_val = todc_mc146818_read_val;
208 ppc_md.nvram_write_val = todc_mc146818_write_val;
209 ppc_md.calibrate_decr = adir_calibrate_decr;
210}
diff --git a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c
index 507870c9a97a..f64ac2acb603 100644
--- a/arch/ppc/platforms/cpci690.c
+++ b/arch/ppc/platforms/cpci690.c
@@ -35,11 +35,7 @@
35#define SET_PCI_IDE_NATIVE 35#define SET_PCI_IDE_NATIVE
36 36
37static struct mv64x60_handle bh; 37static struct mv64x60_handle bh;
38static u32 cpci690_br_base; 38static void __iomem *cpci690_br_base;
39
40static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
41 18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
42};
43 39
44TODC_ALLOC(); 40TODC_ALLOC();
45 41
@@ -55,7 +51,7 @@ cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
55 * A B C D 51 * A B C D
56 */ 52 */
57 { 53 {
58 { 90, 91, 88, 89}, /* IDSEL 30/20 - Sentinel */ 54 { 90, 91, 88, 89 }, /* IDSEL 30/20 - Sentinel */
59 }; 55 };
60 56
61 const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4; 57 const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4;
@@ -67,9 +63,9 @@ cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
67 * A B C D 63 * A B C D
68 */ 64 */
69 { 65 {
70 { 93, 94, 95, 92}, /* IDSEL 28/18 - PMC slot 2 */ 66 { 93, 94, 95, 92 }, /* IDSEL 28/18 - PMC slot 2 */
71 { 0, 0, 0, 0}, /* IDSEL 29/19 - Not used */ 67 { 0, 0, 0, 0 }, /* IDSEL 29/19 - Not used */
72 { 94, 95, 92, 93}, /* IDSEL 30/20 - PMC slot 1 */ 68 { 94, 95, 92, 93 }, /* IDSEL 30/20 - PMC slot 1 */
73 }; 69 };
74 70
75 const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4; 71 const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4;
@@ -77,68 +73,29 @@ cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
77 } 73 }
78} 74}
79 75
80static int 76#define GB (1024UL * 1024UL * 1024UL)
81cpci690_get_cpu_speed(void)
82{
83 unsigned long hid1;
84 77
85 hid1 = mfspr(SPRN_HID1) >> 28; 78static u32
86 return CPCI690_BUS_FREQ * cpu_7xx[hid1]/2; 79cpci690_get_bus_freq(void)
80{
81 if (boot_mem_size >= (1*GB)) /* bus speed based on mem size */
82 return 100000000;
83 else
84 return 133333333;
87} 85}
88 86
89#define KB (1024UL) 87static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
90#define MB (1024UL * KB) 88 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/
91#define GB (1024UL * MB) 89 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/
90};
92 91
93unsigned long __init 92static int
94cpci690_find_end_of_memory(void) 93cpci690_get_cpu_freq(void)
95{ 94{
96 u32 mem_ctlr_size; 95 unsigned long pll_cfg;
97 static u32 board_size; 96
98 static u8 first_time = 1; 97 pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
99 98 return cpci690_get_bus_freq() * cpu_750xx[pll_cfg]/2;
100 if (first_time) {
101 /* Using cpci690_set_bat() mapping ==> virt addr == phys addr */
102 switch (in_8((u8 *) (cpci690_br_base +
103 CPCI690_BR_MEM_CTLR)) & 0x07) {
104 case 0x01:
105 board_size = 256*MB;
106 break;
107 case 0x02:
108 board_size = 512*MB;
109 break;
110 case 0x03:
111 board_size = 768*MB;
112 break;
113 case 0x04:
114 board_size = 1*GB;
115 break;
116 case 0x05:
117 board_size = 1*GB + 512*MB;
118 break;
119 case 0x06:
120 board_size = 2*GB;
121 break;
122 default:
123 board_size = 0xffffffff; /* use mem ctlr size */
124 } /* switch */
125
126 mem_ctlr_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
127 MV64x60_TYPE_GT64260A);
128
129 /* Check that mem ctlr & board reg agree. If not, pick MIN. */
130 if (board_size != mem_ctlr_size) {
131 printk(KERN_WARNING "Board register & memory controller"
132 "mem size disagree (board reg: 0x%lx, "
133 "mem ctlr: 0x%lx)\n",
134 (ulong)board_size, (ulong)mem_ctlr_size);
135 board_size = min(board_size, mem_ctlr_size);
136 }
137
138 first_time = 0;
139 } /* if */
140
141 return board_size;
142} 99}
143 100
144static void __init 101static void __init
@@ -228,7 +185,7 @@ cpci690_setup_peripherals(void)
228 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE, 185 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE,
229 CPCI690_BR_SIZE, 0); 186 CPCI690_BR_SIZE, 0);
230 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); 187 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
231 cpci690_br_base = (u32)ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE); 188 cpci690_br_base = ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);
232 189
233 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE, 190 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE,
234 CPCI690_TODC_SIZE, 0); 191 CPCI690_TODC_SIZE, 0);
@@ -329,7 +286,7 @@ cpci690_fixup_mpsc_pdata(struct platform_device *pdev)
329 pdata->max_idle = 40; 286 pdata->max_idle = 40;
330 pdata->default_baud = CPCI690_MPSC_BAUD; 287 pdata->default_baud = CPCI690_MPSC_BAUD;
331 pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC; 288 pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC;
332 pdata->brg_clk_freq = CPCI690_BUS_FREQ; 289 pdata->brg_clk_freq = cpci690_get_bus_freq();
333} 290}
334 291
335static int __init 292static int __init
@@ -365,7 +322,7 @@ cpci690_reset_board(void)
365 u32 i = 10000; 322 u32 i = 10000;
366 323
367 local_irq_disable(); 324 local_irq_disable();
368 out_8((u8 *)(cpci690_br_base + CPCI690_BR_SW_RESET), 0x11); 325 out_8((cpci690_br_base + CPCI690_BR_SW_RESET), 0x11);
369 326
370 while (i != 0) i++; 327 while (i != 0) i++;
371 panic("restart failed\n"); 328 panic("restart failed\n");
@@ -394,10 +351,40 @@ cpci690_power_off(void)
394static int 351static int
395cpci690_show_cpuinfo(struct seq_file *m) 352cpci690_show_cpuinfo(struct seq_file *m)
396{ 353{
354 char *s;
355
356 seq_printf(m, "cpu MHz\t\t: %d\n",
357 (cpci690_get_cpu_freq() + 500000) / 1000000);
358 seq_printf(m, "bus MHz\t\t: %d\n",
359 (cpci690_get_bus_freq() + 500000) / 1000000);
397 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n"); 360 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
398 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n"); 361 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
399 seq_printf(m, "cpu MHz\t\t: %d\n", cpci690_get_cpu_speed()/1000/1000); 362 seq_printf(m, "FPGA Revision\t: %d\n",
400 seq_printf(m, "bus MHz\t\t: %d\n", CPCI690_BUS_FREQ/1000/1000); 363 in_8(cpci690_br_base + CPCI690_BR_MEM_CTLR) >> 5);
364
365 switch(bh.type) {
366 case MV64x60_TYPE_GT64260A:
367 s = "gt64260a";
368 break;
369 case MV64x60_TYPE_GT64260B:
370 s = "gt64260b";
371 break;
372 case MV64x60_TYPE_MV64360:
373 s = "mv64360";
374 break;
375 case MV64x60_TYPE_MV64460:
376 s = "mv64460";
377 break;
378 default:
379 s = "Unknown";
380 }
381 seq_printf(m, "bridge type\t: %s\n", s);
382 seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
383#if defined(CONFIG_NOT_COHERENT_CACHE)
384 seq_printf(m, "coherency\t: %s\n", "off");
385#else
386 seq_printf(m, "coherency\t: %s\n", "on");
387#endif
401 388
402 return 0; 389 return 0;
403} 390}
@@ -407,7 +394,7 @@ cpci690_calibrate_decr(void)
407{ 394{
408 ulong freq; 395 ulong freq;
409 396
410 freq = CPCI690_BUS_FREQ / 4; 397 freq = cpci690_get_bus_freq() / 4;
411 398
412 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", 399 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
413 freq/1000000, freq%1000000); 400 freq/1000000, freq%1000000);
@@ -416,25 +403,12 @@ cpci690_calibrate_decr(void)
416 tb_to_us = mulhwu_scale_factor(freq, 1000000); 403 tb_to_us = mulhwu_scale_factor(freq, 1000000);
417} 404}
418 405
419static __inline__ void 406#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC)
420cpci690_set_bat(u32 addr, u32 size)
421{
422 addr &= 0xfffe0000;
423 size &= 0x1ffe0000;
424 size = ((size >> 17) - 1) << 2;
425
426 mb();
427 mtspr(SPRN_DBAT1U, addr | size | 0x2); /* Vs == 1; Vp == 0 */
428 mtspr(SPRN_DBAT1L, addr | 0x2a); /* WIMG bits == 0101; PP == r/w access */
429 mb();
430}
431
432#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
433static void __init 407static void __init
434cpci690_map_io(void) 408cpci690_map_io(void)
435{ 409{
436 io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE, 410 io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE,
437 128 * KB, _PAGE_IO); 411 128 * 1024, _PAGE_IO);
438} 412}
439#endif 413#endif
440 414
@@ -442,14 +416,15 @@ void __init
442platform_init(unsigned long r3, unsigned long r4, unsigned long r5, 416platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
443 unsigned long r6, unsigned long r7) 417 unsigned long r6, unsigned long r7)
444{ 418{
445#ifdef CONFIG_BLK_DEV_INITRD
446 initrd_start=initrd_end=0;
447 initrd_below_start_ok=0;
448#endif /* CONFIG_BLK_DEV_INITRD */
449
450 parse_bootinfo(find_bootinfo()); 419 parse_bootinfo(find_bootinfo());
451 420
452 loops_per_jiffy = cpci690_get_cpu_speed() / HZ; 421#ifdef CONFIG_BLK_DEV_INITRD
422 /* take care of initrd if we have one */
423 if (r4) {
424 initrd_start = r4 + KERNELBASE;
425 initrd_end = r5 + KERNELBASE;
426 }
427#endif /* CONFIG_BLK_DEV_INITRD */
453 428
454 isa_mem_base = 0; 429 isa_mem_base = 0;
455 430
@@ -460,7 +435,6 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
460 ppc_md.restart = cpci690_restart; 435 ppc_md.restart = cpci690_restart;
461 ppc_md.power_off = cpci690_power_off; 436 ppc_md.power_off = cpci690_power_off;
462 ppc_md.halt = cpci690_halt; 437 ppc_md.halt = cpci690_halt;
463 ppc_md.find_end_of_memory = cpci690_find_end_of_memory;
464 ppc_md.time_init = todc_time_init; 438 ppc_md.time_init = todc_time_init;
465 ppc_md.set_rtc_time = todc_set_rtc_time; 439 ppc_md.set_rtc_time = todc_set_rtc_time;
466 ppc_md.get_rtc_time = todc_get_rtc_time; 440 ppc_md.get_rtc_time = todc_get_rtc_time;
@@ -468,22 +442,13 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
468 ppc_md.nvram_write_val = todc_direct_write_val; 442 ppc_md.nvram_write_val = todc_direct_write_val;
469 ppc_md.calibrate_decr = cpci690_calibrate_decr; 443 ppc_md.calibrate_decr = cpci690_calibrate_decr;
470 444
471 /* 445#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC)
472 * Need to map in board regs (used by cpci690_find_end_of_memory())
473 * and the bridge's regs (used by progress);
474 */
475 cpci690_set_bat(CPCI690_BR_BASE, 32 * MB);
476 cpci690_br_base = CPCI690_BR_BASE;
477
478#ifdef CONFIG_SERIAL_TEXT_DEBUG
479 ppc_md.setup_io_mappings = cpci690_map_io; 446 ppc_md.setup_io_mappings = cpci690_map_io;
447#ifdef CONFIG_SERIAL_TEXT_DEBUG
480 ppc_md.progress = mv64x60_mpsc_progress; 448 ppc_md.progress = mv64x60_mpsc_progress;
481 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); 449 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
482#endif /* CONFIG_SERIAL_TEXT_DEBUG */ 450#endif /* CONFIG_SERIAL_TEXT_DEBUG */
483#ifdef CONFIG_KGDB 451#endif /* defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) */
484 ppc_md.setup_io_mappings = cpci690_map_io;
485 ppc_md.early_serial_map = cpci690_early_serial_map;
486#endif /* CONFIG_KGDB */
487 452
488#if defined(CONFIG_SERIAL_MPSC) 453#if defined(CONFIG_SERIAL_MPSC)
489 platform_notify = cpci690_platform_notify; 454 platform_notify = cpci690_platform_notify;
diff --git a/arch/ppc/platforms/cpci690.h b/arch/ppc/platforms/cpci690.h
index 36cd2673c742..49584c9cedf3 100644
--- a/arch/ppc/platforms/cpci690.h
+++ b/arch/ppc/platforms/cpci690.h
@@ -73,6 +73,4 @@ typedef struct board_info {
73#define CPCI690_MPSC_BAUD 9600 73#define CPCI690_MPSC_BAUD 9600
74#define CPCI690_MPSC_CLK_SRC 8 /* TCLK */ 74#define CPCI690_MPSC_CLK_SRC 8 /* TCLK */
75 75
76#define CPCI690_BUS_FREQ 133333333
77
78#endif /* __PPC_PLATFORMS_CPCI690_H */ 76#endif /* __PPC_PLATFORMS_CPCI690_H */
diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c
new file mode 100644
index 000000000000..9811a8a52c25
--- /dev/null
+++ b/arch/ppc/platforms/ev64360.c
@@ -0,0 +1,510 @@
1/*
2 * arch/ppc/platforms/ev64360.c
3 *
4 * Board setup routines for the Marvell EV-64360-BP Evaluation Board.
5 *
6 * Author: Lee Nicks <allinux@gmail.com>
7 *
8 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
9 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/config.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/kdev_t.h>
20#include <linux/console.h>
21#include <linux/initrd.h>
22#include <linux/root_dev.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/bootmem.h>
26#include <linux/mtd/physmap.h>
27#include <linux/mv643xx.h>
28#ifdef CONFIG_BOOTIMG
29#include <linux/bootimg.h>
30#endif
31#include <asm/page.h>
32#include <asm/time.h>
33#include <asm/smp.h>
34#include <asm/todc.h>
35#include <asm/bootinfo.h>
36#include <asm/ppcboot.h>
37#include <asm/mv64x60.h>
38#include <platforms/ev64360.h>
39
40#define BOARD_VENDOR "Marvell"
41#define BOARD_MACHINE "EV-64360-BP"
42
43static struct mv64x60_handle bh;
44static void __iomem *sram_base;
45
46static u32 ev64360_flash_size_0;
47static u32 ev64360_flash_size_1;
48
49static u32 ev64360_bus_frequency;
50
51unsigned char __res[sizeof(bd_t)];
52
53static int __init
54ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
55{
56 return 0;
57}
58
59static void __init
60ev64360_setup_bridge(void)
61{
62 struct mv64x60_setup_info si;
63 int i;
64
65 memset(&si, 0, sizeof(si));
66
67 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
68
69 #ifdef CONFIG_PCI
70 si.pci_1.enable_bus = 1;
71 si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR;
72 si.pci_1.pci_io.pci_base_hi = 0;
73 si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR;
74 si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE;
75 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
76 si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR;
77 si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR;
78 si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR;
79 si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE;
80 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
81 si.pci_1.pci_cmd_bits = 0;
82 si.pci_1.latency_timer = 0x80;
83 #else
84 si.pci_0.enable_bus = 0;
85 si.pci_1.enable_bus = 0;
86 #endif
87
88 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
89#if defined(CONFIG_NOT_COHERENT_CACHE)
90 si.cpu_prot_options[i] = 0;
91 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
92 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
93 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
94
95 si.pci_1.acc_cntl_options[i] =
96 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
97 MV64360_PCI_ACC_CNTL_SWAP_NONE |
98 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
99 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
100#else
101 si.cpu_prot_options[i] = 0;
102 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
103 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
104 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
105
106 si.pci_1.acc_cntl_options[i] =
107 MV64360_PCI_ACC_CNTL_SNOOP_WB |
108 MV64360_PCI_ACC_CNTL_SWAP_NONE |
109 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
110 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
111#endif
112 }
113
114 if (mv64x60_init(&bh, &si))
115 printk(KERN_WARNING "Bridge initialization failed.\n");
116
117 #ifdef CONFIG_PCI
118 pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
119 ppc_md.pci_swizzle = common_swizzle;
120 ppc_md.pci_map_irq = ev64360_map_irq;
121 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
122
123 mv64x60_set_bus(&bh, 1, 0);
124 bh.hose_b->first_busno = 0;
125 bh.hose_b->last_busno = 0xff;
126 #endif
127}
128
129/* Bridge & platform setup routines */
130void __init
131ev64360_intr_setup(void)
132{
133 /* MPP 8, 9, and 10 */
134 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
135
136 /*
137 * Define GPP 8,9,and 10 interrupt polarity as active low
138 * input signal and level triggered
139 */
140 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
141 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
142
143 /* Config GPP intr ctlr to respond to level trigger */
144 mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
145
146 /* Erranum FEr PCI-#8 */
147 mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
148 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
149
150 /*
151 * Dismiss and then enable interrupt on GPP interrupt cause
152 * for CPU #0
153 */
154 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
155 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
156
157 /*
158 * Dismiss and then enable interrupt on CPU #0 high cause reg
159 * BIT25 summarizes GPP interrupts 8-15
160 */
161 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
162}
163
164void __init
165ev64360_setup_peripherals(void)
166{
167 u32 base;
168
169 /* Set up window for boot CS */
170 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
171 EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
172 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
173
174 /* We only use the 32-bit flash */
175 mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
176 &ev64360_flash_size_0);
177 ev64360_flash_size_1 = 0;
178
179 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
180 EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
181 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
182
183 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
184 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
185 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
186 sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
187
188 /* Set up Enet->SRAM window */
189 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
190 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
191 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
192
193 /* Give enet r/w access to memory region */
194 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
195 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
196 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
197
198 mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
199 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
200 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
201
202#if defined(CONFIG_NOT_COHERENT_CACHE)
203 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
204#else
205 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
206#endif
207
208 /*
209 * Setting the SRAM to 0. Note that this generates parity errors on
210 * internal data path in SRAM since it's first time accessing it
211 * while after reset it's not configured.
212 */
213 memset(sram_base, 0, MV64360_SRAM_SIZE);
214
215 /* set up PCI interrupt controller */
216 ev64360_intr_setup();
217}
218
219static void __init
220ev64360_setup_arch(void)
221{
222 if (ppc_md.progress)
223 ppc_md.progress("ev64360_setup_arch: enter", 0);
224
225 set_tb(0, 0);
226
227#ifdef CONFIG_BLK_DEV_INITRD
228 if (initrd_start)
229 ROOT_DEV = Root_RAM0;
230 else
231#endif
232#ifdef CONFIG_ROOT_NFS
233 ROOT_DEV = Root_NFS;
234#else
235 ROOT_DEV = Root_SDA2;
236#endif
237
238 /*
239 * Set up the L2CR register.
240 */
241 _set_L2CR(L2CR_L2E | L2CR_L2PE);
242
243 if (ppc_md.progress)
244 ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0);
245
246 ev64360_setup_bridge();
247 ev64360_setup_peripherals();
248 ev64360_bus_frequency = ev64360_bus_freq();
249
250 printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks "
251 "(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE);
252 if (ppc_md.progress)
253 ppc_md.progress("ev64360_setup_arch: exit", 0);
254}
255
256/* Platform device data fixup routines. */
257#if defined(CONFIG_SERIAL_MPSC)
258static void __init
259ev64360_fixup_mpsc_pdata(struct platform_device *pdev)
260{
261 struct mpsc_pdata *pdata;
262
263 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
264
265 pdata->max_idle = 40;
266 pdata->default_baud = EV64360_DEFAULT_BAUD;
267 pdata->brg_clk_src = EV64360_MPSC_CLK_SRC;
268 /*
269 * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
270 * TCLK == SysCLK but on 64460, they are separate pins.
271 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
272 */
273 pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX);
274}
275#endif
276
277#if defined(CONFIG_MV643XX_ETH)
278static void __init
279ev64360_fixup_eth_pdata(struct platform_device *pdev)
280{
281 struct mv643xx_eth_platform_data *eth_pd;
282 static u16 phy_addr[] = {
283 EV64360_ETH0_PHY_ADDR,
284 EV64360_ETH1_PHY_ADDR,
285 EV64360_ETH2_PHY_ADDR,
286 };
287
288 eth_pd = pdev->dev.platform_data;
289 eth_pd->force_phy_addr = 1;
290 eth_pd->phy_addr = phy_addr[pdev->id];
291 eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE;
292 eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE;
293}
294#endif
295
296static int __init
297ev64360_platform_notify(struct device *dev)
298{
299 static struct {
300 char *bus_id;
301 void ((*rtn)(struct platform_device *pdev));
302 } dev_map[] = {
303#if defined(CONFIG_SERIAL_MPSC)
304 { MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata },
305 { MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata },
306#endif
307#if defined(CONFIG_MV643XX_ETH)
308 { MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata },
309 { MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata },
310 { MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata },
311#endif
312 };
313 struct platform_device *pdev;
314 int i;
315
316 if (dev && dev->bus_id)
317 for (i=0; i<ARRAY_SIZE(dev_map); i++)
318 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
319 BUS_ID_SIZE)) {
320
321 pdev = container_of(dev,
322 struct platform_device, dev);
323 dev_map[i].rtn(pdev);
324 }
325
326 return 0;
327}
328
329#ifdef CONFIG_MTD_PHYSMAP
330
331#ifndef MB
332#define MB (1 << 20)
333#endif
334
335/*
336 * MTD Layout.
337 *
338 * FLASH Amount: 0xff000000 - 0xffffffff
339 * ------------- -----------------------
340 * Reserved: 0xff000000 - 0xff03ffff
341 * JFFS2 file system: 0xff040000 - 0xffefffff
342 * U-boot: 0xfff00000 - 0xffffffff
343 */
344static int __init
345ev64360_setup_mtd(void)
346{
347 u32 size;
348 int ptbl_entries;
349 static struct mtd_partition *ptbl;
350
351 size = ev64360_flash_size_0 + ev64360_flash_size_1;
352 if (!size)
353 return -ENOMEM;
354
355 ptbl_entries = 3;
356
357 if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
358 GFP_KERNEL)) == NULL) {
359
360 printk(KERN_WARNING "Can't alloc MTD partition table\n");
361 return -ENOMEM;
362 }
363 memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
364
365 ptbl[0].name = "reserved";
366 ptbl[0].offset = 0;
367 ptbl[0].size = EV64360_MTD_RESERVED_SIZE;
368 ptbl[1].name = "jffs2";
369 ptbl[1].offset = EV64360_MTD_RESERVED_SIZE;
370 ptbl[1].size = EV64360_MTD_JFFS2_SIZE;
371 ptbl[2].name = "U-BOOT";
372 ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE;
373 ptbl[2].size = EV64360_MTD_UBOOT_SIZE;
374
375 physmap_map.size = size;
376 physmap_set_partitions(ptbl, ptbl_entries);
377 return 0;
378}
379
380arch_initcall(ev64360_setup_mtd);
381#endif
382
383static void
384ev64360_restart(char *cmd)
385{
386 ulong i = 0xffffffff;
387 volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000);
388
389 /* issue hard reset */
390 rtc_base[0xf] = 0x80;
391 rtc_base[0xc] = 0x00;
392 rtc_base[0xd] = 0x01;
393 rtc_base[0xf] = 0x83;
394
395 while (i-- > 0) ;
396 panic("restart failed\n");
397}
398
399static void
400ev64360_halt(void)
401{
402 while (1) ;
403 /* NOTREACHED */
404}
405
406static void
407ev64360_power_off(void)
408{
409 ev64360_halt();
410 /* NOTREACHED */
411}
412
413static int
414ev64360_show_cpuinfo(struct seq_file *m)
415{
416 seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
417 seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
418 seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000);
419
420 return 0;
421}
422
423static void __init
424ev64360_calibrate_decr(void)
425{
426 u32 freq;
427
428 freq = ev64360_bus_frequency / 4;
429
430 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
431 (long)freq / 1000000, (long)freq % 1000000);
432
433 tb_ticks_per_jiffy = freq / HZ;
434 tb_to_us = mulhwu_scale_factor(freq, 1000000);
435}
436
437unsigned long __init
438ev64360_find_end_of_memory(void)
439{
440 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
441 MV64x60_TYPE_MV64360);
442}
443
444static inline void
445ev64360_set_bat(void)
446{
447 mb();
448 mtspr(SPRN_DBAT2U, 0xf0001ffe);
449 mtspr(SPRN_DBAT2L, 0xf000002a);
450 mb();
451}
452
453#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
454static void __init
455ev64360_map_io(void)
456{
457 io_block_mapping(CONFIG_MV64X60_NEW_BASE, \
458 CONFIG_MV64X60_NEW_BASE, \
459 0x00020000, _PAGE_IO);
460}
461#endif
462
463void __init
464platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
465 unsigned long r6, unsigned long r7)
466{
467 parse_bootinfo(find_bootinfo());
468
469 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
470 * are non-zero, then we should use the board info from the bd_t
471 * structure and the cmdline pointed to by r6 instead of the
472 * information from birecs, if any. Otherwise, use the information
473 * from birecs as discovered by the preceeding call to
474 * parse_bootinfo(). This rule should work with both PPCBoot, which
475 * uses a bd_t board info structure, and the kernel boot wrapper,
476 * which uses birecs.
477 */
478 if (r3 && r6) {
479 /* copy board info structure */
480 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
481 /* copy command line */
482 *(char *)(r7+KERNELBASE) = 0;
483 strcpy(cmd_line, (char *)(r6+KERNELBASE));
484 }
485 #ifdef CONFIG_ISA
486 isa_mem_base = 0;
487 #endif
488
489 ppc_md.setup_arch = ev64360_setup_arch;
490 ppc_md.show_cpuinfo = ev64360_show_cpuinfo;
491 ppc_md.init_IRQ = mv64360_init_irq;
492 ppc_md.get_irq = mv64360_get_irq;
493 ppc_md.restart = ev64360_restart;
494 ppc_md.power_off = ev64360_power_off;
495 ppc_md.halt = ev64360_halt;
496 ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
497 ppc_md.calibrate_decr = ev64360_calibrate_decr;
498
499#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
500 ppc_md.setup_io_mappings = ev64360_map_io;
501 ppc_md.progress = mv64x60_mpsc_progress;
502 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
503#endif
504
505#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
506 platform_notify = ev64360_platform_notify;
507#endif
508
509 ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */
510}
diff --git a/arch/ppc/platforms/ev64360.h b/arch/ppc/platforms/ev64360.h
new file mode 100644
index 000000000000..68eabe490397
--- /dev/null
+++ b/arch/ppc/platforms/ev64360.h
@@ -0,0 +1,116 @@
1/*
2 * arch/ppc/platforms/ev64360.h
3 *
4 * Definitions for Marvell EV-64360-BP Evaluation Board.
5 *
6 * Author: Lee Nicks <allinux@gmail.com>
7 *
8 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
9 * Based on code done by Mark A. Greer <mgreer@mvista.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17/*
18 * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
19 * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
20 * We'll only use one PCI MEM window on each PCI bus.
21 *
22 * This is the CPU physical memory map (windows must be at least 64KB and start
23 * on a boundary that is a multiple of the window size):
24 *
25 * 0x42000000-0x4203ffff - Internal SRAM
26 * 0xf1000000-0xf100ffff - MV64360 Registers (CONFIG_MV64X60_NEW_BASE)
27 * 0xfc800000-0xfcffffff - RTC
28 * 0xff000000-0xffffffff - Boot window, 16 MB flash
29 * 0xc0000000-0xc3ffffff - PCI I/O (second hose)
30 * 0x80000000-0xbfffffff - PCI MEM (second hose)
31 */
32
33#ifndef __PPC_PLATFORMS_EV64360_H
34#define __PPC_PLATFORMS_EV64360_H
35
36/* CPU Physical Memory Map setup. */
37#define EV64360_BOOT_WINDOW_BASE 0xff000000
38#define EV64360_BOOT_WINDOW_SIZE 0x01000000 /* 16 MB */
39#define EV64360_INTERNAL_SRAM_BASE 0x42000000
40#define EV64360_RTC_WINDOW_BASE 0xfc800000
41#define EV64360_RTC_WINDOW_SIZE 0x00800000 /* 8 MB */
42
43#define EV64360_PCI1_MEM_START_PROC_ADDR 0x80000000
44#define EV64360_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
45#define EV64360_PCI1_MEM_START_PCI_LO_ADDR 0x80000000
46#define EV64360_PCI1_MEM_SIZE 0x40000000 /* 1 GB */
47#define EV64360_PCI1_IO_START_PROC_ADDR 0xc0000000
48#define EV64360_PCI1_IO_START_PCI_ADDR 0x00000000
49#define EV64360_PCI1_IO_SIZE 0x04000000 /* 64 MB */
50
51#define EV64360_DEFAULT_BAUD 115200
52#define EV64360_MPSC_CLK_SRC 8 /* TCLK */
53#define EV64360_MPSC_CLK_FREQ 133333333
54
55#define EV64360_MTD_RESERVED_SIZE 0x40000
56#define EV64360_MTD_JFFS2_SIZE 0xec0000
57#define EV64360_MTD_UBOOT_SIZE 0x100000
58
59#define EV64360_ETH0_PHY_ADDR 8
60#define EV64360_ETH1_PHY_ADDR 9
61#define EV64360_ETH2_PHY_ADDR 10
62
63#define EV64360_ETH_TX_QUEUE_SIZE 800
64#define EV64360_ETH_RX_QUEUE_SIZE 400
65
66#define EV64360_ETH_PORT_CONFIG_VALUE \
67 ETH_UNICAST_NORMAL_MODE | \
68 ETH_DEFAULT_RX_QUEUE_0 | \
69 ETH_DEFAULT_RX_ARP_QUEUE_0 | \
70 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
71 ETH_RECEIVE_BC_IF_IP | \
72 ETH_RECEIVE_BC_IF_ARP | \
73 ETH_CAPTURE_TCP_FRAMES_DIS | \
74 ETH_CAPTURE_UDP_FRAMES_DIS | \
75 ETH_DEFAULT_RX_TCP_QUEUE_0 | \
76 ETH_DEFAULT_RX_UDP_QUEUE_0 | \
77 ETH_DEFAULT_RX_BPDU_QUEUE_0
78
79#define EV64360_ETH_PORT_CONFIG_EXTEND_VALUE \
80 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
81 ETH_PARTITION_DISABLE
82
83#define GT_ETH_IPG_INT_RX(value) \
84 ((value & 0x3fff) << 8)
85
86#define EV64360_ETH_PORT_SDMA_CONFIG_VALUE \
87 ETH_RX_BURST_SIZE_4_64BIT | \
88 GT_ETH_IPG_INT_RX(0) | \
89 ETH_TX_BURST_SIZE_4_64BIT
90
91#define EV64360_ETH_PORT_SERIAL_CONTROL_VALUE \
92 ETH_FORCE_LINK_PASS | \
93 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
94 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
95 ETH_ADV_SYMMETRIC_FLOW_CTRL | \
96 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
97 ETH_FORCE_BP_MODE_NO_JAM | \
98 BIT9 | \
99 ETH_DO_NOT_FORCE_LINK_FAIL | \
100 ETH_RETRANSMIT_16_ATTEMPTS | \
101 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
102 ETH_DTE_ADV_0 | \
103 ETH_DISABLE_AUTO_NEG_BYPASS | \
104 ETH_AUTO_NEG_NO_CHANGE | \
105 ETH_MAX_RX_PACKET_9700BYTE | \
106 ETH_CLR_EXT_LOOPBACK | \
107 ETH_SET_FULL_DUPLEX_MODE | \
108 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
109
110static inline u32
111ev64360_bus_freq(void)
112{
113 return 133333333;
114}
115
116#endif /* __PPC_PLATFORMS_EV64360_H */
diff --git a/arch/ppc/platforms/k2.c b/arch/ppc/platforms/k2.c
deleted file mode 100644
index aacb438708ff..000000000000
--- a/arch/ppc/platforms/k2.c
+++ /dev/null
@@ -1,613 +0,0 @@
1/*
2 * arch/ppc/platforms/k2.c
3 *
4 * Board setup routines for SBS K2
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * Updated by: Randy Vinson <rvinson@mvista.com.
9 *
10 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16#include <linux/config.h>
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/types.h>
25#include <linux/major.h>
26#include <linux/initrd.h>
27#include <linux/console.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/irq.h>
31#include <linux/seq_file.h>
32#include <linux/root_dev.h>
33
34#include <asm/system.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/dma.h>
38#include <asm/io.h>
39#include <asm/machdep.h>
40#include <asm/time.h>
41#include <asm/i8259.h>
42#include <asm/todc.h>
43#include <asm/bootinfo.h>
44
45#include <syslib/cpc710.h>
46#include "k2.h"
47
48extern unsigned long loops_per_jiffy;
49extern void gen550_progress(char *, unsigned short);
50
51static unsigned int cpu_7xx[16] = {
52 0, 15, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
53};
54static unsigned int cpu_6xx[16] = {
55 0, 0, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 0, 12, 7, 0
56};
57
58static inline int __init
59k2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
60{
61 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
62 /*
63 * Check our hose index. If we are zero then we are on the
64 * local PCI hose, otherwise we are on the cPCI hose.
65 */
66 if (!hose->index) {
67 static char pci_irq_table[][4] =
68 /*
69 * PCI IDSEL/INTPIN->INTLINE
70 * A B C D
71 */
72 {
73 {1, 0, 0, 0}, /* Ethernet */
74 {5, 5, 5, 5}, /* PMC Site 1 */
75 {6, 6, 6, 6}, /* PMC Site 2 */
76 {0, 0, 0, 0}, /* unused */
77 {0, 0, 0, 0}, /* unused */
78 {0, 0, 0, 0}, /* PCI-ISA Bridge */
79 {0, 0, 0, 0}, /* unused */
80 {0, 0, 0, 0}, /* unused */
81 {0, 0, 0, 0}, /* unused */
82 {0, 0, 0, 0}, /* unused */
83 {0, 0, 0, 0}, /* unused */
84 {0, 0, 0, 0}, /* unused */
85 {0, 0, 0, 0}, /* unused */
86 {0, 0, 0, 0}, /* unused */
87 {15, 0, 0, 0}, /* M5229 IDE */
88 };
89 const long min_idsel = 3, max_idsel = 17, irqs_per_slot = 4;
90 return PCI_IRQ_TABLE_LOOKUP;
91 } else {
92 static char pci_irq_table[][4] =
93 /*
94 * PCI IDSEL/INTPIN->INTLINE
95 * A B C D
96 */
97 {
98 {10, 11, 12, 9}, /* cPCI slot 8 */
99 {11, 12, 9, 10}, /* cPCI slot 7 */
100 {12, 9, 10, 11}, /* cPCI slot 6 */
101 {9, 10, 11, 12}, /* cPCI slot 5 */
102 {10, 11, 12, 9}, /* cPCI slot 4 */
103 {11, 12, 9, 10}, /* cPCI slot 3 */
104 {12, 9, 10, 11}, /* cPCI slot 2 */
105 };
106 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
107 return PCI_IRQ_TABLE_LOOKUP;
108 }
109}
110
111void k2_pcibios_fixup(void)
112{
113#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
114 struct pci_dev *ide_dev;
115
116 /*
117 * Enable DMA support on hdc
118 */
119 ide_dev = pci_get_device(PCI_VENDOR_ID_AL,
120 PCI_DEVICE_ID_AL_M5229, NULL);
121
122 if (ide_dev) {
123
124 unsigned long ide_dma_base;
125
126 ide_dma_base = pci_resource_start(ide_dev, 4);
127 outb(0x00, ide_dma_base + 0x2);
128 outb(0x20, ide_dma_base + 0xa);
129 pci_dev_put(ide_dev);
130 }
131#endif
132}
133
134void k2_pcibios_fixup_resources(struct pci_dev *dev)
135{
136 int i;
137
138 if ((dev->vendor == PCI_VENDOR_ID_IBM) &&
139 (dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64)) {
140 pr_debug("Fixup CPC710 resources\n");
141 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
142 dev->resource[i].start = 0;
143 dev->resource[i].end = 0;
144 }
145 }
146}
147
148void k2_setup_hoses(void)
149{
150 struct pci_controller *hose_a, *hose_b;
151
152 /*
153 * Reconfigure CPC710 memory map so
154 * we have some more PCI memory space.
155 */
156
157 /* Set FPHB mode */
158 __raw_writel(0x808000e0, PGCHP); /* Set FPHB mode */
159
160 /* PCI32 mappings */
161 __raw_writel(0x00000000, K2_PCI32_BAR + PIBAR); /* PCI I/O base */
162 __raw_writel(0x00000000, K2_PCI32_BAR + PMBAR); /* PCI Mem base */
163 __raw_writel(0xf0000000, K2_PCI32_BAR + MSIZE); /* 256MB */
164 __raw_writel(0xfff00000, K2_PCI32_BAR + IOSIZE); /* 1MB */
165 __raw_writel(0xc0000000, K2_PCI32_BAR + SMBAR); /* Base@0xc0000000 */
166 __raw_writel(0x80000000, K2_PCI32_BAR + SIBAR); /* Base@0x80000000 */
167 __raw_writel(0x000000c0, K2_PCI32_BAR + PSSIZE); /* 1GB space */
168 __raw_writel(0x000000c0, K2_PCI32_BAR + PPSIZE); /* 1GB space */
169 __raw_writel(0x00000000, K2_PCI32_BAR + BARPS); /* Base@0x00000000 */
170 __raw_writel(0x00000000, K2_PCI32_BAR + BARPP); /* Base@0x00000000 */
171 __raw_writel(0x00000080, K2_PCI32_BAR + PSBAR); /* Base@0x80 */
172 __raw_writel(0x00000000, K2_PCI32_BAR + PPBAR);
173
174 __raw_writel(0xc0000000, K2_PCI32_BAR + BPMDLK);
175 __raw_writel(0xd0000000, K2_PCI32_BAR + TPMDLK);
176 __raw_writel(0x80000000, K2_PCI32_BAR + BIODLK);
177 __raw_writel(0x80100000, K2_PCI32_BAR + TIODLK);
178 __raw_writel(0xe0008000, K2_PCI32_BAR + DLKCTRL);
179 __raw_writel(0xffffffff, K2_PCI32_BAR + DLKDEV);
180
181 /* PCI64 mappings */
182 __raw_writel(0x00100000, K2_PCI64_BAR + PIBAR); /* PCI I/O base */
183 __raw_writel(0x10000000, K2_PCI64_BAR + PMBAR); /* PCI Mem base */
184 __raw_writel(0xf0000000, K2_PCI64_BAR + MSIZE); /* 256MB */
185 __raw_writel(0xfff00000, K2_PCI64_BAR + IOSIZE); /* 1MB */
186 __raw_writel(0xd0000000, K2_PCI64_BAR + SMBAR); /* Base@0xd0000000 */
187 __raw_writel(0x80100000, K2_PCI64_BAR + SIBAR); /* Base@0x80100000 */
188 __raw_writel(0x000000c0, K2_PCI64_BAR + PSSIZE); /* 1GB space */
189 __raw_writel(0x000000c0, K2_PCI64_BAR + PPSIZE); /* 1GB space */
190 __raw_writel(0x00000000, K2_PCI64_BAR + BARPS); /* Base@0x00000000 */
191 __raw_writel(0x00000000, K2_PCI64_BAR + BARPP); /* Base@0x00000000 */
192
193 /* Setup PCI32 hose */
194 hose_a = pcibios_alloc_controller();
195 if (!hose_a)
196 return;
197
198 hose_a->first_busno = 0;
199 hose_a->last_busno = 0xff;
200 hose_a->pci_mem_offset = K2_PCI32_MEM_BASE;
201
202 pci_init_resource(&hose_a->io_resource,
203 K2_PCI32_LOWER_IO,
204 K2_PCI32_UPPER_IO,
205 IORESOURCE_IO, "PCI32 host bridge");
206
207 pci_init_resource(&hose_a->mem_resources[0],
208 K2_PCI32_LOWER_MEM + K2_PCI32_MEM_BASE,
209 K2_PCI32_UPPER_MEM + K2_PCI32_MEM_BASE,
210 IORESOURCE_MEM, "PCI32 host bridge");
211
212 hose_a->io_space.start = K2_PCI32_LOWER_IO;
213 hose_a->io_space.end = K2_PCI32_UPPER_IO;
214 hose_a->mem_space.start = K2_PCI32_LOWER_MEM;
215 hose_a->mem_space.end = K2_PCI32_UPPER_MEM;
216 hose_a->io_base_virt = (void *)K2_ISA_IO_BASE;
217
218 setup_indirect_pci(hose_a, K2_PCI32_CONFIG_ADDR, K2_PCI32_CONFIG_DATA);
219
220 /* Initialize PCI32 bus registers */
221 early_write_config_byte(hose_a,
222 hose_a->first_busno,
223 PCI_DEVFN(0, 0),
224 CPC710_BUS_NUMBER, hose_a->first_busno);
225
226 early_write_config_byte(hose_a,
227 hose_a->first_busno,
228 PCI_DEVFN(0, 0),
229 CPC710_SUB_BUS_NUMBER, hose_a->last_busno);
230
231 /* Enable PCI interrupt polling */
232 early_write_config_byte(hose_a,
233 hose_a->first_busno,
234 PCI_DEVFN(8, 0), 0x45, 0x80);
235
236 /* Route polled PCI interrupts */
237 early_write_config_byte(hose_a,
238 hose_a->first_busno,
239 PCI_DEVFN(8, 0), 0x48, 0x58);
240
241 early_write_config_byte(hose_a,
242 hose_a->first_busno,
243 PCI_DEVFN(8, 0), 0x49, 0x07);
244
245 early_write_config_byte(hose_a,
246 hose_a->first_busno,
247 PCI_DEVFN(8, 0), 0x4a, 0x31);
248
249 early_write_config_byte(hose_a,
250 hose_a->first_busno,
251 PCI_DEVFN(8, 0), 0x4b, 0xb9);
252
253 /* route secondary IDE channel interrupt to IRQ 15 */
254 early_write_config_byte(hose_a,
255 hose_a->first_busno,
256 PCI_DEVFN(8, 0), 0x75, 0x0f);
257
258 /* enable IDE controller IDSEL */
259 early_write_config_byte(hose_a,
260 hose_a->first_busno,
261 PCI_DEVFN(8, 0), 0x58, 0x48);
262
263 /* Enable IDE function */
264 early_write_config_byte(hose_a,
265 hose_a->first_busno,
266 PCI_DEVFN(17, 0), 0x50, 0x03);
267
268 /* Set M5229 IDE controller to native mode */
269 early_write_config_byte(hose_a,
270 hose_a->first_busno,
271 PCI_DEVFN(17, 0), PCI_CLASS_PROG, 0xdf);
272
273 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
274
275 /* Write out correct max subordinate bus number for hose A */
276 early_write_config_byte(hose_a,
277 hose_a->first_busno,
278 PCI_DEVFN(0, 0),
279 CPC710_SUB_BUS_NUMBER, hose_a->last_busno);
280
281 /* Only setup PCI64 hose if we are in the system slot */
282 if (!(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK)) {
283 /* Setup PCI64 hose */
284 hose_b = pcibios_alloc_controller();
285 if (!hose_b)
286 return;
287
288 hose_b->first_busno = hose_a->last_busno + 1;
289 hose_b->last_busno = 0xff;
290
291 /* Reminder: quit changing the following, it is correct. */
292 hose_b->pci_mem_offset = K2_PCI32_MEM_BASE;
293
294 pci_init_resource(&hose_b->io_resource,
295 K2_PCI64_LOWER_IO,
296 K2_PCI64_UPPER_IO,
297 IORESOURCE_IO, "PCI64 host bridge");
298
299 pci_init_resource(&hose_b->mem_resources[0],
300 K2_PCI64_LOWER_MEM + K2_PCI32_MEM_BASE,
301 K2_PCI64_UPPER_MEM + K2_PCI32_MEM_BASE,
302 IORESOURCE_MEM, "PCI64 host bridge");
303
304 hose_b->io_space.start = K2_PCI64_LOWER_IO;
305 hose_b->io_space.end = K2_PCI64_UPPER_IO;
306 hose_b->mem_space.start = K2_PCI64_LOWER_MEM;
307 hose_b->mem_space.end = K2_PCI64_UPPER_MEM;
308 hose_b->io_base_virt = (void *)K2_ISA_IO_BASE;
309
310 setup_indirect_pci(hose_b,
311 K2_PCI64_CONFIG_ADDR, K2_PCI64_CONFIG_DATA);
312
313 /* Initialize PCI64 bus registers */
314 early_write_config_byte(hose_b,
315 0,
316 PCI_DEVFN(0, 0),
317 CPC710_SUB_BUS_NUMBER, 0xff);
318
319 early_write_config_byte(hose_b,
320 0,
321 PCI_DEVFN(0, 0),
322 CPC710_BUS_NUMBER, hose_b->first_busno);
323
324 hose_b->last_busno = pciauto_bus_scan(hose_b,
325 hose_b->first_busno);
326
327 /* Write out correct max subordinate bus number for hose B */
328 early_write_config_byte(hose_b,
329 hose_b->first_busno,
330 PCI_DEVFN(0, 0),
331 CPC710_SUB_BUS_NUMBER,
332 hose_b->last_busno);
333
334 /* Configure PCI64 PSBAR */
335 early_write_config_dword(hose_b,
336 hose_b->first_busno,
337 PCI_DEVFN(0, 0),
338 PCI_BASE_ADDRESS_0,
339 K2_PCI64_SYS_MEM_BASE);
340 }
341
342 /* Configure i8259 level/edge settings */
343 outb(0x62, 0x4d0);
344 outb(0xde, 0x4d1);
345
346#ifdef CONFIG_CPC710_DATA_GATHERING
347 {
348 unsigned int tmp;
349 tmp = __raw_readl(ABCNTL);
350 /* Enable data gathering on both PCI interfaces */
351 __raw_writel(tmp | 0x05000000, ABCNTL);
352 }
353#endif
354
355 ppc_md.pcibios_fixup = k2_pcibios_fixup;
356 ppc_md.pcibios_fixup_resources = k2_pcibios_fixup_resources;
357 ppc_md.pci_swizzle = common_swizzle;
358 ppc_md.pci_map_irq = k2_map_irq;
359}
360
361static int k2_get_bus_speed(void)
362{
363 int bus_speed;
364 unsigned char board_id;
365
366 board_id = *(unsigned char *)K2_BOARD_ID_REG;
367
368 switch (K2_BUS_SPD(board_id)) {
369
370 case 0:
371 default:
372 bus_speed = 100000000;
373 break;
374
375 case 1:
376 bus_speed = 83333333;
377 break;
378
379 case 2:
380 bus_speed = 75000000;
381 break;
382
383 case 3:
384 bus_speed = 66666666;
385 break;
386 }
387 return bus_speed;
388}
389
390static int k2_get_cpu_speed(void)
391{
392 unsigned long hid1;
393 int cpu_speed;
394
395 hid1 = mfspr(SPRN_HID1) >> 28;
396
397 if ((mfspr(SPRN_PVR) >> 16) == 8)
398 hid1 = cpu_7xx[hid1];
399 else
400 hid1 = cpu_6xx[hid1];
401
402 cpu_speed = k2_get_bus_speed() * hid1 / 2;
403 return cpu_speed;
404}
405
406static void __init k2_calibrate_decr(void)
407{
408 int freq, divisor = 4;
409
410 /* determine processor bus speed */
411 freq = k2_get_bus_speed();
412 tb_ticks_per_jiffy = freq / HZ / divisor;
413 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
414}
415
416static int k2_show_cpuinfo(struct seq_file *m)
417{
418 unsigned char k2_geo_bits, k2_system_slot;
419
420 seq_printf(m, "vendor\t\t: SBS\n");
421 seq_printf(m, "machine\t\t: K2\n");
422 seq_printf(m, "cpu speed\t: %dMhz\n", k2_get_cpu_speed() / 1000000);
423 seq_printf(m, "bus speed\t: %dMhz\n", k2_get_bus_speed() / 1000000);
424 seq_printf(m, "memory type\t: SDRAM\n");
425
426 k2_geo_bits = readb(K2_MSIZ_GEO_REG) & K2_GEO_ADR_MASK;
427 k2_system_slot = !(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK);
428 seq_printf(m, "backplane\t: %s slot board",
429 k2_system_slot ? "System" : "Non system");
430 seq_printf(m, "with geographical address %x\n", k2_geo_bits);
431
432 return 0;
433}
434
435TODC_ALLOC();
436
437static void __init k2_setup_arch(void)
438{
439 unsigned int cpu;
440
441 /* Setup TODC access */
442 TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
443 ioremap(K2_RTC_BASE_ADDRESS, K2_RTC_SIZE), 8);
444
445 /* init to some ~sane value until calibrate_delay() runs */
446 loops_per_jiffy = 50000000 / HZ;
447
448 /* make FLASH transactions higher priority than PCI to avoid deadlock */
449 __raw_writel(__raw_readl(SIOC1) | 0x80000000, SIOC1);
450
451 /* Set hardware to access FLASH page 2 */
452 __raw_writel(1 << 29, GPOUT);
453
454 /* Setup PCI host bridges */
455 k2_setup_hoses();
456
457#ifdef CONFIG_BLK_DEV_INITRD
458 if (initrd_start)
459 ROOT_DEV = Root_RAM0;
460 else
461#endif
462#ifdef CONFIG_ROOT_NFS
463 ROOT_DEV = Root_NFS;
464#else
465 ROOT_DEV = Root_HDC1;
466#endif
467
468 /* Identify the system */
469 printk(KERN_INFO "System Identification: SBS K2 - PowerPC 750 @ "
470 "%d Mhz\n", k2_get_cpu_speed() / 1000000);
471 printk(KERN_INFO "Port by MontaVista Software, Inc. "
472 "(source@mvista.com)\n");
473
474 /* Identify the CPU manufacturer */
475 cpu = PVR_REV(mfspr(SPRN_PVR));
476 printk(KERN_INFO "CPU manufacturer: %s [rev=%04x]\n",
477 (cpu & (1 << 15)) ? "IBM" : "Motorola", cpu);
478}
479
480static void k2_restart(char *cmd)
481{
482 local_irq_disable();
483
484 /* Flip FLASH back to page 1 to access firmware image */
485 __raw_writel(0, GPOUT);
486
487 /* SRR0 has system reset vector, SRR1 has default MSR value */
488 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
489 mtspr(SPRN_SRR0, 0xfff00100);
490 mtspr(SPRN_SRR1, 0);
491 __asm__ __volatile__("rfi\n\t");
492
493 /* not reached */
494 for (;;) ;
495}
496
497static void k2_power_off(void)
498{
499 for (;;) ;
500}
501
502static void k2_halt(void)
503{
504 k2_restart(NULL);
505}
506
507/*
508 * Set BAT 3 to map PCI32 I/O space.
509 */
510static __inline__ void k2_set_bat(void)
511{
512 /* wait for all outstanding memory accesses to complete */
513 mb();
514
515 /* setup DBATs */
516 mtspr(SPRN_DBAT2U, 0x80001ffe);
517 mtspr(SPRN_DBAT2L, 0x8000002a);
518 mtspr(SPRN_DBAT3U, 0xf0001ffe);
519 mtspr(SPRN_DBAT3L, 0xf000002a);
520
521 /* wait for updates */
522 mb();
523}
524
525static unsigned long __init k2_find_end_of_memory(void)
526{
527 unsigned long total;
528 unsigned char msize = 7; /* Default to 128MB */
529
530 msize = K2_MEM_SIZE(readb(K2_MSIZ_GEO_REG));
531
532 switch (msize) {
533 case 2:
534 /*
535 * This will break without a lowered
536 * KERNELBASE or CONFIG_HIGHMEM on.
537 * It seems non 1GB builds exist yet,
538 * though.
539 */
540 total = K2_MEM_SIZE_1GB;
541 break;
542 case 3:
543 case 4:
544 total = K2_MEM_SIZE_512MB;
545 break;
546 case 5:
547 case 6:
548 total = K2_MEM_SIZE_256MB;
549 break;
550 case 7:
551 total = K2_MEM_SIZE_128MB;
552 break;
553 default:
554 printk
555 ("K2: Invalid memory size detected, defaulting to 128MB\n");
556 total = K2_MEM_SIZE_128MB;
557 break;
558 }
559 return total;
560}
561
562static void __init k2_map_io(void)
563{
564 io_block_mapping(K2_PCI32_IO_BASE,
565 K2_PCI32_IO_BASE, 0x00200000, _PAGE_IO);
566 io_block_mapping(0xff000000, 0xff000000, 0x01000000, _PAGE_IO);
567}
568
569static void __init k2_init_irq(void)
570{
571 int i;
572
573 for (i = 0; i < 16; i++)
574 irq_desc[i].handler = &i8259_pic;
575
576 i8259_init(0);
577}
578
579void __init platform_init(unsigned long r3, unsigned long r4,
580 unsigned long r5, unsigned long r6, unsigned long r7)
581{
582 parse_bootinfo((struct bi_record *)(r3 + KERNELBASE));
583
584 k2_set_bat();
585
586 isa_io_base = K2_ISA_IO_BASE;
587 isa_mem_base = K2_ISA_MEM_BASE;
588 pci_dram_offset = K2_PCI32_SYS_MEM_BASE;
589
590 ppc_md.setup_arch = k2_setup_arch;
591 ppc_md.show_cpuinfo = k2_show_cpuinfo;
592 ppc_md.init_IRQ = k2_init_irq;
593 ppc_md.get_irq = i8259_irq;
594
595 ppc_md.find_end_of_memory = k2_find_end_of_memory;
596 ppc_md.setup_io_mappings = k2_map_io;
597
598 ppc_md.restart = k2_restart;
599 ppc_md.power_off = k2_power_off;
600 ppc_md.halt = k2_halt;
601
602 ppc_md.time_init = todc_time_init;
603 ppc_md.set_rtc_time = todc_set_rtc_time;
604 ppc_md.get_rtc_time = todc_get_rtc_time;
605 ppc_md.calibrate_decr = k2_calibrate_decr;
606
607 ppc_md.nvram_read_val = todc_direct_read_val;
608 ppc_md.nvram_write_val = todc_direct_write_val;
609
610#ifdef CONFIG_SERIAL_TEXT_DEBUG
611 ppc_md.progress = gen550_progress;
612#endif
613}
diff --git a/arch/ppc/platforms/k2.h b/arch/ppc/platforms/k2.h
deleted file mode 100644
index 78326aba1988..000000000000
--- a/arch/ppc/platforms/k2.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * arch/ppc/platforms/k2.h
3 *
4 * Definitions for SBS K2 board support
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifndef __PPC_PLATFORMS_K2_H
15#define __PPC_PLATFORMS_K2_H
16
17/*
18 * SBS K2 definitions
19 */
20
21#define K2_PCI64_BAR 0xff400000
22#define K2_PCI32_BAR 0xff500000
23
24#define K2_PCI64_CONFIG_ADDR (K2_PCI64_BAR + 0x000f8000)
25#define K2_PCI64_CONFIG_DATA (K2_PCI64_BAR + 0x000f8010)
26
27#define K2_PCI32_CONFIG_ADDR (K2_PCI32_BAR + 0x000f8000)
28#define K2_PCI32_CONFIG_DATA (K2_PCI32_BAR + 0x000f8010)
29
30#define K2_PCI64_MEM_BASE 0xd0000000
31#define K2_PCI64_IO_BASE 0x80100000
32
33#define K2_PCI32_MEM_BASE 0xc0000000
34#define K2_PCI32_IO_BASE 0x80000000
35
36#define K2_PCI32_SYS_MEM_BASE 0x80000000
37#define K2_PCI64_SYS_MEM_BASE K2_PCI32_SYS_MEM_BASE
38
39#define K2_PCI32_LOWER_MEM 0x00000000
40#define K2_PCI32_UPPER_MEM 0x0fffffff
41#define K2_PCI32_LOWER_IO 0x00000000
42#define K2_PCI32_UPPER_IO 0x000fffff
43
44#define K2_PCI64_LOWER_MEM 0x10000000
45#define K2_PCI64_UPPER_MEM 0x1fffffff
46#define K2_PCI64_LOWER_IO 0x00100000
47#define K2_PCI64_UPPER_IO 0x001fffff
48
49#define K2_ISA_IO_BASE K2_PCI32_IO_BASE
50#define K2_ISA_MEM_BASE K2_PCI32_MEM_BASE
51
52#define K2_BOARD_ID_REG (K2_ISA_IO_BASE + 0x800)
53#define K2_MISC_REG (K2_ISA_IO_BASE + 0x804)
54#define K2_MSIZ_GEO_REG (K2_ISA_IO_BASE + 0x808)
55#define K2_HOT_SWAP_REG (K2_ISA_IO_BASE + 0x80c)
56#define K2_PLD2_REG (K2_ISA_IO_BASE + 0x80e)
57#define K2_PLD3_REG (K2_ISA_IO_BASE + 0x80f)
58
59#define K2_BUS_SPD(board_id) (board_id >> 2) & 3
60
61#define K2_RTC_BASE_OFFSET 0x90000
62#define K2_RTC_BASE_ADDRESS (K2_PCI32_MEM_BASE + K2_RTC_BASE_OFFSET)
63#define K2_RTC_SIZE 0x8000
64
65#define K2_MEM_SIZE_MASK 0xe0
66#define K2_MEM_SIZE(size_reg) (size_reg & K2_MEM_SIZE_MASK) >> 5
67#define K2_MEM_SIZE_1GB 0x40000000
68#define K2_MEM_SIZE_512MB 0x20000000
69#define K2_MEM_SIZE_256MB 0x10000000
70#define K2_MEM_SIZE_128MB 0x08000000
71
72#define K2_L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
73#define K2_L2CACHE_512KB 0x00 /* 512KB */
74#define K2_L2CACHE_256KB 0x01 /* 256KB */
75#define K2_L2CACHE_1MB 0x02 /* 1MB */
76#define K2_L2CACHE_NONE 0x03 /* None */
77
78#define K2_GEO_ADR_MASK 0x1f
79
80#define K2_SYS_SLOT_MASK 0x08
81
82#endif /* __PPC_PLATFORMS_K2_H */
diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c
index 169dbf6534b9..2b53afae0e9c 100644
--- a/arch/ppc/platforms/katana.c
+++ b/arch/ppc/platforms/katana.c
@@ -33,6 +33,7 @@
33#include <linux/bootimg.h> 33#include <linux/bootimg.h>
34#endif 34#endif
35#include <asm/io.h> 35#include <asm/io.h>
36#include <asm/unistd.h>
36#include <asm/page.h> 37#include <asm/page.h>
37#include <asm/time.h> 38#include <asm/time.h>
38#include <asm/smp.h> 39#include <asm/smp.h>
@@ -42,15 +43,14 @@
42#include <asm/mv64x60.h> 43#include <asm/mv64x60.h>
43#include <platforms/katana.h> 44#include <platforms/katana.h>
44 45
45static struct mv64x60_handle bh; 46static struct mv64x60_handle bh;
46static katana_id_t katana_id; 47static katana_id_t katana_id;
47static void __iomem *cpld_base; 48static void __iomem *cpld_base;
48static void __iomem *sram_base; 49static void __iomem *sram_base;
49 50static u32 katana_flash_size_0;
50static u32 katana_flash_size_0; 51static u32 katana_flash_size_1;
51static u32 katana_flash_size_1; 52static u32 katana_bus_frequency;
52 53static struct pci_controller katana_hose_a;
53static u32 katana_bus_frequency;
54 54
55unsigned char __res[sizeof(bd_t)]; 55unsigned char __res[sizeof(bd_t)];
56 56
@@ -71,8 +71,12 @@ katana_irq_lookup_750i(unsigned char idsel, unsigned char pin)
71 KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i }, 71 KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i },
72 /* IDSEL 6 (T8110) */ 72 /* IDSEL 6 (T8110) */
73 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 }, 73 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
74 /* IDSEL 7 (unused) */
75 {0, 0, 0, 0 },
76 /* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */
77 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
74 }; 78 };
75 const long min_idsel = 4, max_idsel = 6, irqs_per_slot = 4; 79 const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4;
76 80
77 return PCI_IRQ_TABLE_LOOKUP; 81 return PCI_IRQ_TABLE_LOOKUP;
78} 82}
@@ -148,7 +152,7 @@ katana_get_proc_num(void)
148 save_exclude = mv64x60_pci_exclude_bridge; 152 save_exclude = mv64x60_pci_exclude_bridge;
149 mv64x60_pci_exclude_bridge = 0; 153 mv64x60_pci_exclude_bridge = 0;
150 154
151 early_read_config_word(bh.hose_a, 0, 155 early_read_config_word(bh.hose_b, 0,
152 PCI_DEVFN(0,0), PCI_DEVICE_ID, &val); 156 PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
153 157
154 mv64x60_pci_exclude_bridge = save_exclude; 158 mv64x60_pci_exclude_bridge = save_exclude;
@@ -191,7 +195,8 @@ katana_setup_bridge(void)
191 struct mv64x60_setup_info si; 195 struct mv64x60_setup_info si;
192 void __iomem *vaddr; 196 void __iomem *vaddr;
193 int i; 197 int i;
194 u16 val; 198 u32 v;
199 u16 val, type;
195 u8 save_exclude; 200 u8 save_exclude;
196 201
197 /* 202 /*
@@ -222,6 +227,20 @@ katana_setup_bridge(void)
222 PCI_DEVICE_ID, val); 227 PCI_DEVICE_ID, val);
223 } 228 }
224 229
230 /*
231 * While we're in here, set the hotswap register correctly.
232 * Turn off blue LED; mask ENUM#, clear insertion & extraction bits.
233 */
234 early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0),
235 MV64360_PCICFG_CPCI_HOTSWAP, &v);
236 v &= ~(1<<19);
237 v |= ((1<<17) | (1<<22) | (1<<23));
238 early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0),
239 MV64360_PCICFG_CPCI_HOTSWAP, v);
240
241 /* While we're at it, grab the bridge type for later */
242 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type);
243
225 mv64x60_pci_exclude_bridge = save_exclude; 244 mv64x60_pci_exclude_bridge = save_exclude;
226 iounmap(vaddr); 245 iounmap(vaddr);
227 246
@@ -251,21 +270,23 @@ katana_setup_bridge(void)
251 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; 270 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
252 271
253 si.pci_1.acc_cntl_options[i] = 272 si.pci_1.acc_cntl_options[i] =
254 MV64360_PCI_ACC_CNTL_SNOOP_NONE | 273 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
255 MV64360_PCI_ACC_CNTL_SWAP_NONE | 274 MV64360_PCI_ACC_CNTL_SWAP_NONE |
256 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | 275 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
257 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; 276 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
258#else 277#else
259 si.cpu_prot_options[i] = 0; 278 si.cpu_prot_options[i] = 0;
260 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */ 279 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
261 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */ 280 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
262 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */ 281 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
263 282
264 si.pci_1.acc_cntl_options[i] = 283 si.pci_1.acc_cntl_options[i] =
265 MV64360_PCI_ACC_CNTL_SNOOP_WB | 284 MV64360_PCI_ACC_CNTL_SNOOP_WB |
266 MV64360_PCI_ACC_CNTL_SWAP_NONE | 285 MV64360_PCI_ACC_CNTL_SWAP_NONE |
267 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | 286 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
268 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; 287 ((type == PCI_DEVICE_ID_MARVELL_MV64360) ?
288 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES :
289 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES);
269#endif 290#endif
270 } 291 }
271 292
@@ -281,12 +302,26 @@ katana_setup_bridge(void)
281 mv64x60_set_bus(&bh, 1, 0); 302 mv64x60_set_bus(&bh, 1, 0);
282 bh.hose_b->first_busno = 0; 303 bh.hose_b->first_busno = 0;
283 bh.hose_b->last_busno = 0xff; 304 bh.hose_b->last_busno = 0xff;
305
306 /*
307 * Need to access hotswap reg which is in the pci config area of the
308 * bridge's hose 0. Note that pcibios_alloc_controller() can't be used
309 * to alloc hose_a b/c that would make hose 0 known to the generic
310 * pci code which we don't want.
311 */
312 bh.hose_a = &katana_hose_a;
313 setup_indirect_pci_nomap(bh.hose_a,
314 bh.v_base + MV64x60_PCI0_CONFIG_ADDR,
315 bh.v_base + MV64x60_PCI0_CONFIG_DATA);
284} 316}
285 317
286/* Bridge & platform setup routines */ 318/* Bridge & platform setup routines */
287void __init 319void __init
288katana_intr_setup(void) 320katana_intr_setup(void)
289{ 321{
322 if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */
323 mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15);
324
290 /* MPP 8, 9, and 10 */ 325 /* MPP 8, 9, and 10 */
291 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff); 326 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
292 327
@@ -309,9 +344,16 @@ katana_intr_setup(void)
309 /* Config GPP intr ctlr to respond to level trigger */ 344 /* Config GPP intr ctlr to respond to level trigger */
310 mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10)); 345 mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
311 346
312 /* Erranum FEr PCI-#8 */ 347 if (bh.type == MV64x60_TYPE_MV64360) {
313 mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9)); 348 /* Erratum FEr PCI-#9 */
314 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9)); 349 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD,
350 (1<<4) | (1<<5) | (1<<6) | (1<<7));
351 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9));
352 } else {
353 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7));
354 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD,
355 (1<<4) | (1<<5) | (1<<8) | (1<<9));
356 }
315 357
316 /* 358 /*
317 * Dismiss and then enable interrupt on GPP interrupt cause 359 * Dismiss and then enable interrupt on GPP interrupt cause
@@ -473,17 +515,46 @@ katana_setup_arch(void)
473 ppc_md.progress("katana_setup_arch: exit", 0); 515 ppc_md.progress("katana_setup_arch: exit", 0);
474} 516}
475 517
518void
519katana_fixup_resources(struct pci_dev *dev)
520{
521 u16 v16;
522
523 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_LINE_SIZE>>2);
524
525 pci_read_config_word(dev, PCI_COMMAND, &v16);
526 v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK;
527 pci_write_config_word(dev, PCI_COMMAND, v16);
528}
529
530static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
531 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/
532 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/
533};
534
535static int
536katana_get_cpu_freq(void)
537{
538 unsigned long pll_cfg;
539
540 pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
541 return katana_bus_frequency * cpu_750xx[pll_cfg]/2;
542}
543
476/* Platform device data fixup routines. */ 544/* Platform device data fixup routines. */
477#if defined(CONFIG_SERIAL_MPSC) 545#if defined(CONFIG_SERIAL_MPSC)
478static void __init 546static void __init
479katana_fixup_mpsc_pdata(struct platform_device *pdev) 547katana_fixup_mpsc_pdata(struct platform_device *pdev)
480{ 548{
481 struct mpsc_pdata *pdata; 549 struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
550 bd_t *bdp = (bd_t *)__res;
482 551
483 pdata = (struct mpsc_pdata *)pdev->dev.platform_data; 552 if (bdp->bi_baudrate)
553 pdata->default_baud = bdp->bi_baudrate;
554 else
555 pdata->default_baud = KATANA_DEFAULT_BAUD;
484 556
485 pdata->max_idle = 40; 557 pdata->max_idle = 40;
486 pdata->default_baud = KATANA_DEFAULT_BAUD;
487 pdata->brg_clk_src = KATANA_MPSC_CLK_SRC; 558 pdata->brg_clk_src = KATANA_MPSC_CLK_SRC;
488 /* 559 /*
489 * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts, 560 * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
@@ -513,6 +584,18 @@ katana_fixup_eth_pdata(struct platform_device *pdev)
513} 584}
514#endif 585#endif
515 586
587#if defined(CONFIG_SYSFS)
588static void __init
589katana_fixup_mv64xxx_pdata(struct platform_device *pdev)
590{
591 struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *)
592 pdev->dev.platform_data;
593
594 /* Katana supports the mv64xxx hotswap register */
595 pdata->hs_reg_valid = 1;
596}
597#endif
598
516static int __init 599static int __init
517katana_platform_notify(struct device *dev) 600katana_platform_notify(struct device *dev)
518{ 601{
@@ -529,6 +612,9 @@ katana_platform_notify(struct device *dev)
529 { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata }, 612 { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata },
530 { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata }, 613 { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata },
531#endif 614#endif
615#if defined(CONFIG_SYSFS)
616 { MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata },
617#endif
532 }; 618 };
533 struct platform_device *pdev; 619 struct platform_device *pdev;
534 int i; 620 int i;
@@ -536,8 +622,7 @@ katana_platform_notify(struct device *dev)
536 if (dev && dev->bus_id) 622 if (dev && dev->bus_id)
537 for (i=0; i<ARRAY_SIZE(dev_map); i++) 623 for (i=0; i<ARRAY_SIZE(dev_map); i++)
538 if (!strncmp(dev->bus_id, dev_map[i].bus_id, 624 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
539 BUS_ID_SIZE)) { 625 BUS_ID_SIZE)) {
540
541 pdev = container_of(dev, 626 pdev = container_of(dev,
542 struct platform_device, dev); 627 struct platform_device, dev);
543 dev_map[i].rtn(pdev); 628 dev_map[i].rtn(pdev);
@@ -578,8 +663,7 @@ katana_setup_mtd(void)
578 ptbl_entries = (size >= (64*MB)) ? 6 : 4; 663 ptbl_entries = (size >= (64*MB)) ? 6 : 4;
579 664
580 if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition), 665 if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
581 GFP_KERNEL)) == NULL) { 666 GFP_KERNEL)) == NULL) {
582
583 printk(KERN_WARNING "Can't alloc MTD partition table\n"); 667 printk(KERN_WARNING "Can't alloc MTD partition table\n");
584 return -ENOMEM; 668 return -ENOMEM;
585 } 669 }
@@ -611,7 +695,6 @@ katana_setup_mtd(void)
611 physmap_set_partitions(ptbl, ptbl_entries); 695 physmap_set_partitions(ptbl, ptbl_entries);
612 return 0; 696 return 0;
613} 697}
614
615arch_initcall(katana_setup_mtd); 698arch_initcall(katana_setup_mtd);
616#endif 699#endif
617 700
@@ -632,7 +715,22 @@ katana_halt(void)
632{ 715{
633 u8 v; 716 u8 v;
634 717
635 if (katana_id == KATANA_ID_752I) { 718 /* Turn on blue LED to indicate its okay to remove */
719 if (katana_id == KATANA_ID_750I) {
720 u32 v;
721 u8 save_exclude;
722
723 /* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */
724 save_exclude = mv64x60_pci_exclude_bridge;
725 mv64x60_pci_exclude_bridge = 0;
726 early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
727 MV64360_PCICFG_CPCI_HOTSWAP, &v);
728 v &= 0xff;
729 v |= (1 << 19);
730 early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
731 MV64360_PCICFG_CPCI_HOTSWAP, v);
732 mv64x60_pci_exclude_bridge = save_exclude;
733 } else if (katana_id == KATANA_ID_752I) {
636 v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF); 734 v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF);
637 v |= HSL_PLD_HOT_SWAP_LED_BIT; 735 v |= HSL_PLD_HOT_SWAP_LED_BIT;
638 out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v); 736 out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v);
@@ -652,37 +750,65 @@ katana_power_off(void)
652static int 750static int
653katana_show_cpuinfo(struct seq_file *m) 751katana_show_cpuinfo(struct seq_file *m)
654{ 752{
753 char *s;
754
755 seq_printf(m, "cpu freq\t: %dMHz\n",
756 (katana_get_cpu_freq() + 500000) / 1000000);
757 seq_printf(m, "bus freq\t: %ldMHz\n",
758 ((long)katana_bus_frequency + 500000) / 1000000);
655 seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n"); 759 seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n");
656 760
657 seq_printf(m, "board\t\t: "); 761 seq_printf(m, "board\t\t: ");
658
659 switch (katana_id) { 762 switch (katana_id) {
660 case KATANA_ID_3750: 763 case KATANA_ID_3750:
661 seq_printf(m, "Katana 3750\n"); 764 seq_printf(m, "Katana 3750");
662 break; 765 break;
663 766
664 case KATANA_ID_750I: 767 case KATANA_ID_750I:
665 seq_printf(m, "Katana 750i\n"); 768 seq_printf(m, "Katana 750i");
666 break; 769 break;
667 770
668 case KATANA_ID_752I: 771 case KATANA_ID_752I:
669 seq_printf(m, "Katana 752i\n"); 772 seq_printf(m, "Katana 752i");
670 break; 773 break;
671 774
672 default: 775 default:
673 seq_printf(m, "Unknown\n"); 776 seq_printf(m, "Unknown");
674 break; 777 break;
675 } 778 }
676 779 seq_printf(m, " (product id: 0x%x)\n",
677 seq_printf(m, "product ID\t: 0x%x\n",
678 in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)); 780 in_8(cpld_base + KATANA_CPLD_PRODUCT_ID));
781
782 seq_printf(m, "pci mode\t: %sMonarch\n",
783 katana_is_monarch()? "" : "Non-");
679 seq_printf(m, "hardware rev\t: 0x%x\n", 784 seq_printf(m, "hardware rev\t: 0x%x\n",
680 in_8(cpld_base+KATANA_CPLD_HARDWARE_VER)); 785 in_8(cpld_base+KATANA_CPLD_HARDWARE_VER));
681 seq_printf(m, "PLD rev\t\t: 0x%x\n", 786 seq_printf(m, "pld rev\t\t: 0x%x\n",
682 in_8(cpld_base + KATANA_CPLD_PLD_VER)); 787 in_8(cpld_base + KATANA_CPLD_PLD_VER));
683 seq_printf(m, "PLB freq\t: %ldMhz\n", 788
684 (long)katana_bus_frequency / 1000000); 789 switch(bh.type) {
685 seq_printf(m, "PCI\t\t: %sMonarch\n", katana_is_monarch()? "" : "Non-"); 790 case MV64x60_TYPE_GT64260A:
791 s = "gt64260a";
792 break;
793 case MV64x60_TYPE_GT64260B:
794 s = "gt64260b";
795 break;
796 case MV64x60_TYPE_MV64360:
797 s = "mv64360";
798 break;
799 case MV64x60_TYPE_MV64460:
800 s = "mv64460";
801 break;
802 default:
803 s = "Unknown";
804 }
805 seq_printf(m, "bridge type\t: %s\n", s);
806 seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
807#if defined(CONFIG_NOT_COHERENT_CACHE)
808 seq_printf(m, "coherency\t: %s\n", "off");
809#else
810 seq_printf(m, "coherency\t: %s\n", "on");
811#endif
686 812
687 return 0; 813 return 0;
688} 814}
@@ -701,11 +827,20 @@ katana_calibrate_decr(void)
701 tb_to_us = mulhwu_scale_factor(freq, 1000000); 827 tb_to_us = mulhwu_scale_factor(freq, 1000000);
702} 828}
703 829
830/*
831 * The katana supports both uImage and zImage. If uImage, get the mem size
832 * from the bd info. If zImage, the bootwrapper adds a BI_MEMSIZE entry in
833 * the bi_rec data which is sucked out and put into boot_mem_size by
834 * parse_bootinfo(). MMU_init() will then use the boot_mem_size for the mem
835 * size and not call this routine. The only way this will fail is when a uImage
836 * is used but the fw doesn't pass in a valid bi_memsize. This should never
837 * happen, though.
838 */
704unsigned long __init 839unsigned long __init
705katana_find_end_of_memory(void) 840katana_find_end_of_memory(void)
706{ 841{
707 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE, 842 bd_t *bdp = (bd_t *)__res;
708 MV64x60_TYPE_MV64360); 843 return bdp->bi_memsize;
709} 844}
710 845
711#if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00) 846#if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00)
@@ -729,15 +864,6 @@ katana_rtc_hookup(void)
729late_initcall(katana_rtc_hookup); 864late_initcall(katana_rtc_hookup);
730#endif 865#endif
731 866
732static inline void
733katana_set_bat(void)
734{
735 mb();
736 mtspr(SPRN_DBAT2U, 0xf0001ffe);
737 mtspr(SPRN_DBAT2L, 0xf000002a);
738 mb();
739}
740
741#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) 867#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
742static void __init 868static void __init
743katana_map_io(void) 869katana_map_io(void)
@@ -763,15 +889,24 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
763 */ 889 */
764 if (r3 && r6) { 890 if (r3 && r6) {
765 /* copy board info structure */ 891 /* copy board info structure */
766 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); 892 memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t));
767 /* copy command line */ 893 /* copy command line */
768 *(char *)(r7+KERNELBASE) = 0; 894 *(char *)(r7+KERNELBASE) = 0;
769 strcpy(cmd_line, (char *)(r6+KERNELBASE)); 895 strcpy(cmd_line, (char *)(r6+KERNELBASE));
770 } 896 }
771 897
898#ifdef CONFIG_BLK_DEV_INITRD
899 /* take care of initrd if we have one */
900 if (r4) {
901 initrd_start = r4 + KERNELBASE;
902 initrd_end = r5 + KERNELBASE;
903 }
904#endif /* CONFIG_BLK_DEV_INITRD */
905
772 isa_mem_base = 0; 906 isa_mem_base = 0;
773 907
774 ppc_md.setup_arch = katana_setup_arch; 908 ppc_md.setup_arch = katana_setup_arch;
909 ppc_md.pcibios_fixup_resources = katana_fixup_resources;
775 ppc_md.show_cpuinfo = katana_show_cpuinfo; 910 ppc_md.show_cpuinfo = katana_show_cpuinfo;
776 ppc_md.init_IRQ = mv64360_init_irq; 911 ppc_md.init_IRQ = mv64360_init_irq;
777 ppc_md.get_irq = mv64360_get_irq; 912 ppc_md.get_irq = mv64360_get_irq;
@@ -790,6 +925,4 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
790#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) 925#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
791 platform_notify = katana_platform_notify; 926 platform_notify = katana_platform_notify;
792#endif 927#endif
793
794 katana_set_bat(); /* Need for katana_find_end_of_memory and progress */
795} 928}
diff --git a/arch/ppc/platforms/katana.h b/arch/ppc/platforms/katana.h
index b82ed81950f5..597257eff2ec 100644
--- a/arch/ppc/platforms/katana.h
+++ b/arch/ppc/platforms/katana.h
@@ -56,14 +56,14 @@
56#define KATANA_PCI1_IO_SIZE 0x04000000 /* 64 MB */ 56#define KATANA_PCI1_IO_SIZE 0x04000000 /* 64 MB */
57 57
58/* Board-specific IRQ info */ 58/* Board-specific IRQ info */
59#define KATANA_PCI_INTA_IRQ_3750 64+8 59#define KATANA_PCI_INTA_IRQ_3750 (64+8)
60#define KATANA_PCI_INTB_IRQ_3750 64+9 60#define KATANA_PCI_INTB_IRQ_3750 (64+9)
61#define KATANA_PCI_INTC_IRQ_3750 64+10 61#define KATANA_PCI_INTC_IRQ_3750 (64+10)
62 62
63#define KATANA_PCI_INTA_IRQ_750i 64+8 63#define KATANA_PCI_INTA_IRQ_750i (64+8)
64#define KATANA_PCI_INTB_IRQ_750i 64+9 64#define KATANA_PCI_INTB_IRQ_750i (64+9)
65#define KATANA_PCI_INTC_IRQ_750i 64+10 65#define KATANA_PCI_INTC_IRQ_750i (64+10)
66#define KATANA_PCI_INTD_IRQ_750i 64+14 66#define KATANA_PCI_INTD_IRQ_750i (64+14)
67 67
68#define KATANA_CPLD_RST_EVENT 0x00000000 68#define KATANA_CPLD_RST_EVENT 0x00000000
69#define KATANA_CPLD_RST_CMD 0x00001000 69#define KATANA_CPLD_RST_CMD 0x00001000
diff --git a/arch/ppc/platforms/mcpn765.c b/arch/ppc/platforms/mcpn765.c
deleted file mode 100644
index e88d294ea593..000000000000
--- a/arch/ppc/platforms/mcpn765.c
+++ /dev/null
@@ -1,527 +0,0 @@
1/*
2 * arch/ppc/platforms/mcpn765.c
3 *
4 * Board setup routines for the Motorola MCG MCPN765 cPCI Board.
5 *
6 * Author: Mark A. Greer
7 * mgreer@mvista.com
8 *
9 * Modified by Randy Vinson (rvinson@mvista.com)
10 *
11 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17/*
18 * This file adds support for the Motorola MCG MCPN765.
19 */
20#include <linux/config.h>
21#include <linux/stddef.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/errno.h>
25#include <linux/reboot.h>
26#include <linux/pci.h>
27#include <linux/kdev_t.h>
28#include <linux/major.h>
29#include <linux/initrd.h>
30#include <linux/console.h>
31#include <linux/delay.h>
32#include <linux/irq.h>
33#include <linux/seq_file.h>
34#include <linux/root_dev.h>
35#include <linux/serial.h>
36#include <linux/tty.h> /* for linux/serial_core.h */
37#include <linux/serial_core.h>
38#include <linux/slab.h>
39
40#include <asm/system.h>
41#include <asm/pgtable.h>
42#include <asm/page.h>
43#include <asm/time.h>
44#include <asm/dma.h>
45#include <asm/byteorder.h>
46#include <asm/io.h>
47#include <asm/machdep.h>
48#include <asm/prom.h>
49#include <asm/smp.h>
50#include <asm/open_pic.h>
51#include <asm/i8259.h>
52#include <asm/todc.h>
53#include <asm/pci-bridge.h>
54#include <asm/irq.h>
55#include <asm/uaccess.h>
56#include <asm/bootinfo.h>
57#include <asm/hawk.h>
58#include <asm/kgdb.h>
59
60#include "mcpn765.h"
61
62static u_char mcpn765_openpic_initsenses[] __initdata = {
63 (IRQ_SENSE_EDGE | IRQ_POLARITY_POSITIVE),/* 16: i8259 cascade */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 17: COM1,2,3,4 */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 18: Enet 1 (front) */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 19: HAWK WDT XXXX */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 20: 21554 bridge */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 21: cPCI INTA# */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 22: cPCI INTB# */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 23: cPCI INTC# */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 24: cPCI INTD# */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 25: PMC1 INTA#,PMC2 INTB#*/
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 26: PMC1 INTB#,PMC2 INTC#*/
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 27: PMC1 INTC#,PMC2 INTD#*/
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 28: PMC1 INTD#,PMC2 INTA#*/
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 29: Enet 2 (J3) */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 30: Abort Switch */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/* 31: RTC Alarm */
79};
80
81extern void mcpn765_set_VIA_IDE_native(void);
82
83extern u_int openpic_irq(void);
84extern char cmd_line[];
85
86extern void gen550_progress(char *, unsigned short);
87extern void gen550_init(int, struct uart_port *);
88
89int use_of_interrupt_tree = 0;
90
91static void mcpn765_halt(void);
92
93TODC_ALLOC();
94
95/*
96 * Motorola MCG MCPN765 interrupt routing.
97 */
98static inline int
99mcpn765_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
100{
101 static char pci_irq_table[][4] =
102 /*
103 * PCI IDSEL/INTPIN->INTLINE
104 * A B C D
105 */
106 {
107 { 14, 0, 0, 0 }, /* IDSEL 11 - have to manually set */
108 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
109 { 0, 0, 0, 0 }, /* IDSEL 13 - unused */
110 { 18, 0, 0, 0 }, /* IDSEL 14 - Enet 0 */
111 { 0, 0, 0, 0 }, /* IDSEL 15 - unused */
112 { 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
113 { 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */
114 { 0, 0, 0, 0 }, /* IDSEL 18 - PMC 2B Connector XXXX */
115 { 29, 0, 0, 0 }, /* IDSEL 19 - Enet 1 */
116 { 20, 0, 0, 0 }, /* IDSEL 20 - 21554 cPCI bridge */
117 };
118
119 const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4;
120 return PCI_IRQ_TABLE_LOOKUP;
121}
122
123void __init
124mcpn765_set_VIA_IDE_legacy(void)
125{
126 unsigned short vend, dev;
127
128 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
129 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
130
131 if ((vend == PCI_VENDOR_ID_VIA) &&
132 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
133
134 unsigned char temp;
135
136 /* put back original "standard" port base addresses */
137 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
138 PCI_BASE_ADDRESS_0, 0x1f1);
139 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
140 PCI_BASE_ADDRESS_1, 0x3f5);
141 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
142 PCI_BASE_ADDRESS_2, 0x171);
143 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
144 PCI_BASE_ADDRESS_3, 0x375);
145 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
146 PCI_BASE_ADDRESS_4, 0xcc01);
147
148 /* put into legacy mode */
149 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
150 &temp);
151 temp &= ~0x05;
152 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
153 temp);
154 }
155}
156
157void
158mcpn765_set_VIA_IDE_native(void)
159{
160 unsigned short vend, dev;
161
162 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
163 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
164
165 if ((vend == PCI_VENDOR_ID_VIA) &&
166 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
167
168 unsigned char temp;
169
170 /* put into native mode */
171 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
172 &temp);
173 temp |= 0x05;
174 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
175 temp);
176 }
177}
178
179/*
180 * Initialize the VIA 82c586b.
181 */
182static void __init
183mcpn765_setup_via_82c586b(void)
184{
185 struct pci_dev *dev;
186 u_char c;
187
188 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
189 PCI_DEVICE_ID_VIA_82C586_0,
190 NULL)) == NULL) {
191 printk("No VIA ISA bridge found\n");
192 mcpn765_halt();
193 /* NOTREACHED */
194 }
195
196 /*
197 * If the firmware left the EISA 4d0/4d1 ports enabled, make sure
198 * IRQ 14 is set for edge.
199 */
200 pci_read_config_byte(dev, 0x47, &c);
201
202 if (c & (1<<5)) {
203 c = inb(0x4d1);
204 c &= ~(1<<6);
205 outb(c, 0x4d1);
206 }
207
208 /* Disable PNP IRQ routing since we use the Hawk's MPIC */
209 pci_write_config_dword(dev, 0x54, 0);
210 pci_write_config_byte(dev, 0x58, 0);
211
212 pci_dev_put(dev);
213 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
214 PCI_DEVICE_ID_VIA_82C586_1,
215 NULL)) == NULL) {
216 printk("No VIA ISA bridge found\n");
217 mcpn765_halt();
218 /* NOTREACHED */
219 }
220
221 /*
222 * PPCBug doesn't set the enable bits for the IDE device.
223 * Turn them on now.
224 */
225 pci_read_config_byte(dev, 0x40, &c);
226 c |= 0x03;
227 pci_write_config_byte(dev, 0x40, c);
228 pci_dev_put(dev);
229
230 return;
231}
232
233void __init
234mcpn765_pcibios_fixup(void)
235{
236 /* Do MCPN765 board specific initialization. */
237 mcpn765_setup_via_82c586b();
238}
239
240void __init
241mcpn765_find_bridges(void)
242{
243 struct pci_controller *hose;
244
245 hose = pcibios_alloc_controller();
246
247 if (!hose)
248 return;
249
250 hose->first_busno = 0;
251 hose->last_busno = 0xff;
252 hose->pci_mem_offset = MCPN765_PCI_PHY_MEM_OFFSET;
253
254 pci_init_resource(&hose->io_resource,
255 MCPN765_PCI_IO_START,
256 MCPN765_PCI_IO_END,
257 IORESOURCE_IO,
258 "PCI host bridge");
259
260 pci_init_resource(&hose->mem_resources[0],
261 MCPN765_PCI_MEM_START,
262 MCPN765_PCI_MEM_END,
263 IORESOURCE_MEM,
264 "PCI host bridge");
265
266 hose->io_space.start = MCPN765_PCI_IO_START;
267 hose->io_space.end = MCPN765_PCI_IO_END;
268 hose->mem_space.start = MCPN765_PCI_MEM_START;
269 hose->mem_space.end = MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE;
270
271 if (hawk_init(hose,
272 MCPN765_HAWK_PPC_REG_BASE,
273 MCPN765_PROC_PCI_MEM_START,
274 MCPN765_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
275 MCPN765_PROC_PCI_IO_START,
276 MCPN765_PROC_PCI_IO_END,
277 MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE + 1) != 0) {
278 printk("Could not initialize HAWK bridge\n");
279 }
280
281 /* VIA IDE BAR decoders are only 16-bits wide. PCI Auto Config
282 * will reassign the bars outside of 16-bit I/O space, which will
283 * "break" things. To prevent this, we'll set the IDE chip into
284 * legacy mode and seed the bars with their legacy addresses (in 16-bit
285 * I/O space). The Auto Config code will skip the IDE contoller in
286 * legacy mode, so our bar values will stick.
287 */
288 mcpn765_set_VIA_IDE_legacy();
289
290 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
291
292 /* Now that we've got 16-bit addresses in the bars, we can switch the
293 * IDE controller back into native mode so we can do "modern" resource
294 * and interrupt management.
295 */
296 mcpn765_set_VIA_IDE_native();
297
298 ppc_md.pcibios_fixup = mcpn765_pcibios_fixup;
299 ppc_md.pcibios_fixup_bus = NULL;
300 ppc_md.pci_swizzle = common_swizzle;
301 ppc_md.pci_map_irq = mcpn765_map_irq;
302
303 return;
304}
305static void __init
306mcpn765_setup_arch(void)
307{
308 struct pci_controller *hose;
309
310 if ( ppc_md.progress )
311 ppc_md.progress("mcpn765_setup_arch: enter", 0);
312
313 loops_per_jiffy = 50000000 / HZ;
314
315#ifdef CONFIG_BLK_DEV_INITRD
316 if (initrd_start)
317 ROOT_DEV = Root_RAM0;
318 else
319#endif
320#ifdef CONFIG_ROOT_NFS
321 ROOT_DEV = Root_NFS;
322#else
323 ROOT_DEV = Root_SDA2;
324#endif
325
326 if ( ppc_md.progress )
327 ppc_md.progress("mcpn765_setup_arch: find_bridges", 0);
328
329 /* Lookup PCI host bridges */
330 mcpn765_find_bridges();
331
332 hose = pci_bus_to_hose(0);
333 isa_io_base = (ulong)hose->io_base_virt;
334
335 TODC_INIT(TODC_TYPE_MK48T37,
336 (MCPN765_PHYS_NVRAM_AS0 - isa_io_base),
337 (MCPN765_PHYS_NVRAM_AS1 - isa_io_base),
338 (MCPN765_PHYS_NVRAM_DATA - isa_io_base),
339 8);
340
341 OpenPIC_InitSenses = mcpn765_openpic_initsenses;
342 OpenPIC_NumInitSenses = sizeof(mcpn765_openpic_initsenses);
343
344 printk("Motorola MCG MCPN765 cPCI Non-System Board\n");
345 printk("MCPN765 port (MontaVista Software, Inc. (source@mvista.com))\n");
346
347 if ( ppc_md.progress )
348 ppc_md.progress("mcpn765_setup_arch: exit", 0);
349
350 return;
351}
352
353static void __init
354mcpn765_init2(void)
355{
356
357 request_region(0x00,0x20,"dma1");
358 request_region(0x20,0x20,"pic1");
359 request_region(0x40,0x20,"timer");
360 request_region(0x80,0x10,"dma page reg");
361 request_region(0xa0,0x20,"pic2");
362 request_region(0xc0,0x20,"dma2");
363
364 return;
365}
366
367/*
368 * Interrupt setup and service.
369 * Have MPIC on HAWK and cascaded 8259s on VIA 82586 cascaded to MPIC.
370 */
371static void __init
372mcpn765_init_IRQ(void)
373{
374 int i;
375
376 if ( ppc_md.progress )
377 ppc_md.progress("init_irq: enter", 0);
378
379 openpic_init(NUM_8259_INTERRUPTS);
380 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
381 i8259_irq);
382
383 for(i=0; i < NUM_8259_INTERRUPTS; i++)
384 irq_desc[i].handler = &i8259_pic;
385
386 i8259_init(0);
387
388 if ( ppc_md.progress )
389 ppc_md.progress("init_irq: exit", 0);
390
391 return;
392}
393
394static u32
395mcpn765_irq_canonicalize(u32 irq)
396{
397 if (irq == 2)
398 return 9;
399 else
400 return irq;
401}
402
403static unsigned long __init
404mcpn765_find_end_of_memory(void)
405{
406 return hawk_get_mem_size(MCPN765_HAWK_SMC_BASE);
407}
408
409static void __init
410mcpn765_map_io(void)
411{
412 io_block_mapping(0xfe800000, 0xfe800000, 0x00800000, _PAGE_IO);
413}
414
415static void
416mcpn765_reset_board(void)
417{
418 local_irq_disable();
419
420 /* set VIA IDE controller into native mode */
421 mcpn765_set_VIA_IDE_native();
422
423 /* Set exception prefix high - to the firmware */
424 _nmask_and_or_msr(0, MSR_IP);
425
426 out_8((u_char *)MCPN765_BOARD_MODRST_REG, 0x01);
427
428 return;
429}
430
431static void
432mcpn765_restart(char *cmd)
433{
434 volatile ulong i = 10000000;
435
436 mcpn765_reset_board();
437
438 while (i-- > 0);
439 panic("restart failed\n");
440}
441
442static void
443mcpn765_power_off(void)
444{
445 mcpn765_halt();
446 /* NOTREACHED */
447}
448
449static void
450mcpn765_halt(void)
451{
452 local_irq_disable();
453 while (1);
454 /* NOTREACHED */
455}
456
457static int
458mcpn765_show_cpuinfo(struct seq_file *m)
459{
460 seq_printf(m, "vendor\t\t: Motorola MCG\n");
461 seq_printf(m, "machine\t\t: MCPN765\n");
462
463 return 0;
464}
465
466/*
467 * Set BAT 3 to map 0xf0000000 to end of physical memory space.
468 */
469static __inline__ void
470mcpn765_set_bat(void)
471{
472 mb();
473 mtspr(SPRN_DBAT1U, 0xfe8000fe);
474 mtspr(SPRN_DBAT1L, 0xfe80002a);
475 mb();
476}
477
478void __init
479platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
480 unsigned long r6, unsigned long r7)
481{
482 parse_bootinfo(find_bootinfo());
483
484 /* Map in board regs, etc. */
485 mcpn765_set_bat();
486
487 isa_mem_base = MCPN765_ISA_MEM_BASE;
488 pci_dram_offset = MCPN765_PCI_DRAM_OFFSET;
489 ISA_DMA_THRESHOLD = 0x00ffffff;
490 DMA_MODE_READ = 0x44;
491 DMA_MODE_WRITE = 0x48;
492
493 ppc_md.setup_arch = mcpn765_setup_arch;
494 ppc_md.show_cpuinfo = mcpn765_show_cpuinfo;
495 ppc_md.irq_canonicalize = mcpn765_irq_canonicalize;
496 ppc_md.init_IRQ = mcpn765_init_IRQ;
497 ppc_md.get_irq = openpic_get_irq;
498 ppc_md.init = mcpn765_init2;
499
500 ppc_md.restart = mcpn765_restart;
501 ppc_md.power_off = mcpn765_power_off;
502 ppc_md.halt = mcpn765_halt;
503
504 ppc_md.find_end_of_memory = mcpn765_find_end_of_memory;
505 ppc_md.setup_io_mappings = mcpn765_map_io;
506
507 ppc_md.time_init = todc_time_init;
508 ppc_md.set_rtc_time = todc_set_rtc_time;
509 ppc_md.get_rtc_time = todc_get_rtc_time;
510 ppc_md.calibrate_decr = todc_calibrate_decr;
511
512 ppc_md.nvram_read_val = todc_m48txx_read_val;
513 ppc_md.nvram_write_val = todc_m48txx_write_val;
514
515 ppc_md.heartbeat = NULL;
516 ppc_md.heartbeat_reset = 0;
517 ppc_md.heartbeat_count = 0;
518
519#ifdef CONFIG_SERIAL_TEXT_DEBUG
520 ppc_md.progress = gen550_progress;
521#endif
522#ifdef CONFIG_KGDB
523 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
524#endif
525
526 return;
527}
diff --git a/arch/ppc/platforms/mcpn765.h b/arch/ppc/platforms/mcpn765.h
deleted file mode 100644
index 4d35ecad097b..000000000000
--- a/arch/ppc/platforms/mcpn765.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * arch/ppc/platforms/mcpn765.h
3 *
4 * Definitions for Motorola MCG MCPN765 cPCI Board.
5 *
6 * Author: Mark A. Greer
7 * mgreer@mvista.com
8 *
9 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15/*
16 * From Processor to PCI:
17 * PCI Mem Space: 0x80000000 - 0xc0000000 -> 0x80000000 - 0xc0000000 (1 GB)
18 * PCI I/O Space: 0xfd800000 - 0xfe000000 -> 0x00000000 - 0x00800000 (8 MB)
19 * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
20 * MPIC in PCI Mem Space: 0xfe800000 - 0xfe830000 (not all used by MPIC)
21 *
22 * From PCI to Processor:
23 * System Memory: 0x00000000 -> 0x00000000
24 */
25
26#ifndef __PPC_PLATFORMS_MCPN765_H
27#define __PPC_PLATFORMS_MCPN765_H
28#include <linux/config.h>
29
30/* PCI Memory space mapping info */
31#define MCPN765_PCI_MEM_SIZE 0x40000000U
32#define MCPN765_PROC_PCI_MEM_START 0x80000000U
33#define MCPN765_PROC_PCI_MEM_END (MCPN765_PROC_PCI_MEM_START + \
34 MCPN765_PCI_MEM_SIZE - 1)
35#define MCPN765_PCI_MEM_START 0x80000000U
36#define MCPN765_PCI_MEM_END (MCPN765_PCI_MEM_START + \
37 MCPN765_PCI_MEM_SIZE - 1)
38
39/* PCI I/O space mapping info */
40#define MCPN765_PCI_IO_SIZE 0x00800000U
41#define MCPN765_PROC_PCI_IO_START 0xfd800000U
42#define MCPN765_PROC_PCI_IO_END (MCPN765_PROC_PCI_IO_START + \
43 MCPN765_PCI_IO_SIZE - 1)
44#define MCPN765_PCI_IO_START 0x00000000U
45#define MCPN765_PCI_IO_END (MCPN765_PCI_IO_START + \
46 MCPN765_PCI_IO_SIZE - 1)
47
48/* System memory mapping info */
49#define MCPN765_PCI_DRAM_OFFSET 0x00000000U
50#define MCPN765_PCI_PHY_MEM_OFFSET 0x00000000U
51
52#define MCPN765_ISA_MEM_BASE 0x00000000U
53#define MCPN765_ISA_IO_BASE MCPN765_PROC_PCI_IO_START
54
55/* Define base addresses for important sets of registers */
56#define MCPN765_HAWK_MPIC_BASE 0xfe800000U
57#define MCPN765_HAWK_SMC_BASE 0xfef80000U
58#define MCPN765_HAWK_PPC_REG_BASE 0xfeff0000U
59
60/* Define MCPN765 board register addresses. */
61#define MCPN765_BOARD_STATUS_REG 0xfef88080U
62#define MCPN765_BOARD_MODFAIL_REG 0xfef88090U
63#define MCPN765_BOARD_MODRST_REG 0xfef880a0U
64#define MCPN765_BOARD_TBEN_REG 0xfef880c0U
65#define MCPN765_BOARD_GEOGRAPHICAL_REG 0xfef880e8U
66#define MCPN765_BOARD_EXT_FEATURE_REG 0xfef880f0U
67#define MCPN765_BOARD_LAST_RESET_REG 0xfef880f8U
68
69/* Defines for UART */
70
71/* Define the UART base addresses */
72#define MCPN765_SERIAL_1 0xfef88000
73#define MCPN765_SERIAL_2 0xfef88200
74#define MCPN765_SERIAL_3 0xfef88400
75#define MCPN765_SERIAL_4 0xfef88600
76
77#ifdef CONFIG_SERIAL_MANY_PORTS
78#define RS_TABLE_SIZE 64
79#else
80#define RS_TABLE_SIZE 4
81#endif
82
83/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
84#define BASE_BAUD ( 1843200 / 16 )
85#define UART_CLK 1843200
86
87#ifdef CONFIG_SERIAL_DETECT_IRQ
88#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
89#else
90#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
91#endif
92
93/* All UART IRQ's are wire-OR'd to IRQ 17 */
94#define STD_SERIAL_PORT_DFNS \
95 { 0, BASE_BAUD, MCPN765_SERIAL_1, 17, STD_COM_FLAGS, /* ttyS0 */\
96 iomem_base: (u8 *)MCPN765_SERIAL_1, \
97 iomem_reg_shift: 4, \
98 io_type: SERIAL_IO_MEM }, \
99 { 0, BASE_BAUD, MCPN765_SERIAL_2, 17, STD_COM_FLAGS, /* ttyS1 */\
100 iomem_base: (u8 *)MCPN765_SERIAL_2, \
101 iomem_reg_shift: 4, \
102 io_type: SERIAL_IO_MEM }, \
103 { 0, BASE_BAUD, MCPN765_SERIAL_3, 17, STD_COM_FLAGS, /* ttyS2 */\
104 iomem_base: (u8 *)MCPN765_SERIAL_3, \
105 iomem_reg_shift: 4, \
106 io_type: SERIAL_IO_MEM }, \
107 { 0, BASE_BAUD, MCPN765_SERIAL_4, 17, STD_COM_FLAGS, /* ttyS3 */\
108 iomem_base: (u8 *)MCPN765_SERIAL_4, \
109 iomem_reg_shift: 4, \
110 io_type: SERIAL_IO_MEM },
111
112#define SERIAL_PORT_DFNS \
113 STD_SERIAL_PORT_DFNS
114
115/* Define the NVRAM/RTC address strobe & data registers */
116#define MCPN765_PHYS_NVRAM_AS0 0xfef880c8U
117#define MCPN765_PHYS_NVRAM_AS1 0xfef880d0U
118#define MCPN765_PHYS_NVRAM_DATA 0xfef880d8U
119
120extern void mcpn765_find_bridges(void);
121
122#endif /* __PPC_PLATFORMS_MCPN765_H */
diff --git a/arch/ppc/platforms/pcore.c b/arch/ppc/platforms/pcore.c
deleted file mode 100644
index d7191630a650..000000000000
--- a/arch/ppc/platforms/pcore.c
+++ /dev/null
@@ -1,352 +0,0 @@
1/*
2 * arch/ppc/platforms/pcore_setup.c
3 *
4 * Setup routines for Force PCORE boards
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/stddef.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/reboot.h>
20#include <linux/pci.h>
21#include <linux/kdev_t.h>
22#include <linux/types.h>
23#include <linux/major.h>
24#include <linux/initrd.h>
25#include <linux/console.h>
26#include <linux/irq.h>
27#include <linux/seq_file.h>
28#include <linux/root_dev.h>
29
30#include <asm/io.h>
31#include <asm/machdep.h>
32#include <asm/time.h>
33#include <asm/i8259.h>
34#include <asm/mpc10x.h>
35#include <asm/todc.h>
36#include <asm/bootinfo.h>
37#include <asm/kgdb.h>
38
39#include "pcore.h"
40
41extern unsigned long loops_per_jiffy;
42
43static int board_type;
44
45static inline int __init
46pcore_6750_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
47{
48 static char pci_irq_table[][4] =
49 /*
50 * PCI IDSEL/INTPIN->INTLINE
51 * A B C D
52 */
53 {
54 {9, 10, 11, 12}, /* IDSEL 24 - DEC 21554 */
55 {10, 0, 0, 0}, /* IDSEL 25 - DEC 21143 */
56 {11, 12, 9, 10}, /* IDSEL 26 - PMC I */
57 {12, 9, 10, 11}, /* IDSEL 27 - PMC II */
58 {0, 0, 0, 0}, /* IDSEL 28 - unused */
59 {0, 0, 9, 0}, /* IDSEL 29 - unused */
60 {0, 0, 0, 0}, /* IDSEL 30 - Winbond */
61 };
62 const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
63 return PCI_IRQ_TABLE_LOOKUP;
64};
65
66static inline int __init
67pcore_680_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
68{
69 static char pci_irq_table[][4] =
70 /*
71 * PCI IDSEL/INTPIN->INTLINE
72 * A B C D
73 */
74 {
75 {9, 10, 11, 12}, /* IDSEL 24 - Sentinel */
76 {10, 0, 0, 0}, /* IDSEL 25 - i82559 #1 */
77 {11, 12, 9, 10}, /* IDSEL 26 - PMC I */
78 {12, 9, 10, 11}, /* IDSEL 27 - PMC II */
79 {9, 0, 0, 0}, /* IDSEL 28 - i82559 #2 */
80 {0, 0, 0, 0}, /* IDSEL 29 - unused */
81 {0, 0, 0, 0}, /* IDSEL 30 - Winbond */
82 };
83 const long min_idsel = 24, max_idsel = 30, irqs_per_slot = 4;
84 return PCI_IRQ_TABLE_LOOKUP;
85};
86
87void __init
88pcore_pcibios_fixup(void)
89{
90 struct pci_dev *dev;
91
92 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
93 PCI_DEVICE_ID_WINBOND_83C553,
94 0)))
95 {
96 /* Reroute interrupts both IDE channels to 15 */
97 pci_write_config_byte(dev,
98 PCORE_WINBOND_IDE_INT,
99 0xff);
100
101 /* Route INTA-D to IRQ9-12, respectively */
102 pci_write_config_word(dev,
103 PCORE_WINBOND_PCI_INT,
104 0x9abc);
105
106 /*
107 * Set up 8259 edge/level triggering
108 */
109 outb(0x00, PCORE_WINBOND_PRI_EDG_LVL);
110 outb(0x1e, PCORE_WINBOND_SEC_EDG_LVL);
111 pci_dev_put(dev);
112 }
113}
114
115int __init
116pcore_find_bridges(void)
117{
118 struct pci_controller* hose;
119 int host_bridge, board_type;
120
121 hose = pcibios_alloc_controller();
122 if (!hose)
123 return 0;
124
125 mpc10x_bridge_init(hose,
126 MPC10X_MEM_MAP_B,
127 MPC10X_MEM_MAP_B,
128 MPC10X_MAPB_EUMB_BASE);
129
130 /* Determine board type */
131 early_read_config_dword(hose,
132 0,
133 PCI_DEVFN(0,0),
134 PCI_VENDOR_ID,
135 &host_bridge);
136 if (host_bridge == MPC10X_BRIDGE_106)
137 board_type = PCORE_TYPE_6750;
138 else /* MPC10X_BRIDGE_107 */
139 board_type = PCORE_TYPE_680;
140
141 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
142
143 ppc_md.pcibios_fixup = pcore_pcibios_fixup;
144 ppc_md.pci_swizzle = common_swizzle;
145
146 if (board_type == PCORE_TYPE_6750)
147 ppc_md.pci_map_irq = pcore_6750_map_irq;
148 else /* PCORE_TYPE_680 */
149 ppc_md.pci_map_irq = pcore_680_map_irq;
150
151 return board_type;
152}
153
154/* Dummy variable to satisfy mpc10x_common.o */
155void *OpenPIC_Addr;
156
157static int
158pcore_show_cpuinfo(struct seq_file *m)
159{
160 seq_printf(m, "vendor\t\t: Force Computers\n");
161
162 if (board_type == PCORE_TYPE_6750)
163 seq_printf(m, "machine\t\t: PowerCore 6750\n");
164 else /* PCORE_TYPE_680 */
165 seq_printf(m, "machine\t\t: PowerCore 680\n");
166
167 seq_printf(m, "L2\t\t: " );
168 if (board_type == PCORE_TYPE_6750)
169 switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
170 {
171 case PCORE_DCCR_L2_0KB:
172 seq_printf(m, "nocache");
173 break;
174 case PCORE_DCCR_L2_256KB:
175 seq_printf(m, "256KB");
176 break;
177 case PCORE_DCCR_L2_1MB:
178 seq_printf(m, "1MB");
179 break;
180 case PCORE_DCCR_L2_512KB:
181 seq_printf(m, "512KB");
182 break;
183 default:
184 seq_printf(m, "error");
185 break;
186 }
187 else /* PCORE_TYPE_680 */
188 switch (readb(PCORE_DCCR_REG) & PCORE_DCCR_L2_MASK)
189 {
190 case PCORE_DCCR_L2_2MB:
191 seq_printf(m, "2MB");
192 break;
193 case PCORE_DCCR_L2_256KB:
194 seq_printf(m, "reserved");
195 break;
196 case PCORE_DCCR_L2_1MB:
197 seq_printf(m, "1MB");
198 break;
199 case PCORE_DCCR_L2_512KB:
200 seq_printf(m, "512KB");
201 break;
202 default:
203 seq_printf(m, "error");
204 break;
205 }
206
207 seq_printf(m, "\n");
208
209 return 0;
210}
211
212static void __init
213pcore_setup_arch(void)
214{
215 /* init to some ~sane value until calibrate_delay() runs */
216 loops_per_jiffy = 50000000/HZ;
217
218 /* Lookup PCI host bridges */
219 board_type = pcore_find_bridges();
220
221#ifdef CONFIG_BLK_DEV_INITRD
222 if (initrd_start)
223 ROOT_DEV = Root_RAM0;
224 else
225#endif
226#ifdef CONFIG_ROOT_NFS
227 ROOT_DEV = Root_NFS;
228#else
229 ROOT_DEV = Root_SDA2;
230#endif
231
232 printk(KERN_INFO "Force PowerCore ");
233 if (board_type == PCORE_TYPE_6750)
234 printk("6750\n");
235 else
236 printk("680\n");
237 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
238 _set_L2CR(L2CR_L2E | _get_L2CR());
239
240}
241
242static void
243pcore_restart(char *cmd)
244{
245 local_irq_disable();
246 /* Hard reset */
247 writeb(0x11, 0xfe000332);
248 while(1);
249}
250
251static void
252pcore_halt(void)
253{
254 local_irq_disable();
255 /* Turn off user LEDs */
256 writeb(0x00, 0xfe000300);
257 while (1);
258}
259
260static void
261pcore_power_off(void)
262{
263 pcore_halt();
264}
265
266
267static void __init
268pcore_init_IRQ(void)
269{
270 int i;
271
272 for ( i = 0 ; i < 16 ; i++ )
273 irq_desc[i].handler = &i8259_pic;
274
275 i8259_init(0);
276}
277
278/*
279 * Set BAT 3 to map 0xf0000000 to end of physical memory space.
280 */
281static __inline__ void
282pcore_set_bat(void)
283{
284 mb();
285 mtspr(SPRN_DBAT3U, 0xf0001ffe);
286 mtspr(SPRN_DBAT3L, 0xfe80002a);
287 mb();
288
289}
290
291static unsigned long __init
292pcore_find_end_of_memory(void)
293{
294
295 return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
296}
297
298static void __init
299pcore_map_io(void)
300{
301 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
302}
303
304TODC_ALLOC();
305
306void __init
307platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
308 unsigned long r6, unsigned long r7)
309{
310 parse_bootinfo(find_bootinfo());
311
312 /* Cover I/O space with a BAT */
313 /* yuck, better hope your ram size is a power of 2 -- paulus */
314 pcore_set_bat();
315
316 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
317 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
318 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
319
320 ppc_md.setup_arch = pcore_setup_arch;
321 ppc_md.show_cpuinfo = pcore_show_cpuinfo;
322 ppc_md.init_IRQ = pcore_init_IRQ;
323 ppc_md.get_irq = i8259_irq;
324
325 ppc_md.find_end_of_memory = pcore_find_end_of_memory;
326 ppc_md.setup_io_mappings = pcore_map_io;
327
328 ppc_md.restart = pcore_restart;
329 ppc_md.power_off = pcore_power_off;
330 ppc_md.halt = pcore_halt;
331
332 TODC_INIT(TODC_TYPE_MK48T59,
333 PCORE_NVRAM_AS0,
334 PCORE_NVRAM_AS1,
335 PCORE_NVRAM_DATA,
336 8);
337
338 ppc_md.time_init = todc_time_init;
339 ppc_md.get_rtc_time = todc_get_rtc_time;
340 ppc_md.set_rtc_time = todc_set_rtc_time;
341 ppc_md.calibrate_decr = todc_calibrate_decr;
342
343 ppc_md.nvram_read_val = todc_m48txx_read_val;
344 ppc_md.nvram_write_val = todc_m48txx_write_val;
345
346#ifdef CONFIG_SERIAL_TEXT_DEBUG
347 ppc_md.progress = gen550_progress;
348#endif
349#ifdef CONFIG_KGDB
350 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
351#endif
352}
diff --git a/arch/ppc/platforms/pcore.h b/arch/ppc/platforms/pcore.h
deleted file mode 100644
index c6a26e764926..000000000000
--- a/arch/ppc/platforms/pcore.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * arch/ppc/platforms/pcore.h
3 *
4 * Definitions for Force PowerCore board support
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifndef __PPC_PLATFORMS_PCORE_H
15#define __PPC_PLATFORMS_PCORE_H
16
17#include <asm/mpc10x.h>
18
19#define PCORE_TYPE_6750 1
20#define PCORE_TYPE_680 2
21
22#define PCORE_NVRAM_AS0 0x73
23#define PCORE_NVRAM_AS1 0x75
24#define PCORE_NVRAM_DATA 0x77
25
26#define PCORE_DCCR_REG (MPC10X_MAPB_ISA_IO_BASE + 0x308)
27#define PCORE_DCCR_L2_MASK 0xc0
28#define PCORE_DCCR_L2_0KB 0x00
29#define PCORE_DCCR_L2_256KB 0x40
30#define PCORE_DCCR_L2_512KB 0xc0
31#define PCORE_DCCR_L2_1MB 0x80
32#define PCORE_DCCR_L2_2MB 0x00
33
34#define PCORE_WINBOND_IDE_INT 0x43
35#define PCORE_WINBOND_PCI_INT 0x44
36#define PCORE_WINBOND_PRI_EDG_LVL 0x4d0
37#define PCORE_WINBOND_SEC_EDG_LVL 0x4d1
38
39#endif /* __PPC_PLATFORMS_PCORE_H */
diff --git a/arch/ppc/platforms/pmac_pic.c b/arch/ppc/platforms/pmac_pic.c
index 9f92e1bb7f34..2ce058895e03 100644
--- a/arch/ppc/platforms/pmac_pic.c
+++ b/arch/ppc/platforms/pmac_pic.c
@@ -619,7 +619,7 @@ not_found:
619 return viaint; 619 return viaint;
620} 620}
621 621
622static int pmacpic_suspend(struct sys_device *sysdev, u32 state) 622static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
623{ 623{
624 int viaint = pmacpic_find_viaint(); 624 int viaint = pmacpic_find_viaint();
625 625
diff --git a/arch/ppc/platforms/spd8xx.h b/arch/ppc/platforms/spd8xx.h
deleted file mode 100644
index ed48d144f415..000000000000
--- a/arch/ppc/platforms/spd8xx.h
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Speech Design SPD8xxTS board specific definitions
3 *
4 * Copyright (c) 2000,2001 Wolfgang Denk (wd@denx.de)
5 */
6
7#ifdef __KERNEL__
8#ifndef __ASM_SPD8XX_H__
9#define __ASM_SPD8XX_H__
10
11#include <linux/config.h>
12
13#include <asm/ppcboot.h>
14
15#ifndef __ASSEMBLY__
16#define SPD_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */
17#define SPD_IMAP_SIZE (64 * 1024) /* size of mapped area */
18
19#define IMAP_ADDR SPD_IMMR_BASE /* physical base address of IMMR area */
20#define IMAP_SIZE SPD_IMAP_SIZE /* mapped size of IMMR area */
21
22#define PCMCIA_MEM_ADDR ((uint)0xFE100000)
23#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
24
25#define IDE0_INTERRUPT 10 /* = IRQ5 */
26#define IDE1_INTERRUPT 12 /* = IRQ6 */
27#define CPM_INTERRUPT 13 /* = SIU_LEVEL6 (was: SIU_LEVEL2) */
28
29/* override the default number of IDE hardware interfaces */
30#define MAX_HWIFS 2
31
32/*
33 * Definitions for IDE0 Interface
34 */
35#define IDE0_BASE_OFFSET 0x0000 /* Offset in PCMCIA memory */
36#define IDE0_DATA_REG_OFFSET 0x0000
37#define IDE0_ERROR_REG_OFFSET 0x0081
38#define IDE0_NSECTOR_REG_OFFSET 0x0082
39#define IDE0_SECTOR_REG_OFFSET 0x0083
40#define IDE0_LCYL_REG_OFFSET 0x0084
41#define IDE0_HCYL_REG_OFFSET 0x0085
42#define IDE0_SELECT_REG_OFFSET 0x0086
43#define IDE0_STATUS_REG_OFFSET 0x0087
44#define IDE0_CONTROL_REG_OFFSET 0x0106
45#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */
46
47/*
48 * Definitions for IDE1 Interface
49 */
50#define IDE1_BASE_OFFSET 0x0C00 /* Offset in PCMCIA memory */
51#define IDE1_DATA_REG_OFFSET 0x0000
52#define IDE1_ERROR_REG_OFFSET 0x0081
53#define IDE1_NSECTOR_REG_OFFSET 0x0082
54#define IDE1_SECTOR_REG_OFFSET 0x0083
55#define IDE1_LCYL_REG_OFFSET 0x0084
56#define IDE1_HCYL_REG_OFFSET 0x0085
57#define IDE1_SELECT_REG_OFFSET 0x0086
58#define IDE1_STATUS_REG_OFFSET 0x0087
59#define IDE1_CONTROL_REG_OFFSET 0x0106
60#define IDE1_IRQ_REG_OFFSET 0x000A /* not used */
61
62/* CPM Ethernet through SCCx.
63 *
64 * Bits in parallel I/O port registers that have to be set/cleared
65 * to configure the pins for SCC2 use.
66 */
67#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
68#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
69#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
70#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
71#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
72#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
73
74#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
75
76#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
77#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
78#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
79
80/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
81 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
82 */
83#define SICR_ENET_MASK ((uint)0x0000ff00)
84#define SICR_ENET_CLKRT ((uint)0x00002E00)
85
86/* We don't use the 8259.
87*/
88#define NR_8259_INTS 0
89
90#endif /* !__ASSEMBLY__ */
91#endif /* __ASM_SPD8XX_H__ */
92#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/tqm8xx.h b/arch/ppc/platforms/tqm8xx.h
index 2150dc87b18f..43ac064ebe5a 100644
--- a/arch/ppc/platforms/tqm8xx.h
+++ b/arch/ppc/platforms/tqm8xx.h
@@ -147,29 +147,6 @@ static __inline__ void ide_led(int on)
147#define SICR_ENET_CLKRT ((uint)0x00002600) 147#define SICR_ENET_CLKRT ((uint)0x00002600)
148#endif /* CONFIG_FPS850L */ 148#endif /* CONFIG_FPS850L */
149 149
150/*** SM850 *********************************************************/
151
152/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
153
154#ifdef CONFIG_SM850
155#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
156#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
157#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
158#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
159
160#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
161#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
162
163#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
164#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
165
166/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
167 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
168 */
169#define SICR_ENET_MASK ((uint)0x00FF0000)
170#define SICR_ENET_CLKRT ((uint)0x00260000)
171#endif /* CONFIG_SM850 */
172
173/* We don't use the 8259. 150/* We don't use the 8259.
174*/ 151*/
175#define NR_8259_INTS 0 152#define NR_8259_INTS 0
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 04:27:47 -0500