[PATCH] ppc32: Added PCI support MPC83xx

Adds support for the two PCI busses on MPC83xx and the MPC834x SYS/PIBS
reference board.

The code initializes PCI inbound/outbound windows, allocates and registers
PCI memory/io space.  Be aware that setup of the PCI buses on the PIBs
board is expected to be done by the firmware.

Signed-off-by: Tony Li <tony.li@freescale.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

2 files changed, 52 insertions, 23 deletions

diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c
index ddd04d4c1ea9..b38a851a64ec 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.c
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.c
@@ -62,9 +62,29 @@ extern unsigned long total_memory;	/* in mm/init */
 unsigned char __res[sizeof (bd_t)];
 
 #ifdef CONFIG_PCI
-#error "PCI is not supported"
-/* NEED mpc83xx_map_irq & mpc83xx_exclude_device
-   see platforms/85xx/mpc85xx_ads_common.c */
+int
+mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+        static char pci_irq_table[][4] =
+            /*
+             *      PCI IDSEL/INTPIN->INTLINE
+             *       A      B      C      D
+             */
+        {
+                {PIRQA, PIRQB,  PIRQC,  PIRQD}, /* idsel 0x11 */
+                {PIRQC, PIRQD,  PIRQA,  PIRQB}, /* idsel 0x12 */
+                {PIRQD, PIRQA,  PIRQB,  PIRQC}  /* idsel 0x13 */
+        };
+
+        const long min_idsel = 0x11, max_idsel = 0x13, irqs_per_slot = 4;
+        return PCI_IRQ_TABLE_LOOKUP;
+}
+
+int
+mpc83xx_exclude_device(u_char bus, u_char devfn)
+{
+        return PCIBIOS_SUCCESSFUL;
+}
 #endif /* CONFIG_PCI */
 
 /* ************************************************************************
@@ -88,7 +108,7 @@ mpc834x_sys_setup_arch(void)
 
 #ifdef CONFIG_PCI
         /* setup PCI host bridges */
-        mpc83xx_sys_setup_hose();
+        mpc83xx_setup_hose();
 #endif
         mpc83xx_early_serial_map();
 
@@ -175,10 +195,17 @@ mpc834x_sys_init_IRQ(void)
                 IRQ_SENSE_LEVEL,        /* EXT 1 */
                 IRQ_SENSE_LEVEL,        /* EXT 2 */
                 0,                      /* EXT 3 */
+#ifdef CONFIG_PCI
+                IRQ_SENSE_LEVEL,        /* EXT 4 */
+                IRQ_SENSE_LEVEL,        /* EXT 5 */
+                IRQ_SENSE_LEVEL,        /* EXT 6 */
+                IRQ_SENSE_LEVEL,        /* EXT 7 */
+#else
                 0,                      /* EXT 4 */
                 0,                      /* EXT 5 */
                 0,                      /* EXT 6 */
                 0,                      /* EXT 7 */
+#endif
         };
 
         ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8);
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h
index a2f6e49d7151..1584cd77a9ef 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.h
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.h
@@ -26,7 +26,7 @@
 #define VIRT_IMMRBAR            ((uint)0xfe000000)
 
 #define BCSR_PHYS_ADDR          ((uint)0xf8000000)
-#define BCSR_SIZE               ((uint)(32 * 1024))
+#define BCSR_SIZE               ((uint)(128 * 1024))
 
 #define BCSR_MISC_REG2_OFF      0x07
 #define BCSR_MISC_REG2_PORESET  0x01
@@ -34,23 +34,25 @@
 #define BCSR_MISC_REG3_OFF      0x08
 #define BCSR_MISC_REG3_CNFLOCK  0x80
 
-#ifdef CONFIG_PCI
-/* PCI interrupt controller */
-#define PIRQA        MPC83xx_IRQ_IRQ4
-#define PIRQB        MPC83xx_IRQ_IRQ5
-#define PIRQC        MPC83xx_IRQ_IRQ6
-#define PIRQD        MPC83xx_IRQ_IRQ7
-
-#define MPC834x_SYS_PCI1_LOWER_IO        0x00000000
-#define MPC834x_SYS_PCI1_UPPER_IO        0x00ffffff
-
-#define MPC834x_SYS_PCI1_LOWER_MEM       0x80000000
-#define MPC834x_SYS_PCI1_UPPER_MEM       0x9fffffff
-
-#define MPC834x_SYS_PCI1_IO_BASE         0xe2000000
-#define MPC834x_SYS_PCI1_MEM_OFFSET      0x00000000
-
-#define MPC834x_SYS_PCI1_IO_SIZE         0x01000000
-#endif /* CONFIG_PCI */
+#define PIRQA   MPC83xx_IRQ_EXT4
+#define PIRQB   MPC83xx_IRQ_EXT5
+#define PIRQC   MPC83xx_IRQ_EXT6
+#define PIRQD   MPC83xx_IRQ_EXT7
+
+#define MPC83xx_PCI1_LOWER_IO   0x00000000
+#define MPC83xx_PCI1_UPPER_IO   0x00ffffff
+#define MPC83xx_PCI1_LOWER_MEM  0x80000000
+#define MPC83xx_PCI1_UPPER_MEM  0x9fffffff
+#define MPC83xx_PCI1_IO_BASE    0xe2000000
+#define MPC83xx_PCI1_MEM_OFFSET 0x00000000
+#define MPC83xx_PCI1_IO_SIZE    0x01000000
+
+#define MPC83xx_PCI2_LOWER_IO   0x00000000
+#define MPC83xx_PCI2_UPPER_IO   0x00ffffff
+#define MPC83xx_PCI2_LOWER_MEM  0xa0000000
+#define MPC83xx_PCI2_UPPER_MEM  0xbfffffff
+#define MPC83xx_PCI2_IO_BASE    0xe3000000
+#define MPC83xx_PCI2_MEM_OFFSET 0x00000000
+#define MPC83xx_PCI2_IO_SIZE    0x01000000
 
 #endif                /* __MACH_MPC83XX_SYS_H__ */