diff options
author | Chris Elston <chris.elston@radstone.co.uk> | 2005-05-01 11:58:40 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-05-01 11:58:40 -0400 |
commit | 630710e3f72b6a324a525f6e5db3f7985d0fc4a2 (patch) | |
tree | 9088f17473108acb611b80b03f417e0591e1313d /arch/ppc/platforms/radstone_ppc7d.c | |
parent | 443a848cd30eb5bb5c1038e6371d83404775dcfc (diff) |
[PATCH] ppc32: fix for misreported SDRAM size on Radstone PPC7D platform
This patch fixes the SDRAM output from /proc/cpuinfo. The previous code
assumed that there was only one bank of SDRAM, and that the size in the memory
configuration register was the total size.
Signed-off-by: Chris Elston <chris.elston@radstone.co.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/platforms/radstone_ppc7d.c')
-rw-r--r-- | arch/ppc/platforms/radstone_ppc7d.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c index 2a99b43737a8..df2ea051380a 100644 --- a/arch/ppc/platforms/radstone_ppc7d.c +++ b/arch/ppc/platforms/radstone_ppc7d.c | |||
@@ -253,6 +253,8 @@ static int ppc7d_show_cpuinfo(struct seq_file *m) | |||
253 | u8 val1, val2; | 253 | u8 val1, val2; |
254 | static int flash_sizes[4] = { 64, 32, 0, 16 }; | 254 | static int flash_sizes[4] = { 64, 32, 0, 16 }; |
255 | static int flash_banks[4] = { 4, 3, 2, 1 }; | 255 | static int flash_banks[4] = { 4, 3, 2, 1 }; |
256 | static int sdram_bank_sizes[4] = { 128, 256, 512, 1 }; | ||
257 | int sdram_num_banks = 2; | ||
256 | static char *pci_modes[] = { "PCI33", "PCI66", | 258 | static char *pci_modes[] = { "PCI33", "PCI66", |
257 | "Unknown", "Unknown", | 259 | "Unknown", "Unknown", |
258 | "PCIX33", "PCIX66", | 260 | "PCIX33", "PCIX66", |
@@ -279,13 +281,17 @@ static int ppc7d_show_cpuinfo(struct seq_file *m) | |||
279 | (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 : | 281 | (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 : |
280 | (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0); | 282 | (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0); |
281 | 283 | ||
284 | val = inb(PPC7D_CPLD_MEM_CONFIG); | ||
285 | if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--; | ||
286 | |||
282 | val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND); | 287 | val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND); |
283 | val1 = val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK; | 288 | val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6; |
284 | seq_printf(m, "SDRAM\t\t: %d%c", | 289 | seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c", |
285 | (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_128M) ? 128 : | 290 | sdram_num_banks, |
286 | (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_256M) ? 256 : | 291 | sdram_bank_sizes[val1], |
287 | (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_512M) ? 512 : 1, | 292 | (sdram_bank_sizes[val1] < 128) ? 'G' : 'M', |
288 | (val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_1G) ? 'G' : 'M'); | 293 | sdram_num_banks * sdram_bank_sizes[val1], |
294 | (sdram_bank_sizes[val1] < 128) ? 'G' : 'M'); | ||
289 | if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) { | 295 | if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) { |
290 | seq_printf(m, " [ECC %sabled]", | 296 | seq_printf(m, " [ECC %sabled]", |
291 | (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" : | 297 | (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" : |