[PATCH] ppc32: Support for 82xx PQII on-chip PCI bridge

This patch adds on-chip PCI bridge support for the PQ2 family.  The
incomplete existent code is updated with interrupt handling stuff and
board-specific bits for 8272ADS and PQ2FADS; the related files were renamed
(from m8260_pci to m82xx_pci) to be of more generic fashion.  This is
tested with 8266ADS and 8272ADS, should work on PQ2FADS as well.

Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 18 insertions, 23 deletions

diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
index cf5e5dd06d63..067d9a5aebc1 100644
--- a/arch/ppc/platforms/pq2ads.h
+++ b/arch/ppc/platforms/pq2ads.h
@@ -49,10 +49,10 @@
 /* PCI interrupt controller */
 #define PCI_INT_STAT_REG        0xF8200000
 #define PCI_INT_MASK_REG        0xF8200004
-#define PIRQA                   (NR_SIU_INTS + 0)
-#define PIRQB                   (NR_SIU_INTS + 1)
-#define PIRQC                   (NR_SIU_INTS + 2)
-#define PIRQD                   (NR_SIU_INTS + 3)
+#define PIRQA                   (NR_CPM_INTS + 0)
+#define PIRQB                   (NR_CPM_INTS + 1)
+#define PIRQC                   (NR_CPM_INTS + 2)
+#define PIRQD                   (NR_CPM_INTS + 3)
 
 /*
  * PCI memory map definitions for MPC8266ADS-PCI.
@@ -68,28 +68,23 @@
  *      0x00000000-0x1FFFFFFF   0x00000000-0x1FFFFFFF   MPC8266 local memory
  */
 
-/* window for a PCI master to access MPC8266 memory */
-#define PCI_SLV_MEM_LOCAL       0x00000000      /* Local base */
-#define PCI_SLV_MEM_BUS         0x00000000      /* PCI base */
+/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
+   Here we should redefine what is unique for this board */
+#define M82xx_PCI_SLAVE_MEM_LOCAL       0x00000000      /* Local base */
+#define M82xx_PCI_SLAVE_MEM_BUS         0x00000000      /* PCI base */
+#define M82xx_PCI_SLAVE_MEM_SIZE        0x10000000      /* 256 Mb */
 
-/* window for the processor to access PCI memory with prefetching */
-#define PCI_MSTR_MEM_LOCAL      0x80000000      /* Local base */
-#define PCI_MSTR_MEM_BUS        0x80000000      /* PCI base   */
-#define PCI_MSTR_MEM_SIZE       0x20000000      /* 512MB */
+#define M82xx_PCI_SLAVE_SEC_WND_SIZE    ~(0x40000000 - 1U)      /* 2 x 512Mb  */
+#define M82xx_PCI_SLAVE_SEC_WND_BASE    0x80000000              /* PCI Memory base */
 
-/* window for the processor to access PCI memory without prefetching */
-#define PCI_MSTR_MEMIO_LOCAL    0xA0000000      /* Local base */
-#define PCI_MSTR_MEMIO_BUS      0xA0000000      /* PCI base   */
-#define PCI_MSTR_MEMIO_SIZE     0x20000000      /* 512MB */
+#if defined(CONFIG_ADS8272)
+#define PCI_INT_TO_SIU  SIU_INT_IRQ2
+#elif defined(CONFIG_PQ2FADS)
+#define PCI_INT_TO_SIU  SIU_INT_IRQ6
+#else
+#warning PCI Bridge will be without interrupts support
+#endif
 
-/* window for the processor to access PCI I/O */
-#define PCI_MSTR_IO_LOCAL       0xF4000000      /* Local base */
-#define PCI_MSTR_IO_BUS         0x00000000      /* PCI base   */
-#define PCI_MSTR_IO_SIZE        0x04000000      /* 64MB */
-
-#define _IO_BASE                PCI_MSTR_IO_LOCAL
-#define _ISA_MEM_BASE           PCI_MSTR_MEMIO_LOCAL
-#define PCI_DRAM_OFFSET         PCI_SLV_MEM_BUS
 #endif /* CONFIG_PCI */
 
 #endif /* __MACH_ADS8260_DEFS */