aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ppc/platforms/85xx
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/ppc/platforms/85xx
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/ppc/platforms/85xx')
-rw-r--r--arch/ppc/platforms/85xx/Kconfig76
-rw-r--r--arch/ppc/platforms/85xx/Makefile8
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.c218
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.h25
-rw-r--r--arch/ppc/platforms/85xx/mpc8555_cds.h26
-rw-r--r--arch/ppc/platforms/85xx/mpc8560_ads.c210
-rw-r--r--arch/ppc/platforms/85xx/mpc8560_ads.h27
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_ads_common.c225
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_ads_common.h50
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.c467
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.h80
-rw-r--r--arch/ppc/platforms/85xx/sbc8560.c227
-rw-r--r--arch/ppc/platforms/85xx/sbc8560.h49
-rw-r--r--arch/ppc/platforms/85xx/sbc85xx.c203
-rw-r--r--arch/ppc/platforms/85xx/sbc85xx.h55
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.c355
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.h74
17 files changed, 2375 insertions, 0 deletions
diff --git a/arch/ppc/platforms/85xx/Kconfig b/arch/ppc/platforms/85xx/Kconfig
new file mode 100644
index 000000000000..ff92e38e7da1
--- /dev/null
+++ b/arch/ppc/platforms/85xx/Kconfig
@@ -0,0 +1,76 @@
1config 85xx
2 bool
3 depends on E500
4 default y
5
6config PPC_INDIRECT_PCI_BE
7 bool
8 depends on 85xx
9 default y
10
11menu "Freescale 85xx options"
12 depends on E500
13
14choice
15 prompt "Machine Type"
16 depends on 85xx
17 default MPC8540_ADS
18
19config MPC8540_ADS
20 bool "Freescale MPC8540 ADS"
21 help
22 This option enables support for the MPC 8540 ADS evaluation board.
23
24config MPC8555_CDS
25 bool "Freescale MPC8555 CDS"
26 help
27 This option enablese support for the MPC8555 CDS evaluation board.
28
29config MPC8560_ADS
30 bool "Freescale MPC8560 ADS"
31 help
32 This option enables support for the MPC 8560 ADS evaluation board.
33
34config SBC8560
35 bool "WindRiver PowerQUICC III SBC8560"
36 help
37 This option enables support for the WindRiver PowerQUICC III
38 SBC8560 board.
39
40config STX_GP3
41 bool "Silicon Turnkey Express GP3"
42 help
43 This option enables support for the Silicon Turnkey Express GP3
44 board.
45
46endchoice
47
48# It's often necessary to know the specific 85xx processor type.
49# Fortunately, it is implied (so far) from the board type, so we
50# don't need to ask more redundant questions.
51config MPC8540
52 bool
53 depends on MPC8540_ADS
54 default y
55
56config MPC8555
57 bool
58 depends on MPC8555_CDS
59 default y
60
61config MPC8560
62 bool
63 depends on SBC8560 || MPC8560_ADS || STX_GP3
64 default y
65
66config 85xx_PCI2
67 bool "Supprt for 2nd PCI host controller"
68 depends on MPC8555_CDS
69 default y
70
71config PPC_GEN550
72 bool
73 depends on MPC8540 || SBC8560 || MPC8555
74 default y
75
76endmenu
diff --git a/arch/ppc/platforms/85xx/Makefile b/arch/ppc/platforms/85xx/Makefile
new file mode 100644
index 000000000000..854fbd298ba2
--- /dev/null
+++ b/arch/ppc/platforms/85xx/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the PowerPC 85xx linux kernel.
3#
4obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads_common.o mpc8540_ads.o
5obj-$(CONFIG_MPC8555_CDS) += mpc85xx_cds_common.o
6obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads_common.o mpc8560_ads.o
7obj-$(CONFIG_SBC8560) += sbc85xx.o sbc8560.o
8obj-$(CONFIG_STX_GP3) += stx_gp3.o
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c
new file mode 100644
index 000000000000..4d857d6d633d
--- /dev/null
+++ b/arch/ppc/platforms/85xx/mpc8540_ads.c
@@ -0,0 +1,218 @@
1/*
2 * arch/ppc/platforms/85xx/mpc8540_ads.c
3 *
4 * MPC8540ADS board specific routines
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/config.h>
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/major.h>
25#include <linux/console.h>
26#include <linux/delay.h>
27#include <linux/irq.h>
28#include <linux/seq_file.h>
29#include <linux/root_dev.h>
30#include <linux/serial.h>
31#include <linux/tty.h> /* for linux/serial_core.h */
32#include <linux/serial_core.h>
33#include <linux/initrd.h>
34#include <linux/module.h>
35#include <linux/fsl_devices.h>
36
37#include <asm/system.h>
38#include <asm/pgtable.h>
39#include <asm/page.h>
40#include <asm/atomic.h>
41#include <asm/time.h>
42#include <asm/io.h>
43#include <asm/machdep.h>
44#include <asm/prom.h>
45#include <asm/open_pic.h>
46#include <asm/bootinfo.h>
47#include <asm/pci-bridge.h>
48#include <asm/mpc85xx.h>
49#include <asm/irq.h>
50#include <asm/immap_85xx.h>
51#include <asm/kgdb.h>
52#include <asm/ppc_sys.h>
53#include <mm/mmu_decl.h>
54
55#include <syslib/ppc85xx_setup.h>
56
57/* ************************************************************************
58 *
59 * Setup the architecture
60 *
61 */
62static void __init
63mpc8540ads_setup_arch(void)
64{
65 bd_t *binfo = (bd_t *) __res;
66 unsigned int freq;
67 struct gianfar_platform_data *pdata;
68
69 /* get the core frequency */
70 freq = binfo->bi_intfreq;
71
72 if (ppc_md.progress)
73 ppc_md.progress("mpc8540ads_setup_arch()", 0);
74
75 /* Set loops_per_jiffy to a half-way reasonable value,
76 for use until calibrate_delay gets called. */
77 loops_per_jiffy = freq / HZ;
78
79#ifdef CONFIG_PCI
80 /* setup PCI host bridges */
81 mpc85xx_setup_hose();
82#endif
83
84#ifdef CONFIG_SERIAL_8250
85 mpc85xx_early_serial_map();
86#endif
87
88#ifdef CONFIG_SERIAL_TEXT_DEBUG
89 /* Invalidate the entry we stole earlier the serial ports
90 * should be properly mapped */
91 invalidate_tlbcam_entry(NUM_TLBCAMS - 1);
92#endif
93
94 /* setup the board related information for the enet controllers */
95 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
96 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
97 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
98 pdata->phyid = 0;
99 /* fixup phy address */
100 pdata->phy_reg_addr += binfo->bi_immr_base;
101 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
102
103 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
104 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
105 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
106 pdata->phyid = 1;
107 /* fixup phy address */
108 pdata->phy_reg_addr += binfo->bi_immr_base;
109 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
110
111 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);
112 pdata->board_flags = 0;
113 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
114 pdata->phyid = 3;
115 /* fixup phy address */
116 pdata->phy_reg_addr += binfo->bi_immr_base;
117 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);
118
119#ifdef CONFIG_BLK_DEV_INITRD
120 if (initrd_start)
121 ROOT_DEV = Root_RAM0;
122 else
123#endif
124#ifdef CONFIG_ROOT_NFS
125 ROOT_DEV = Root_NFS;
126#else
127 ROOT_DEV = Root_HDA1;
128#endif
129}
130
131/* ************************************************************************ */
132void __init
133platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
134 unsigned long r6, unsigned long r7)
135{
136 /* parse_bootinfo must always be called first */
137 parse_bootinfo(find_bootinfo());
138
139 /*
140 * If we were passed in a board information, copy it into the
141 * residual data area.
142 */
143 if (r3) {
144 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
145 sizeof (bd_t));
146 }
147#ifdef CONFIG_SERIAL_TEXT_DEBUG
148 {
149 bd_t *binfo = (bd_t *) __res;
150 struct uart_port p;
151
152 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
153 settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base,
154 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
155
156 memset(&p, 0, sizeof (p));
157 p.iotype = SERIAL_IO_MEM;
158 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
159 p.uartclk = binfo->bi_busfreq;
160
161 gen550_init(0, &p);
162
163 memset(&p, 0, sizeof (p));
164 p.iotype = SERIAL_IO_MEM;
165 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
166 p.uartclk = binfo->bi_busfreq;
167
168 gen550_init(1, &p);
169 }
170#endif
171
172#if defined(CONFIG_BLK_DEV_INITRD)
173 /*
174 * If the init RAM disk has been configured in, and there's a valid
175 * starting address for it, set it up.
176 */
177 if (r4) {
178 initrd_start = r4 + KERNELBASE;
179 initrd_end = r5 + KERNELBASE;
180 }
181#endif /* CONFIG_BLK_DEV_INITRD */
182
183 /* Copy the kernel command line arguments to a safe place. */
184
185 if (r6) {
186 *(char *) (r7 + KERNELBASE) = 0;
187 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
188 }
189
190 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
191
192 /* setup the PowerPC module struct */
193 ppc_md.setup_arch = mpc8540ads_setup_arch;
194 ppc_md.show_cpuinfo = mpc85xx_ads_show_cpuinfo;
195
196 ppc_md.init_IRQ = mpc85xx_ads_init_IRQ;
197 ppc_md.get_irq = openpic_get_irq;
198
199 ppc_md.restart = mpc85xx_restart;
200 ppc_md.power_off = mpc85xx_power_off;
201 ppc_md.halt = mpc85xx_halt;
202
203 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
204
205 ppc_md.time_init = NULL;
206 ppc_md.set_rtc_time = NULL;
207 ppc_md.get_rtc_time = NULL;
208 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
209
210#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
211 ppc_md.progress = gen550_progress;
212#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
213
214 if (ppc_md.progress)
215 ppc_md.progress("mpc8540ads_init(): exit", 0);
216
217 return;
218}
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.h b/arch/ppc/platforms/85xx/mpc8540_ads.h
new file mode 100644
index 000000000000..3d05d7c4a938
--- /dev/null
+++ b/arch/ppc/platforms/85xx/mpc8540_ads.h
@@ -0,0 +1,25 @@
1/*
2 * arch/ppc/platforms/85xx/mpc8540_ads.h
3 *
4 * MPC8540ADS board definitions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifndef __MACH_MPC8540ADS_H__
18#define __MACH_MPC8540ADS_H__
19
20#include <linux/config.h>
21#include <linux/initrd.h>
22#include <syslib/ppc85xx_setup.h>
23#include <platforms/85xx/mpc85xx_ads_common.h>
24
25#endif /* __MACH_MPC8540ADS_H__ */
diff --git a/arch/ppc/platforms/85xx/mpc8555_cds.h b/arch/ppc/platforms/85xx/mpc8555_cds.h
new file mode 100644
index 000000000000..e0e75568bc57
--- /dev/null
+++ b/arch/ppc/platforms/85xx/mpc8555_cds.h
@@ -0,0 +1,26 @@
1/*
2 * arch/ppc/platforms/mpc8555_cds.h
3 *
4 * MPC8555CDS board definitions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifndef __MACH_MPC8555CDS_H__
18#define __MACH_MPC8555CDS_H__
19
20#include <linux/config.h>
21#include <syslib/ppc85xx_setup.h>
22#include <platforms/85xx/mpc85xx_cds_common.h>
23
24#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
25
26#endif /* __MACH_MPC8555CDS_H__ */
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c
new file mode 100644
index 000000000000..761b8c7b25d2
--- /dev/null
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -0,0 +1,210 @@
1/*
2 * arch/ppc/platforms/85xx/mpc8560_ads.c
3 *
4 * MPC8560ADS board specific routines
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/config.h>
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/major.h>
25#include <linux/console.h>
26#include <linux/delay.h>
27#include <linux/irq.h>
28#include <linux/seq_file.h>
29#include <linux/root_dev.h>
30#include <linux/serial.h>
31#include <linux/tty.h> /* for linux/serial_core.h */
32#include <linux/serial_core.h>
33#include <linux/initrd.h>
34#include <linux/module.h>
35#include <linux/fsl_devices.h>
36
37#include <asm/system.h>
38#include <asm/pgtable.h>
39#include <asm/page.h>
40#include <asm/atomic.h>
41#include <asm/time.h>
42#include <asm/io.h>
43#include <asm/machdep.h>
44#include <asm/prom.h>
45#include <asm/open_pic.h>
46#include <asm/bootinfo.h>
47#include <asm/pci-bridge.h>
48#include <asm/mpc85xx.h>
49#include <asm/irq.h>
50#include <asm/immap_85xx.h>
51#include <asm/kgdb.h>
52#include <asm/ppc_sys.h>
53#include <asm/cpm2.h>
54#include <mm/mmu_decl.h>
55
56#include <syslib/cpm2_pic.h>
57#include <syslib/ppc85xx_common.h>
58#include <syslib/ppc85xx_setup.h>
59
60extern void cpm2_reset(void);
61
62/* ************************************************************************
63 *
64 * Setup the architecture
65 *
66 */
67
68static void __init
69mpc8560ads_setup_arch(void)
70{
71 bd_t *binfo = (bd_t *) __res;
72 unsigned int freq;
73 struct gianfar_platform_data *pdata;
74
75 cpm2_reset();
76
77 /* get the core frequency */
78 freq = binfo->bi_intfreq;
79
80 if (ppc_md.progress)
81 ppc_md.progress("mpc8560ads_setup_arch()", 0);
82
83 /* Set loops_per_jiffy to a half-way reasonable value,
84 for use until calibrate_delay gets called. */
85 loops_per_jiffy = freq / HZ;
86
87#ifdef CONFIG_PCI
88 /* setup PCI host bridges */
89 mpc85xx_setup_hose();
90#endif
91
92 /* setup the board related information for the enet controllers */
93 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
94 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
95 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
96 pdata->phyid = 0;
97 /* fixup phy address */
98 pdata->phy_reg_addr += binfo->bi_immr_base;
99 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
100
101 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
102 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
103 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
104 pdata->phyid = 1;
105 /* fixup phy address */
106 pdata->phy_reg_addr += binfo->bi_immr_base;
107 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
108
109#ifdef CONFIG_BLK_DEV_INITRD
110 if (initrd_start)
111 ROOT_DEV = Root_RAM0;
112 else
113#endif
114#ifdef CONFIG_ROOT_NFS
115 ROOT_DEV = Root_NFS;
116#else
117 ROOT_DEV = Root_HDA1;
118#endif
119}
120
121static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
122{
123 while ((irq = cpm2_get_irq(regs)) >= 0)
124 __do_IRQ(irq, regs);
125 return IRQ_HANDLED;
126}
127
128static struct irqaction cpm2_irqaction = {
129 .handler = cpm2_cascade,
130 .flags = SA_INTERRUPT,
131 .mask = CPU_MASK_NONE,
132 .name = "cpm2_cascade",
133};
134
135static void __init
136mpc8560_ads_init_IRQ(void)
137{
138 /* Setup OpenPIC */
139 mpc85xx_ads_init_IRQ();
140
141 /* Setup CPM2 PIC */
142 cpm2_init_IRQ();
143
144 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
145
146 return;
147}
148
149
150
151/* ************************************************************************ */
152void __init
153platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
154 unsigned long r6, unsigned long r7)
155{
156 /* parse_bootinfo must always be called first */
157 parse_bootinfo(find_bootinfo());
158
159 /*
160 * If we were passed in a board information, copy it into the
161 * residual data area.
162 */
163 if (r3) {
164 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
165 sizeof (bd_t));
166
167 }
168#if defined(CONFIG_BLK_DEV_INITRD)
169 /*
170 * If the init RAM disk has been configured in, and there's a valid
171 * starting address for it, set it up.
172 */
173 if (r4) {
174 initrd_start = r4 + KERNELBASE;
175 initrd_end = r5 + KERNELBASE;
176 }
177#endif /* CONFIG_BLK_DEV_INITRD */
178
179 /* Copy the kernel command line arguments to a safe place. */
180
181 if (r6) {
182 *(char *) (r7 + KERNELBASE) = 0;
183 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
184 }
185
186 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
187
188 /* setup the PowerPC module struct */
189 ppc_md.setup_arch = mpc8560ads_setup_arch;
190 ppc_md.show_cpuinfo = mpc85xx_ads_show_cpuinfo;
191
192 ppc_md.init_IRQ = mpc8560_ads_init_IRQ;
193 ppc_md.get_irq = openpic_get_irq;
194
195 ppc_md.restart = mpc85xx_restart;
196 ppc_md.power_off = mpc85xx_power_off;
197 ppc_md.halt = mpc85xx_halt;
198
199 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
200
201 ppc_md.time_init = NULL;
202 ppc_md.set_rtc_time = NULL;
203 ppc_md.get_rtc_time = NULL;
204 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
205
206 if (ppc_md.progress)
207 ppc_md.progress("mpc8560ads_init(): exit", 0);
208
209 return;
210}
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.h b/arch/ppc/platforms/85xx/mpc8560_ads.h
new file mode 100644
index 000000000000..7df885d73e9d
--- /dev/null
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.h
@@ -0,0 +1,27 @@
1/*
2 * arch/ppc/platforms/mpc8560_ads.h
3 *
4 * MPC8540ADS board definitions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifndef __MACH_MPC8560ADS_H
18#define __MACH_MPC8560ADS_H
19
20#include <linux/config.h>
21#include <syslib/ppc85xx_setup.h>
22#include <platforms/85xx/mpc85xx_ads_common.h>
23
24#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
25#define PHY_INTERRUPT MPC85xx_IRQ_EXT7
26
27#endif /* __MACH_MPC8560ADS_H */
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
new file mode 100644
index 000000000000..ba9f9f562c45
--- /dev/null
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
@@ -0,0 +1,225 @@
1/*
2 * arch/ppc/platforms/85xx/mpc85xx_ads_common.c
3 *
4 * MPC85xx ADS board common routines
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/config.h>
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/major.h>
25#include <linux/console.h>
26#include <linux/delay.h>
27#include <linux/irq.h>
28#include <linux/seq_file.h>
29#include <linux/serial.h>
30#include <linux/module.h>
31
32#include <asm/system.h>
33#include <asm/pgtable.h>
34#include <asm/page.h>
35#include <asm/atomic.h>
36#include <asm/time.h>
37#include <asm/io.h>
38#include <asm/machdep.h>
39#include <asm/prom.h>
40#include <asm/open_pic.h>
41#include <asm/bootinfo.h>
42#include <asm/pci-bridge.h>
43#include <asm/mpc85xx.h>
44#include <asm/irq.h>
45#include <asm/immap_85xx.h>
46#include <asm/ppc_sys.h>
47
48#include <mm/mmu_decl.h>
49
50#include <platforms/85xx/mpc85xx_ads_common.h>
51
52#ifndef CONFIG_PCI
53unsigned long isa_io_base = 0;
54unsigned long isa_mem_base = 0;
55#endif
56
57extern unsigned long total_memory; /* in mm/init */
58
59unsigned char __res[sizeof (bd_t)];
60
61/* Internal interrupts are all Level Sensitive, and Positive Polarity */
62
63static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
96 0x0, /* External 0: */
97#if defined(CONFIG_PCI)
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 1 */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 2 */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 3 */
102#else
103 0x0, /* External 1: */
104 0x0, /* External 2: */
105 0x0, /* External 3: */
106 0x0, /* External 4: */
107#endif
108 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
109 0x0, /* External 6: */
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
111 0x0, /* External 8: */
112 0x0, /* External 9: */
113 0x0, /* External 10: */
114 0x0, /* External 11: */
115};
116
117/* ************************************************************************ */
118int
119mpc85xx_ads_show_cpuinfo(struct seq_file *m)
120{
121 uint pvid, svid, phid1;
122 uint memsize = total_memory;
123 bd_t *binfo = (bd_t *) __res;
124 unsigned int freq;
125
126 /* get the core frequency */
127 freq = binfo->bi_intfreq;
128
129 pvid = mfspr(SPRN_PVR);
130 svid = mfspr(SPRN_SVR);
131
132 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
133 seq_printf(m, "Machine\t\t: mpc%sads\n", cur_ppc_sys_spec->ppc_sys_name);
134 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
135 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
136 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
137
138 /* Display cpu Pll setting */
139 phid1 = mfspr(SPRN_HID1);
140 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
141
142 /* Display the amount of memory */
143 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
144
145 return 0;
146}
147
148void __init
149mpc85xx_ads_init_IRQ(void)
150{
151 bd_t *binfo = (bd_t *) __res;
152 /* Determine the Physical Address of the OpenPIC regs */
153 phys_addr_t OpenPIC_PAddr =
154 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
155 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
156 OpenPIC_InitSenses = mpc85xx_ads_openpic_initsenses;
157 OpenPIC_NumInitSenses = sizeof (mpc85xx_ads_openpic_initsenses);
158
159 /* Skip reserved space and internal sources */
160 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
161 /* Map PIC IRQs 0-11 */
162 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
163
164 /* we let openpic interrupts starting from an offset, to
165 * leave space for cascading interrupts underneath.
166 */
167 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
168
169 return;
170}
171
172#ifdef CONFIG_PCI
173/*
174 * interrupt routing
175 */
176
177int
178mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
179{
180 static char pci_irq_table[][4] =
181 /*
182 * This is little evil, but works around the fact
183 * that revA boards have IDSEL starting at 18
184 * and others boards (older) start at 12
185 *
186 * PCI IDSEL/INTPIN->INTLINE
187 * A B C D
188 */
189 {
190 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 2 */
191 {PIRQD, PIRQA, PIRQB, PIRQC},
192 {PIRQC, PIRQD, PIRQA, PIRQB},
193 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 5 */
194 {0, 0, 0, 0}, /* -- */
195 {0, 0, 0, 0}, /* -- */
196 {0, 0, 0, 0}, /* -- */
197 {0, 0, 0, 0}, /* -- */
198 {0, 0, 0, 0}, /* -- */
199 {0, 0, 0, 0}, /* -- */
200 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 12 */
201 {PIRQD, PIRQA, PIRQB, PIRQC},
202 {PIRQC, PIRQD, PIRQA, PIRQB},
203 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 15 */
204 {0, 0, 0, 0}, /* -- */
205 {0, 0, 0, 0}, /* -- */
206 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 18 */
207 {PIRQD, PIRQA, PIRQB, PIRQC},
208 {PIRQC, PIRQD, PIRQA, PIRQB},
209 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 21 */
210 };
211
212 const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
213 return PCI_IRQ_TABLE_LOOKUP;
214}
215
216int
217mpc85xx_exclude_device(u_char bus, u_char devfn)
218{
219 if (bus == 0 && PCI_SLOT(devfn) == 0)
220 return PCIBIOS_DEVICE_NOT_FOUND;
221 else
222 return PCIBIOS_SUCCESSFUL;
223}
224
225#endif /* CONFIG_PCI */
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
new file mode 100644
index 000000000000..3875e839cff7
--- /dev/null
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
@@ -0,0 +1,50 @@
1/*
2 * arch/ppc/platforms/85xx/mpc85xx_ads_common.h
3 *
4 * MPC85XX ADS common board definitions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifndef __MACH_MPC85XX_ADS_H__
18#define __MACH_MPC85XX_ADS_H__
19
20#include <linux/config.h>
21#include <linux/init.h>
22#include <linux/seq_file.h>
23#include <asm/ppcboot.h>
24
25#define BOARD_CCSRBAR ((uint)0xe0000000)
26#define BCSR_ADDR ((uint)0xf8000000)
27#define BCSR_SIZE ((uint)(32 * 1024))
28
29extern int mpc85xx_ads_show_cpuinfo(struct seq_file *m);
30extern void mpc85xx_ads_init_IRQ(void) __init;
31extern void mpc85xx_ads_map_io(void) __init;
32
33/* PCI interrupt controller */
34#define PIRQA MPC85xx_IRQ_EXT1
35#define PIRQB MPC85xx_IRQ_EXT2
36#define PIRQC MPC85xx_IRQ_EXT3
37#define PIRQD MPC85xx_IRQ_EXT4
38
39#define MPC85XX_PCI1_LOWER_IO 0x00000000
40#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
41
42#define MPC85XX_PCI1_LOWER_MEM 0x80000000
43#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
44
45#define MPC85XX_PCI1_IO_BASE 0xe2000000
46#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
47
48#define MPC85XX_PCI1_IO_SIZE 0x01000000
49
50#endif /* __MACH_MPC85XX_ADS_H__ */
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
new file mode 100644
index 000000000000..6c020d67ad70
--- /dev/null
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -0,0 +1,467 @@
1/*
2 * arch/ppc/platform/85xx/mpc85xx_cds_common.c
3 *
4 * MPC85xx CDS board specific routines
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/config.h>
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/major.h>
25#include <linux/console.h>
26#include <linux/delay.h>
27#include <linux/irq.h>
28#include <linux/seq_file.h>
29#include <linux/serial.h>
30#include <linux/module.h>
31#include <linux/root_dev.h>
32#include <linux/initrd.h>
33#include <linux/tty.h>
34#include <linux/serial_core.h>
35#include <linux/fsl_devices.h>
36
37#include <asm/system.h>
38#include <asm/pgtable.h>
39#include <asm/page.h>
40#include <asm/atomic.h>
41#include <asm/time.h>
42#include <asm/todc.h>
43#include <asm/io.h>
44#include <asm/machdep.h>
45#include <asm/prom.h>
46#include <asm/open_pic.h>
47#include <asm/bootinfo.h>
48#include <asm/pci-bridge.h>
49#include <asm/mpc85xx.h>
50#include <asm/irq.h>
51#include <asm/immap_85xx.h>
52#include <asm/immap_cpm2.h>
53#include <asm/ppc_sys.h>
54#include <asm/kgdb.h>
55
56#include <mm/mmu_decl.h>
57#include <syslib/cpm2_pic.h>
58#include <syslib/ppc85xx_common.h>
59#include <syslib/ppc85xx_setup.h>
60
61
62#ifndef CONFIG_PCI
63unsigned long isa_io_base = 0;
64unsigned long isa_mem_base = 0;
65#endif
66
67extern unsigned long total_memory; /* in mm/init */
68
69unsigned char __res[sizeof (bd_t)];
70
71static int cds_pci_slot = 2;
72static volatile u8 * cadmus;
73
74/* Internal interrupts are all Level Sensitive, and Positive Polarity */
75
76static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
102 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
103 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
104 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
105 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
106 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
107 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
108 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
109#if defined(CONFIG_PCI)
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
111 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
112 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
113 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
114#else
115 0x0, /* External 0: */
116 0x0, /* External 1: */
117 0x0, /* External 2: */
118 0x0, /* External 3: */
119#endif
120 0x0, /* External 4: */
121 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
122 0x0, /* External 6: */
123 0x0, /* External 7: */
124 0x0, /* External 8: */
125 0x0, /* External 9: */
126 0x0, /* External 10: */
127#if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
128 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
129#else
130 0x0, /* External 11: */
131#endif
132};
133
134/* ************************************************************************ */
135int
136mpc85xx_cds_show_cpuinfo(struct seq_file *m)
137{
138 uint pvid, svid, phid1;
139 uint memsize = total_memory;
140 bd_t *binfo = (bd_t *) __res;
141 unsigned int freq;
142
143 /* get the core frequency */
144 freq = binfo->bi_intfreq;
145
146 pvid = mfspr(SPRN_PVR);
147 svid = mfspr(SPRN_SVR);
148
149 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
150 seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
151 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
152 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
153 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
154
155 /* Display cpu Pll setting */
156 phid1 = mfspr(SPRN_HID1);
157 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
158
159 /* Display the amount of memory */
160 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
161
162 return 0;
163}
164
165#ifdef CONFIG_CPM2
166static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
167{
168 while((irq = cpm2_get_irq(regs)) >= 0)
169 __do_IRQ(irq, regs);
170}
171
172static struct irqaction cpm2_irqaction = {
173 .handler = cpm2_cascade,
174 .flags = SA_INTERRUPT,
175 .mask = CPU_MASK_NONE,
176 .name = "cpm2_cascade",
177};
178#endif /* CONFIG_CPM2 */
179
180void __init
181mpc85xx_cds_init_IRQ(void)
182{
183 bd_t *binfo = (bd_t *) __res;
184
185 /* Determine the Physical Address of the OpenPIC regs */
186 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
187 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
188 OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
189 OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
190
191 /* Skip reserved space and internal sources */
192 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
193 /* Map PIC IRQs 0-11 */
194 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
195
196 /* we let openpic interrupts starting from an offset, to
197 * leave space for cascading interrupts underneath.
198 */
199 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
200
201#ifdef CONFIG_CPM2
202 /* Setup CPM2 PIC */
203 cpm2_init_IRQ();
204
205 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
206#endif
207
208 return;
209}
210
211#ifdef CONFIG_PCI
212/*
213 * interrupt routing
214 */
215int
216mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
217{
218 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
219
220 if (!hose->index)
221 {
222 /* Handle PCI1 interrupts */
223 char pci_irq_table[][4] =
224 /*
225 * PCI IDSEL/INTPIN->INTLINE
226 * A B C D
227 */
228
229 /* Note IRQ assignment for slots is based on which slot the elysium is
230 * in -- in this setup elysium is in slot #2 (this PIRQA as first
231 * interrupt on slot */
232 {
233 { 0, 1, 2, 3 }, /* 16 - PMC */
234 { 3, 0, 0, 0 }, /* 17 P2P (Tsi320) */
235 { 0, 1, 2, 3 }, /* 18 - Slot 1 */
236 { 1, 2, 3, 0 }, /* 19 - Slot 2 */
237 { 2, 3, 0, 1 }, /* 20 - Slot 3 */
238 { 3, 0, 1, 2 }, /* 21 - Slot 4 */
239 };
240
241 const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
242 int i, j;
243
244 for (i = 0; i < 6; i++)
245 for (j = 0; j < 4; j++)
246 pci_irq_table[i][j] =
247 ((pci_irq_table[i][j] + 5 -
248 cds_pci_slot) & 0x3) + PIRQ0A;
249
250 return PCI_IRQ_TABLE_LOOKUP;
251 } else {
252 /* Handle PCI2 interrupts (if we have one) */
253 char pci_irq_table[][4] =
254 {
255 /*
256 * We only have one slot and one interrupt
257 * going to PIRQA - PIRQD */
258 { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
259 };
260
261 const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
262
263 return PCI_IRQ_TABLE_LOOKUP;
264 }
265}
266
267#define ARCADIA_HOST_BRIDGE_IDSEL 17
268#define ARCADIA_2ND_BRIDGE_IDSEL 3
269
270extern int mpc85xx_pci1_last_busno;
271
272int
273mpc85xx_exclude_device(u_char bus, u_char devfn)
274{
275 if (bus == 0 && PCI_SLOT(devfn) == 0)
276 return PCIBIOS_DEVICE_NOT_FOUND;
277#ifdef CONFIG_85xx_PCI2
278 if (mpc85xx_pci1_last_busno)
279 if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
280 return PCIBIOS_DEVICE_NOT_FOUND;
281#endif
282 /* We explicitly do not go past the Tundra 320 Bridge */
283 if (bus == 1)
284 return PCIBIOS_DEVICE_NOT_FOUND;
285 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
286 return PCIBIOS_DEVICE_NOT_FOUND;
287 else
288 return PCIBIOS_SUCCESSFUL;
289}
290#endif /* CONFIG_PCI */
291
292TODC_ALLOC();
293
294/* ************************************************************************
295 *
296 * Setup the architecture
297 *
298 */
299static void __init
300mpc85xx_cds_setup_arch(void)
301{
302 bd_t *binfo = (bd_t *) __res;
303 unsigned int freq;
304 struct gianfar_platform_data *pdata;
305
306 /* get the core frequency */
307 freq = binfo->bi_intfreq;
308
309 printk("mpc85xx_cds_setup_arch\n");
310
311#ifdef CONFIG_CPM2
312 cpm2_reset();
313#endif
314
315 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
316 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
317 printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
318
319 /* Setup TODC access */
320 TODC_INIT(TODC_TYPE_DS1743,
321 0,
322 0,
323 ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
324 8);
325
326 /* Set loops_per_jiffy to a half-way reasonable value,
327 for use until calibrate_delay gets called. */
328 loops_per_jiffy = freq / HZ;
329
330#ifdef CONFIG_PCI
331 /* setup PCI host bridges */
332 mpc85xx_setup_hose();
333#endif
334
335#ifdef CONFIG_SERIAL_8250
336 mpc85xx_early_serial_map();
337#endif
338
339#ifdef CONFIG_SERIAL_TEXT_DEBUG
340 /* Invalidate the entry we stole earlier the serial ports
341 * should be properly mapped */
342 invalidate_tlbcam_entry(NUM_TLBCAMS - 1);
343#endif
344
345 /* setup the board related information for the enet controllers */
346 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
347 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
348 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
349 pdata->phyid = 0;
350 /* fixup phy address */
351 pdata->phy_reg_addr += binfo->bi_immr_base;
352 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
353
354 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
355 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
356 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
357 pdata->phyid = 1;
358 /* fixup phy address */
359 pdata->phy_reg_addr += binfo->bi_immr_base;
360 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
361
362
363#ifdef CONFIG_BLK_DEV_INITRD
364 if (initrd_start)
365 ROOT_DEV = Root_RAM0;
366 else
367#endif
368#ifdef CONFIG_ROOT_NFS
369 ROOT_DEV = Root_NFS;
370#else
371 ROOT_DEV = Root_HDA1;
372#endif
373}
374
375/* ************************************************************************ */
376void __init
377platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
378 unsigned long r6, unsigned long r7)
379{
380 /* parse_bootinfo must always be called first */
381 parse_bootinfo(find_bootinfo());
382
383 /*
384 * If we were passed in a board information, copy it into the
385 * residual data area.
386 */
387 if (r3) {
388 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
389 sizeof (bd_t));
390
391 }
392#ifdef CONFIG_SERIAL_TEXT_DEBUG
393 {
394 bd_t *binfo = (bd_t *) __res;
395 struct uart_port p;
396
397 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
398 settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base,
399 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
400
401 memset(&p, 0, sizeof (p));
402 p.iotype = SERIAL_IO_MEM;
403 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
404 p.uartclk = binfo->bi_busfreq;
405
406 gen550_init(0, &p);
407
408 memset(&p, 0, sizeof (p));
409 p.iotype = SERIAL_IO_MEM;
410 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
411 p.uartclk = binfo->bi_busfreq;
412
413 gen550_init(1, &p);
414 }
415#endif
416
417#if defined(CONFIG_BLK_DEV_INITRD)
418 /*
419 * If the init RAM disk has been configured in, and there's a valid
420 * starting address for it, set it up.
421 */
422 if (r4) {
423 initrd_start = r4 + KERNELBASE;
424 initrd_end = r5 + KERNELBASE;
425 }
426#endif /* CONFIG_BLK_DEV_INITRD */
427
428 /* Copy the kernel command line arguments to a safe place. */
429
430 if (r6) {
431 *(char *) (r7 + KERNELBASE) = 0;
432 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
433 }
434
435 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
436
437 /* setup the PowerPC module struct */
438 ppc_md.setup_arch = mpc85xx_cds_setup_arch;
439 ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
440
441 ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
442 ppc_md.get_irq = openpic_get_irq;
443
444 ppc_md.restart = mpc85xx_restart;
445 ppc_md.power_off = mpc85xx_power_off;
446 ppc_md.halt = mpc85xx_halt;
447
448 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
449
450 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
451
452 ppc_md.time_init = todc_time_init;
453 ppc_md.set_rtc_time = todc_set_rtc_time;
454 ppc_md.get_rtc_time = todc_get_rtc_time;
455
456 ppc_md.nvram_read_val = todc_direct_read_val;
457 ppc_md.nvram_write_val = todc_direct_write_val;
458
459#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
460 ppc_md.progress = gen550_progress;
461#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
462
463 if (ppc_md.progress)
464 ppc_md.progress("mpc85xx_cds_init(): exit", 0);
465
466 return;
467}
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
new file mode 100644
index 000000000000..7627d77504bd
--- /dev/null
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
@@ -0,0 +1,80 @@
1/*
2 * arch/ppc/platforms/85xx/mpc85xx_cds_common.h
3 *
4 * MPC85xx CDS board definitions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifndef __MACH_MPC85XX_CDS_H__
18#define __MACH_MPC85XX_CDS_H__
19
20#include <linux/config.h>
21#include <linux/serial.h>
22#include <asm/ppcboot.h>
23#include <linux/initrd.h>
24#include <syslib/ppc85xx_setup.h>
25
26#define BOARD_CCSRBAR ((uint)0xe0000000)
27#define CCSRBAR_SIZE ((uint)1024*1024)
28
29/* CADMUS info */
30#define CADMUS_BASE (0xf8004000)
31#define CADMUS_SIZE (256)
32#define CM_VER (0)
33#define CM_CSR (1)
34#define CM_RST (2)
35
36/* CDS NVRAM/RTC */
37#define CDS_RTC_ADDR (0xf8000000)
38#define CDS_RTC_SIZE (8 * 1024)
39
40/* PCI config */
41#define PCI1_CFG_ADDR_OFFSET (0x8000)
42#define PCI1_CFG_DATA_OFFSET (0x8004)
43
44#define PCI2_CFG_ADDR_OFFSET (0x9000)
45#define PCI2_CFG_DATA_OFFSET (0x9004)
46
47/* PCI interrupt controller */
48#define PIRQ0A MPC85xx_IRQ_EXT0
49#define PIRQ0B MPC85xx_IRQ_EXT1
50#define PIRQ0C MPC85xx_IRQ_EXT2
51#define PIRQ0D MPC85xx_IRQ_EXT3
52#define PIRQ1A MPC85xx_IRQ_EXT11
53
54/* PCI 1 memory map */
55#define MPC85XX_PCI1_LOWER_IO 0x00000000
56#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
57
58#define MPC85XX_PCI1_LOWER_MEM 0x80000000
59#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
60
61#define MPC85XX_PCI1_IO_BASE 0xe2000000
62#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
63
64#define MPC85XX_PCI1_IO_SIZE 0x01000000
65
66/* PCI 2 memory map */
67/* Note: the standard PPC fixups will cause IO space to get bumped by
68 * hose->io_base_virt - isa_io_base => MPC85XX_PCI1_IO_SIZE */
69#define MPC85XX_PCI2_LOWER_IO 0x00000000
70#define MPC85XX_PCI2_UPPER_IO 0x00ffffff
71
72#define MPC85XX_PCI2_LOWER_MEM 0xa0000000
73#define MPC85XX_PCI2_UPPER_MEM 0xbfffffff
74
75#define MPC85XX_PCI2_IO_BASE 0xe3000000
76#define MPC85XX_PCI2_MEM_OFFSET 0x00000000
77
78#define MPC85XX_PCI2_IO_SIZE 0x01000000
79
80#endif /* __MACH_MPC85XX_CDS_H__ */
diff --git a/arch/ppc/platforms/85xx/sbc8560.c b/arch/ppc/platforms/85xx/sbc8560.c
new file mode 100644
index 000000000000..9ab05e590c3e
--- /dev/null
+++ b/arch/ppc/platforms/85xx/sbc8560.c
@@ -0,0 +1,227 @@
1/*
2 * arch/ppc/platforms/85xx/sbc8560.c
3 *
4 * Wind River SBC8560 board specific routines
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/config.h>
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/major.h>
25#include <linux/console.h>
26#include <linux/delay.h>
27#include <linux/irq.h>
28#include <linux/seq_file.h>
29#include <linux/root_dev.h>
30#include <linux/serial.h>
31#include <linux/tty.h> /* for linux/serial_core.h */
32#include <linux/serial_core.h>
33#include <linux/initrd.h>
34#include <linux/module.h>
35#include <linux/fsl_devices.h>
36
37#include <asm/system.h>
38#include <asm/pgtable.h>
39#include <asm/page.h>
40#include <asm/atomic.h>
41#include <asm/time.h>
42#include <asm/io.h>
43#include <asm/machdep.h>
44#include <asm/prom.h>
45#include <asm/open_pic.h>
46#include <asm/bootinfo.h>
47#include <asm/pci-bridge.h>
48#include <asm/mpc85xx.h>
49#include <asm/irq.h>
50#include <asm/immap_85xx.h>
51#include <asm/kgdb.h>
52#include <asm/ppc_sys.h>
53#include <mm/mmu_decl.h>
54
55#include <syslib/ppc85xx_common.h>
56#include <syslib/ppc85xx_setup.h>
57
58#ifdef CONFIG_SERIAL_8250
59static void __init
60sbc8560_early_serial_map(void)
61{
62 struct uart_port uart_req;
63
64 /* Setup serial port access */
65 memset(&uart_req, 0, sizeof (uart_req));
66 uart_req.irq = MPC85xx_IRQ_EXT9;
67 uart_req.flags = STD_COM_FLAGS;
68 uart_req.uartclk = BASE_BAUD * 16;
69 uart_req.iotype = SERIAL_IO_MEM;
70 uart_req.mapbase = UARTA_ADDR;
71 uart_req.membase = ioremap(uart_req.mapbase, MPC85xx_UART0_SIZE);
72 uart_req.type = PORT_16650;
73
74#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
75 gen550_init(0, &uart_req);
76#endif
77
78 if (early_serial_setup(&uart_req) != 0)
79 printk("Early serial init of port 0 failed\n");
80
81 /* Assume early_serial_setup() doesn't modify uart_req */
82 uart_req.line = 1;
83 uart_req.mapbase = UARTB_ADDR;
84 uart_req.membase = ioremap(uart_req.mapbase, MPC85xx_UART1_SIZE);
85 uart_req.irq = MPC85xx_IRQ_EXT10;
86
87#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
88 gen550_init(1, &uart_req);
89#endif
90
91 if (early_serial_setup(&uart_req) != 0)
92 printk("Early serial init of port 1 failed\n");
93}
94#endif
95
96/* ************************************************************************
97 *
98 * Setup the architecture
99 *
100 */
101static void __init
102sbc8560_setup_arch(void)
103{
104 bd_t *binfo = (bd_t *) __res;
105 unsigned int freq;
106 struct gianfar_platform_data *pdata;
107
108 /* get the core frequency */
109 freq = binfo->bi_intfreq;
110
111 if (ppc_md.progress)
112 ppc_md.progress("sbc8560_setup_arch()", 0);
113
114 /* Set loops_per_jiffy to a half-way reasonable value,
115 for use until calibrate_delay gets called. */
116 loops_per_jiffy = freq / HZ;
117
118#ifdef CONFIG_PCI
119 /* setup PCI host bridges */
120 mpc85xx_setup_hose();
121#endif
122#ifdef CONFIG_SERIAL_8250
123 sbc8560_early_serial_map();
124#endif
125#ifdef CONFIG_SERIAL_TEXT_DEBUG
126 /* Invalidate the entry we stole earlier the serial ports
127 * should be properly mapped */
128 invalidate_tlbcam_entry(NUM_TLBCAMS - 1);
129#endif
130
131 /* setup the board related information for the enet controllers */
132 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
133 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
134 pdata->interruptPHY = MPC85xx_IRQ_EXT6;
135 pdata->phyid = 25;
136 /* fixup phy address */
137 pdata->phy_reg_addr += binfo->bi_immr_base;
138 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
139
140 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
141 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
142 pdata->interruptPHY = MPC85xx_IRQ_EXT7;
143 pdata->phyid = 26;
144 /* fixup phy address */
145 pdata->phy_reg_addr += binfo->bi_immr_base;
146 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
147
148#ifdef CONFIG_BLK_DEV_INITRD
149 if (initrd_start)
150 ROOT_DEV = Root_RAM0;
151 else
152#endif
153#ifdef CONFIG_ROOT_NFS
154 ROOT_DEV = Root_NFS;
155#else
156 ROOT_DEV = Root_HDA1;
157#endif
158}
159
160/* ************************************************************************ */
161void __init
162platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
163 unsigned long r6, unsigned long r7)
164{
165 /* parse_bootinfo must always be called first */
166 parse_bootinfo(find_bootinfo());
167
168 /*
169 * If we were passed in a board information, copy it into the
170 * residual data area.
171 */
172 if (r3) {
173 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
174 sizeof (bd_t));
175 }
176
177#ifdef CONFIG_SERIAL_TEXT_DEBUG
178 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
179 settlbcam(NUM_TLBCAMS - 1, UARTA_ADDR,
180 UARTA_ADDR, 0x1000, _PAGE_IO, 0);
181#endif
182
183#if defined(CONFIG_BLK_DEV_INITRD)
184 /*
185 * If the init RAM disk has been configured in, and there's a valid
186 * starting address for it, set it up.
187 */
188 if (r4) {
189 initrd_start = r4 + KERNELBASE;
190 initrd_end = r5 + KERNELBASE;
191 }
192#endif /* CONFIG_BLK_DEV_INITRD */
193
194 /* Copy the kernel command line arguments to a safe place. */
195
196 if (r6) {
197 *(char *) (r7 + KERNELBASE) = 0;
198 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
199 }
200
201 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
202
203 /* setup the PowerPC module struct */
204 ppc_md.setup_arch = sbc8560_setup_arch;
205 ppc_md.show_cpuinfo = sbc8560_show_cpuinfo;
206
207 ppc_md.init_IRQ = sbc8560_init_IRQ;
208 ppc_md.get_irq = openpic_get_irq;
209
210 ppc_md.restart = mpc85xx_restart;
211 ppc_md.power_off = mpc85xx_power_off;
212 ppc_md.halt = mpc85xx_halt;
213
214 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
215
216 ppc_md.time_init = NULL;
217 ppc_md.set_rtc_time = NULL;
218 ppc_md.get_rtc_time = NULL;
219 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
220
221#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
222 ppc_md.progress = gen550_progress;
223#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
224
225 if (ppc_md.progress)
226 ppc_md.progress("sbc8560_init(): exit", 0);
227}
diff --git a/arch/ppc/platforms/85xx/sbc8560.h b/arch/ppc/platforms/85xx/sbc8560.h
new file mode 100644
index 000000000000..5e1b00c77da5
--- /dev/null
+++ b/arch/ppc/platforms/85xx/sbc8560.h
@@ -0,0 +1,49 @@
1/*
2 * arch/ppc/platforms/85xx/sbc8560.h
3 *
4 * Wind River SBC8560 board definitions
5 *
6 * Copyright 2003 Motorola Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MACH_SBC8560_H__
16#define __MACH_SBC8560_H__
17
18#include <linux/config.h>
19#include <platforms/85xx/sbc85xx.h>
20
21#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
22
23#ifdef CONFIG_SERIAL_MANY_PORTS
24#define RS_TABLE_SIZE 64
25#else
26#define RS_TABLE_SIZE 2
27#endif
28
29/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
30#define BASE_BAUD ( 1843200 / 16 )
31
32#ifdef CONFIG_SERIAL_DETECT_IRQ
33#define STD_COM_FLAGS (ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
34#else
35#define STD_COM_FLAGS (ASYNC_SKIP_TEST)
36#endif
37
38#define STD_SERIAL_PORT_DFNS \
39 { 0, BASE_BAUD, UARTA_ADDR, MPC85xx_IRQ_EXT9, STD_COM_FLAGS, /* ttyS0 */ \
40 iomem_base: (u8 *)UARTA_ADDR, \
41 io_type: SERIAL_IO_MEM }, \
42 { 0, BASE_BAUD, UARTB_ADDR, MPC85xx_IRQ_EXT10, STD_COM_FLAGS, /* ttyS1 */ \
43 iomem_base: (u8 *)UARTB_ADDR, \
44 io_type: SERIAL_IO_MEM },
45
46#define SERIAL_PORT_DFNS \
47 STD_SERIAL_PORT_DFNS
48
49#endif /* __MACH_SBC8560_H__ */
diff --git a/arch/ppc/platforms/85xx/sbc85xx.c b/arch/ppc/platforms/85xx/sbc85xx.c
new file mode 100644
index 000000000000..2d638c1c1bd6
--- /dev/null
+++ b/arch/ppc/platforms/85xx/sbc85xx.c
@@ -0,0 +1,203 @@
1/*
2 * arch/ppc/platform/85xx/sbc85xx.c
3 *
4 * WindRiver PowerQUICC III SBC85xx board common routines
5 *
6 * Copyright 2002, 2003 Motorola Inc.
7 * Copyright 2004 Red Hat, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/config.h>
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/reboot.h>
21#include <linux/pci.h>
22#include <linux/kdev_t.h>
23#include <linux/major.h>
24#include <linux/console.h>
25#include <linux/delay.h>
26#include <linux/irq.h>
27#include <linux/seq_file.h>
28#include <linux/serial.h>
29#include <linux/module.h>
30
31#include <asm/system.h>
32#include <asm/pgtable.h>
33#include <asm/page.h>
34#include <asm/atomic.h>
35#include <asm/time.h>
36#include <asm/io.h>
37#include <asm/machdep.h>
38#include <asm/prom.h>
39#include <asm/open_pic.h>
40#include <asm/bootinfo.h>
41#include <asm/pci-bridge.h>
42#include <asm/mpc85xx.h>
43#include <asm/irq.h>
44#include <asm/immap_85xx.h>
45#include <asm/ppc_sys.h>
46
47#include <mm/mmu_decl.h>
48
49#include <platforms/85xx/sbc85xx.h>
50
51unsigned char __res[sizeof (bd_t)];
52
53#ifndef CONFIG_PCI
54unsigned long isa_io_base = 0;
55unsigned long isa_mem_base = 0;
56unsigned long pci_dram_offset = 0;
57#endif
58
59extern unsigned long total_memory; /* in mm/init */
60
61/* Internal interrupts are all Level Sensitive, and Positive Polarity */
62
63static u_char sbc8560_openpic_initsenses[] __initdata = {
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
96 0x0, /* External 0: */
97 0x0, /* External 1: */
98#if defined(CONFIG_PCI)
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 0 */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 1 */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 2 */
102 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PCI slot 3 */
103#else
104 0x0, /* External 2: */
105 0x0, /* External 3: */
106 0x0, /* External 4: */
107 0x0, /* External 5: */
108#endif
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 6: PHY */
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
111 0x0, /* External 8: */
112 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: PHY */
113 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 10: PHY */
114 0x0, /* External 11: */
115};
116
117/* ************************************************************************ */
118int
119sbc8560_show_cpuinfo(struct seq_file *m)
120{
121 uint pvid, svid, phid1;
122 uint memsize = total_memory;
123 bd_t *binfo = (bd_t *) __res;
124 unsigned int freq;
125
126 /* get the core frequency */
127 freq = binfo->bi_intfreq;
128
129 pvid = mfspr(SPRN_PVR);
130 svid = mfspr(SPRN_SVR);
131
132 seq_printf(m, "Vendor\t\t: Wind River\n");
133 seq_printf(m, "Machine\t\t: SBC%s\n", cur_ppc_sys_spec->ppc_sys_name);
134 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
135 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
136 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
137
138 /* Display cpu Pll setting */
139 phid1 = mfspr(SPRN_HID1);
140 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
141
142 /* Display the amount of memory */
143 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
144
145 return 0;
146}
147
148void __init
149sbc8560_init_IRQ(void)
150{
151 bd_t *binfo = (bd_t *) __res;
152 /* Determine the Physical Address of the OpenPIC regs */
153 phys_addr_t OpenPIC_PAddr =
154 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
155 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
156 OpenPIC_InitSenses = sbc8560_openpic_initsenses;
157 OpenPIC_NumInitSenses = sizeof (sbc8560_openpic_initsenses);
158
159 /* Skip reserved space and internal sources */
160 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
161 /* Map PIC IRQs 0-11 */
162 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
163
164 /* we let openpic interrupts starting from an offset, to
165 * leave space for cascading interrupts underneath.
166 */
167 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
168
169 return;
170}
171
172/*
173 * interrupt routing
174 */
175
176#ifdef CONFIG_PCI
177int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
178 unsigned char pin)
179{
180 static char pci_irq_table[][4] =
181 /*
182 * PCI IDSEL/INTPIN->INTLINE
183 * A B C D
184 */
185 {
186 {PIRQA, PIRQB, PIRQC, PIRQD},
187 {PIRQD, PIRQA, PIRQB, PIRQC},
188 {PIRQC, PIRQD, PIRQA, PIRQB},
189 {PIRQB, PIRQC, PIRQD, PIRQA},
190 };
191
192 const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
193 return PCI_IRQ_TABLE_LOOKUP;
194}
195
196int mpc85xx_exclude_device(u_char bus, u_char devfn)
197{
198 if (bus == 0 && PCI_SLOT(devfn) == 0)
199 return PCIBIOS_DEVICE_NOT_FOUND;
200 else
201 return PCIBIOS_SUCCESSFUL;
202}
203#endif /* CONFIG_PCI */
diff --git a/arch/ppc/platforms/85xx/sbc85xx.h b/arch/ppc/platforms/85xx/sbc85xx.h
new file mode 100644
index 000000000000..7af93c691a6b
--- /dev/null
+++ b/arch/ppc/platforms/85xx/sbc85xx.h
@@ -0,0 +1,55 @@
1/*
2 * arch/ppc/platforms/85xx/sbc85xx.h
3 *
4 * WindRiver PowerQUICC III SBC85xx common board definitions
5 *
6 * Copyright 2003 Motorola Inc.
7 * Copyright 2004 Red Hat, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __PLATFORMS_85XX_SBC85XX_H__
17#define __PLATFORMS_85XX_SBC85XX_H__
18
19#include <linux/config.h>
20#include <linux/init.h>
21#include <linux/seq_file.h>
22#include <asm/ppcboot.h>
23
24#define BOARD_CCSRBAR ((uint)0xff700000)
25#define CCSRBAR_SIZE ((uint)1024*1024)
26
27#define BCSR_ADDR ((uint)0xfc000000)
28#define BCSR_SIZE ((uint)(16 * 1024 * 1024))
29
30#define UARTA_ADDR (BCSR_ADDR + 0x00700000)
31#define UARTB_ADDR (BCSR_ADDR + 0x00800000)
32#define RTC_DEVICE_ADDR (BCSR_ADDR + 0x00900000)
33#define EEPROM_ADDR (BCSR_ADDR + 0x00b00000)
34
35extern int sbc8560_show_cpuinfo(struct seq_file *m);
36extern void sbc8560_init_IRQ(void) __init;
37
38/* PCI interrupt controller */
39#define PIRQA MPC85xx_IRQ_EXT1
40#define PIRQB MPC85xx_IRQ_EXT2
41#define PIRQC MPC85xx_IRQ_EXT3
42#define PIRQD MPC85xx_IRQ_EXT4
43
44#define MPC85XX_PCI1_LOWER_IO 0x00000000
45#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
46
47#define MPC85XX_PCI1_LOWER_MEM 0x80000000
48#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
49
50#define MPC85XX_PCI1_IO_BASE 0xe2000000
51#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
52
53#define MPC85XX_PCI1_IO_SIZE 0x01000000
54
55#endif /* __PLATFORMS_85XX_SBC85XX_H__ */
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
new file mode 100644
index 000000000000..bc95836e417c
--- /dev/null
+++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -0,0 +1,355 @@
1/*
2 * arch/ppc/platforms/85xx/stx_gp3.c
3 *
4 * STx GP3 board specific routines
5 *
6 * Dan Malek <dan@embeddededge.com>
7 * Copyright 2004 Embedded Edge, LLC
8 *
9 * Copied from mpc8560_ads.c
10 * Copyright 2002, 2003 Motorola Inc.
11 *
12 * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
13 * Copyright 2004-2005 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#include <linux/config.h>
22#include <linux/stddef.h>
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/errno.h>
26#include <linux/reboot.h>
27#include <linux/pci.h>
28#include <linux/kdev_t.h>
29#include <linux/major.h>
30#include <linux/blkdev.h>
31#include <linux/console.h>
32#include <linux/delay.h>
33#include <linux/irq.h>
34#include <linux/root_dev.h>
35#include <linux/seq_file.h>
36#include <linux/serial.h>
37#include <linux/initrd.h>
38#include <linux/module.h>
39#include <linux/fsl_devices.h>
40#include <linux/interrupt.h>
41
42#include <asm/system.h>
43#include <asm/pgtable.h>
44#include <asm/page.h>
45#include <asm/atomic.h>
46#include <asm/time.h>
47#include <asm/io.h>
48#include <asm/machdep.h>
49#include <asm/prom.h>
50#include <asm/open_pic.h>
51#include <asm/bootinfo.h>
52#include <asm/pci-bridge.h>
53#include <asm/mpc85xx.h>
54#include <asm/irq.h>
55#include <asm/immap_85xx.h>
56#include <asm/immap_cpm2.h>
57#include <asm/mpc85xx.h>
58#include <asm/ppc_sys.h>
59
60#include <syslib/cpm2_pic.h>
61#include <syslib/ppc85xx_common.h>
62
63extern void cpm2_reset(void);
64
65unsigned char __res[sizeof(bd_t)];
66
67#ifndef CONFIG_PCI
68unsigned long isa_io_base = 0;
69unsigned long isa_mem_base = 0;
70unsigned long pci_dram_offset = 0;
71#endif
72
73/* Internal interrupts are all Level Sensitive, and Positive Polarity */
74static u8 gp3_openpic_initsenses[] __initdata = {
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
102 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
103 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
104 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
105 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
106 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
107 0x0, /* External 0: */
108#if defined(CONFIG_PCI)
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 1 */
111 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 2 */
112 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 3 */
113#else
114 0x0, /* External 1: */
115 0x0, /* External 2: */
116 0x0, /* External 3: */
117 0x0, /* External 4: */
118#endif
119 0x0, /* External 5: */
120 0x0, /* External 6: */
121 0x0, /* External 7: */
122 0x0, /* External 8: */
123 0x0, /* External 9: */
124 0x0, /* External 10: */
125 0x0, /* External 11: */
126};
127
128/*
129 * Setup the architecture
130 */
131static void __init
132gp3_setup_arch(void)
133{
134 bd_t *binfo = (bd_t *) __res;
135 unsigned int freq;
136 struct gianfar_platform_data *pdata;
137
138 cpm2_reset();
139
140 /* get the core frequency */
141 freq = binfo->bi_intfreq;
142
143 if (ppc_md.progress)
144 ppc_md.progress("gp3_setup_arch()", 0);
145
146 /* Set loops_per_jiffy to a half-way reasonable value,
147 for use until calibrate_delay gets called. */
148 loops_per_jiffy = freq / HZ;
149
150#ifdef CONFIG_PCI
151 /* setup PCI host bridges */
152 mpc85xx_setup_hose();
153#endif
154
155 /* setup the board related information for the enet controllers */
156 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
157/* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
158 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
159 pdata->phyid = 2;
160 pdata->phy_reg_addr += binfo->bi_immr_base;
161 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
162
163 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
164/* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
165 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
166 pdata->phyid = 4;
167 /* fixup phy address */
168 pdata->phy_reg_addr += binfo->bi_immr_base;
169 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
170
171#ifdef CONFIG_BLK_DEV_INITRD
172 if (initrd_start)
173 ROOT_DEV = Root_RAM0;
174 else
175#endif
176#ifdef CONFIG_ROOT_NFS
177 ROOT_DEV = Root_NFS;
178#else
179 ROOT_DEV = Root_HDA1;
180#endif
181
182 printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);
183}
184
185static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
186{
187 while ((irq = cpm2_get_irq(regs)) >= 0)
188 __do_IRQ(irq, regs);
189
190 return IRQ_HANDLED;
191}
192
193static struct irqaction cpm2_irqaction = {
194 .handler = cpm2_cascade,
195 .flags = SA_INTERRUPT,
196 .mask = CPU_MASK_NONE,
197 .name = "cpm2_cascade",
198};
199
200static void __init
201gp3_init_IRQ(void)
202{
203 int i;
204 bd_t *binfo = (bd_t *) __res;
205
206 /*
207 * Setup OpenPIC
208 */
209
210 /* Determine the Physical Address of the OpenPIC regs */
211 phys_addr_t OpenPIC_PAddr =
212 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
213 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
214 OpenPIC_InitSenses = gp3_openpic_initsenses;
215 OpenPIC_NumInitSenses = sizeof (gp3_openpic_initsenses);
216
217 /* Skip reserved space and internal sources */
218 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
219
220 /* Map PIC IRQs 0-11 */
221 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
222
223 /*
224 * Let openpic interrupts starting from an offset, to
225 * leave space for cascading interrupts underneath.
226 */
227 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
228
229 /* Setup CPM2 PIC */
230 cpm2_init_IRQ();
231
232 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
233
234 return;
235}
236
237static int
238gp3_show_cpuinfo(struct seq_file *m)
239{
240 uint pvid, svid, phid1;
241 bd_t *binfo = (bd_t *) __res;
242 uint memsize;
243 unsigned int freq;
244 extern unsigned long total_memory; /* in mm/init */
245
246 /* get the core frequency */
247 freq = binfo->bi_intfreq;
248
249 pvid = mfspr(SPRN_PVR);
250 svid = mfspr(SPRN_SVR);
251
252 memsize = total_memory;
253
254 seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
255 seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
256 seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
257 freq % 1000000);
258 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
259 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
260
261 /* Display cpu Pll setting */
262 phid1 = mfspr(SPRN_HID1);
263 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
264
265 /* Display the amount of memory */
266 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
267
268 return 0;
269}
270
271#ifdef CONFIG_PCI
272int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
273 unsigned char pin)
274{
275 static char pci_irq_table[][4] =
276 /*
277 * PCI IDSEL/INTPIN->INTLINE
278 * A B C D
279 */
280 {
281 {PIRQA, PIRQB, PIRQC, PIRQD},
282 {PIRQD, PIRQA, PIRQB, PIRQC},
283 {PIRQC, PIRQD, PIRQA, PIRQB},
284 {PIRQB, PIRQC, PIRQD, PIRQA},
285 };
286
287 const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
288 return PCI_IRQ_TABLE_LOOKUP;
289}
290
291int mpc85xx_exclude_device(u_char bus, u_char devfn)
292{
293 if (bus == 0 && PCI_SLOT(devfn) == 0)
294 return PCIBIOS_DEVICE_NOT_FOUND;
295 else
296 return PCIBIOS_SUCCESSFUL;
297}
298#endif /* CONFIG_PCI */
299
300void __init
301platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
302 unsigned long r6, unsigned long r7)
303{
304 /* parse_bootinfo must always be called first */
305 parse_bootinfo(find_bootinfo());
306
307 /*
308 * If we were passed in a board information, copy it into the
309 * residual data area.
310 */
311 if (r3) {
312 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
313 sizeof (bd_t));
314
315 }
316#if defined(CONFIG_BLK_DEV_INITRD)
317 /*
318 * If the init RAM disk has been configured in, and there's a valid
319 * starting address for it, set it up.
320 */
321 if (r4) {
322 initrd_start = r4 + KERNELBASE;
323 initrd_end = r5 + KERNELBASE;
324 }
325#endif /* CONFIG_BLK_DEV_INITRD */
326
327 /* Copy the kernel command line arguments to a safe place. */
328
329 if (r6) {
330 *(char *) (r7 + KERNELBASE) = 0;
331 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
332 }
333
334 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
335
336 /* setup the PowerPC module struct */
337 ppc_md.setup_arch = gp3_setup_arch;
338 ppc_md.show_cpuinfo = gp3_show_cpuinfo;
339
340 ppc_md.init_IRQ = gp3_init_IRQ;
341 ppc_md.get_irq = openpic_get_irq;
342
343 ppc_md.restart = mpc85xx_restart;
344 ppc_md.power_off = mpc85xx_power_off;
345 ppc_md.halt = mpc85xx_halt;
346
347 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
348
349 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
350
351 if (ppc_md.progress)
352 ppc_md.progress("platform_init(): exit", 0);
353
354 return;
355}
diff --git a/arch/ppc/platforms/85xx/stx_gp3.h b/arch/ppc/platforms/85xx/stx_gp3.h
new file mode 100644
index 000000000000..7bcc6c35a417
--- /dev/null
+++ b/arch/ppc/platforms/85xx/stx_gp3.h
@@ -0,0 +1,74 @@
1/*
2 * arch/ppc/platforms/stx8560_gp3.h
3 *
4 * STx GP3 board definitions
5 *
6 * Dan Malek (dan@embeddededge.com)
7 * Copyright 2004 Embedded Edge, LLC
8 *
9 * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
10 * Copyright 2004-2005 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18
19#ifndef __MACH_STX_GP3_H
20#define __MACH_STX_GP3_H
21
22#include <linux/config.h>
23#include <linux/init.h>
24#include <linux/seq_file.h>
25#include <asm/ppcboot.h>
26
27#define BOARD_CCSRBAR ((uint)0xe0000000)
28#define CCSRBAR_SIZE ((uint)1024*1024)
29
30#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
31
32#define BCSR_ADDR ((uint)0xfc000000)
33#define BCSR_SIZE ((uint)(16 * 1024))
34
35#define BCSR_TSEC1_RESET 0x00000080
36#define BCSR_TSEC2_RESET 0x00000040
37#define BCSR_LED1 0x00000008
38#define BCSR_LED2 0x00000004
39#define BCSR_LED3 0x00000002
40#define BCSR_LED4 0x00000001
41
42extern void mpc85xx_setup_hose(void) __init;
43extern void mpc85xx_restart(char *cmd);
44extern void mpc85xx_power_off(void);
45extern void mpc85xx_halt(void);
46extern int mpc85xx_show_cpuinfo(struct seq_file *m);
47extern void mpc85xx_init_IRQ(void) __init;
48extern unsigned long mpc85xx_find_end_of_memory(void) __init;
49extern void mpc85xx_calibrate_decr(void) __init;
50
51#define PCI_CFG_ADDR_OFFSET (0x8000)
52#define PCI_CFG_DATA_OFFSET (0x8004)
53
54/* PCI interrupt controller */
55#define PIRQA MPC85xx_IRQ_EXT1
56#define PIRQB MPC85xx_IRQ_EXT2
57#define PIRQC MPC85xx_IRQ_EXT3
58#define PIRQD MPC85xx_IRQ_EXT4
59#define PCI_MIN_IDSEL 16
60#define PCI_MAX_IDSEL 19
61#define PCI_IRQ_SLOT 4
62
63#define MPC85XX_PCI1_LOWER_IO 0x00000000
64#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
65
66#define MPC85XX_PCI1_LOWER_MEM 0x80000000
67#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
68
69#define MPC85XX_PCI1_IO_BASE 0xe2000000
70#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
71
72#define MPC85XX_PCI1_IO_SIZE 0x01000000
73
74#endif /* __MACH_STX_GP3_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 12:45:02 -0500