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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/ppc/platforms/4xx
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/ppc/platforms/4xx')
-rw-r--r--arch/ppc/platforms/4xx/Kconfig247
-rw-r--r--arch/ppc/platforms/4xx/Makefile27
-rw-r--r--arch/ppc/platforms/4xx/ash.c250
-rw-r--r--arch/ppc/platforms/4xx/ash.h83
-rw-r--r--arch/ppc/platforms/4xx/bubinga.c263
-rw-r--r--arch/ppc/platforms/4xx/bubinga.h69
-rw-r--r--arch/ppc/platforms/4xx/cpci405.c84
-rw-r--r--arch/ppc/platforms/4xx/cpci405.h37
-rw-r--r--arch/ppc/platforms/4xx/ebony.c356
-rw-r--r--arch/ppc/platforms/4xx/ebony.h91
-rw-r--r--arch/ppc/platforms/4xx/ep405.c197
-rw-r--r--arch/ppc/platforms/4xx/ep405.h54
-rw-r--r--arch/ppc/platforms/4xx/ibm405ep.c143
-rw-r--r--arch/ppc/platforms/4xx/ibm405ep.h148
-rw-r--r--arch/ppc/platforms/4xx/ibm405gp.c120
-rw-r--r--arch/ppc/platforms/4xx/ibm405gp.h151
-rw-r--r--arch/ppc/platforms/4xx/ibm405gpr.c117
-rw-r--r--arch/ppc/platforms/4xx/ibm405gpr.h151
-rw-r--r--arch/ppc/platforms/4xx/ibm440gp.c164
-rw-r--r--arch/ppc/platforms/4xx/ibm440gp.h66
-rw-r--r--arch/ppc/platforms/4xx/ibm440gx.c234
-rw-r--r--arch/ppc/platforms/4xx/ibm440gx.h74
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.c131
-rw-r--r--arch/ppc/platforms/4xx/ibm440sp.h64
-rw-r--r--arch/ppc/platforms/4xx/ibmnp405h.c172
-rw-r--r--arch/ppc/platforms/4xx/ibmnp405h.h157
-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.c83
-rw-r--r--arch/ppc/platforms/4xx/ibmstb4.h238
-rw-r--r--arch/ppc/platforms/4xx/ibmstbx25.c68
-rw-r--r--arch/ppc/platforms/4xx/ibmstbx25.h261
-rw-r--r--arch/ppc/platforms/4xx/luan.c387
-rw-r--r--arch/ppc/platforms/4xx/luan.h80
-rw-r--r--arch/ppc/platforms/4xx/oak.c255
-rw-r--r--arch/ppc/platforms/4xx/oak.h96
-rw-r--r--arch/ppc/platforms/4xx/oak_setup.h50
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c367
-rw-r--r--arch/ppc/platforms/4xx/ocotea.h88
-rw-r--r--arch/ppc/platforms/4xx/redwood5.c110
-rw-r--r--arch/ppc/platforms/4xx/redwood5.h54
-rw-r--r--arch/ppc/platforms/4xx/redwood6.c159
-rw-r--r--arch/ppc/platforms/4xx/redwood6.h55
-rw-r--r--arch/ppc/platforms/4xx/sycamore.c278
-rw-r--r--arch/ppc/platforms/4xx/sycamore.h67
-rw-r--r--arch/ppc/platforms/4xx/virtex-ii_pro.c60
-rw-r--r--arch/ppc/platforms/4xx/virtex-ii_pro.h99
-rw-r--r--arch/ppc/platforms/4xx/walnut.c249
-rw-r--r--arch/ppc/platforms/4xx/walnut.h72
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml300.c146
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml300.h47
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h310
50 files changed, 7329 insertions, 0 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
new file mode 100644
index 000000000000..a0612a86455a
--- /dev/null
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -0,0 +1,247 @@
1config 4xx
2 bool
3 depends on 40x || 44x
4 default y
5
6menu "IBM 4xx options"
7 depends on 4xx
8
9choice
10 prompt "Machine Type"
11 depends on 40x
12 default WALNUT
13
14config ASH
15 bool "Ash"
16 help
17 This option enables support for the IBM NP405H evaluation board.
18
19config BUBINGA
20 bool "Bubinga"
21 help
22 This option enables support for the IBM 405EP evaluation board.
23
24config CPCI405
25 bool "CPCI405"
26 help
27 This option enables support for the CPCI405 board.
28
29config EP405
30 bool "EP405/EP405PC"
31 help
32 This option enables support for the EP405/EP405PC boards.
33
34config OAK
35 bool "Oak"
36 help
37 This option enables support for the IBM 403GCX evaluation board.
38
39config REDWOOD_5
40 bool "Redwood-5"
41 help
42 This option enables support for the IBM STB04 evaluation board.
43
44config REDWOOD_6
45 bool "Redwood-6"
46 help
47 This option enables support for the IBM STBx25xx evaluation board.
48
49config SYCAMORE
50 bool "Sycamore"
51 help
52 This option enables support for the IBM PPC405GPr evaluation board.
53
54config WALNUT
55 bool "Walnut"
56 help
57 This option enables support for the IBM PPC405GP evaluation board.
58
59config XILINX_ML300
60 bool "Xilinx-ML300"
61 help
62 This option enables support for the Xilinx ML300 evaluation board.
63
64endchoice
65
66choice
67 prompt "Machine Type"
68 depends on 44x
69 default EBONY
70
71config EBONY
72 bool "Ebony"
73 help
74 This option enables support for the IBM PPC440GP evaluation board.
75
76config LUAN
77 bool "Luan"
78 help
79 This option enables support for the IBM PPC440SP evaluation board.
80
81config OCOTEA
82 bool "Ocotea"
83 help
84 This option enables support for the IBM PPC440GX evaluation board.
85
86endchoice
87
88config EP405PC
89 bool "EP405PC Support"
90 depends on EP405
91
92
93# It's often necessary to know the specific 4xx processor type.
94# Fortunately, it is impled (so far) from the board type, so we
95# don't need to ask more redundant questions.
96config NP405H
97 bool
98 depends on ASH
99 default y
100
101config 440GP
102 bool
103 depends on EBONY
104 default y
105
106config 440GX
107 bool
108 depends on OCOTEA
109 default y
110
111config 440SP
112 bool
113 depends on LUAN
114 default y
115
116config 440
117 bool
118 depends on 440GP || 440SP
119 default y
120
121config 440A
122 bool
123 depends on 440GX
124 default y
125
126# All 405-based cores up until the 405GPR and 405EP have this errata.
127config IBM405_ERR77
128 bool
129 depends on 40x && !403GCX && !405GPR
130 default y
131
132# All 40x-based cores, up until the 405GPR and 405EP have this errata.
133config IBM405_ERR51
134 bool
135 depends on 40x && !405GPR
136 default y
137
138config BOOKE
139 bool
140 depends on 44x
141 default y
142
143config IBM_OCP
144 bool
145 depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
146 default y
147
148config XILINX_OCP
149 bool
150 depends on XILINX_ML300
151 default y
152
153config IBM_EMAC4
154 bool
155 depends on 440GX || 440SP
156 default y
157
158config BIOS_FIXUP
159 bool
160 depends on BUBINGA || EP405 || SYCAMORE || WALNUT
161 default y
162
163config 403GCX
164 bool
165 depends OAK
166 default y
167
168config 405EP
169 bool
170 depends on BUBINGA
171 default y
172
173config 405GP
174 bool
175 depends on CPCI405 || EP405 || WALNUT
176 default y
177
178config 405GPR
179 bool
180 depends on SYCAMORE
181 default y
182
183config VIRTEX_II_PRO
184 bool
185 depends on XILINX_ML300
186 default y
187
188config STB03xxx
189 bool
190 depends on REDWOOD_5 || REDWOOD_6
191 default y
192
193config EMBEDDEDBOOT
194 bool
195 depends on EP405 || XILINX_ML300
196 default y
197
198config IBM_OPENBIOS
199 bool
200 depends on ASH || BUBINGA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
201 default y
202
203config PPC4xx_DMA
204 bool "PPC4xx DMA controller support"
205 depends on 4xx
206
207config PPC4xx_EDMA
208 bool
209 depends on !STB03xxx && PPC4xx_DMA
210 default y
211
212config PPC_GEN550
213 bool
214 depends on 4xx
215 default y
216
217config PM
218 bool "Power Management support (EXPERIMENTAL)"
219 depends on 4xx && EXPERIMENTAL
220
221choice
222 prompt "TTYS0 device and default console"
223 depends on 40x
224 default UART0_TTYS0
225
226config UART0_TTYS0
227 bool "UART0"
228
229config UART0_TTYS1
230 bool "UART1"
231
232endchoice
233
234config SERIAL_SICC
235 bool "SICC Serial port support"
236 depends on STB03xxx
237
238config UART1_DFLT_CONSOLE
239 bool
240 depends on SERIAL_SICC && UART0_TTYS1
241 default y
242
243config SERIAL_SICC_CONSOLE
244 bool
245 depends on SERIAL_SICC && UART0_TTYS1
246 default y
247endmenu
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
new file mode 100644
index 000000000000..ea470c6adbb6
--- /dev/null
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -0,0 +1,27 @@
1#
2# Makefile for the PowerPC 4xx linux kernel.
3
4obj-$(CONFIG_ASH) += ash.o
5obj-$(CONFIG_CPCI405) += cpci405.o
6obj-$(CONFIG_EBONY) += ebony.o
7obj-$(CONFIG_EP405) += ep405.o
8obj-$(CONFIG_BUBINGA) += bubinga.o
9obj-$(CONFIG_LUAN) += luan.o
10obj-$(CONFIG_OAK) += oak.o
11obj-$(CONFIG_OCOTEA) += ocotea.o
12obj-$(CONFIG_REDWOOD_5) += redwood5.o
13obj-$(CONFIG_REDWOOD_6) += redwood6.o
14obj-$(CONFIG_SYCAMORE) += sycamore.o
15obj-$(CONFIG_WALNUT) += walnut.o
16obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o
17
18obj-$(CONFIG_405GP) += ibm405gp.o
19obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
20obj-$(CONFIG_NP405H) += ibmnp405h.o
21obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
22obj-$(CONFIG_440GP) += ibm440gp.o
23obj-$(CONFIG_440GX) += ibm440gx.o
24obj-$(CONFIG_440SP) += ibm440sp.o
25obj-$(CONFIG_405EP) += ibm405ep.o
26obj-$(CONFIG_405GPR) += ibm405gpr.o
27obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o
diff --git a/arch/ppc/platforms/4xx/ash.c b/arch/ppc/platforms/4xx/ash.c
new file mode 100644
index 000000000000..ce2911793716
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ash.c
@@ -0,0 +1,250 @@
1/*
2 * arch/ppc/platforms/4xx/ash.c
3 *
4 * Support for the IBM NP405H ash eval board
5 *
6 * Author: Armin Kuster <akuster@mvista.com>
7 *
8 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/pagemap.h>
16#include <linux/pci.h>
17
18#include <asm/machdep.h>
19#include <asm/pci-bridge.h>
20#include <asm/io.h>
21#include <asm/ocp.h>
22#include <asm/ibm_ocp_pci.h>
23#include <asm/todc.h>
24
25#ifdef DEBUG
26#define DBG(x...) printk(x)
27#else
28#define DBG(x...)
29#endif
30
31void *ash_rtc_base;
32
33/* Some IRQs unique to Walnut.
34 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
35 */
36int __init
37ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
38{
39 static char pci_irq_table[][4] =
40 /*
41 * PCI IDSEL/INTPIN->INTLINE
42 * A B C D
43 */
44 {
45 {24, 24, 24, 24}, /* IDSEL 1 - PCI slot 1 */
46 {25, 25, 25, 25}, /* IDSEL 2 - PCI slot 2 */
47 {26, 26, 26, 26}, /* IDSEL 3 - PCI slot 3 */
48 {27, 27, 27, 27}, /* IDSEL 4 - PCI slot 4 */
49 };
50
51 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
52 return PCI_IRQ_TABLE_LOOKUP;
53}
54
55void __init
56ash_setup_arch(void)
57{
58 ppc4xx_setup_arch();
59
60 ibm_ocp_set_emac(0, 3);
61
62#ifdef CONFIG_DEBUG_BRINGUP
63 int i;
64 printk("\n");
65 printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
66 printk("\n");
67 printk("bi_s_version\t %s\n", bip->bi_s_version);
68 printk("bi_r_version\t %s\n", bip->bi_r_version);
69 printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
70 bip->bi_memsize / (1024 * 1000));
71 for (i = 0; i < EMAC_NUMS; i++) {
72 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", i,
73 bip->bi_enetaddr[i][0], bip->bi_enetaddr[i][1],
74 bip->bi_enetaddr[i][2], bip->bi_enetaddr[i][3],
75 bip->bi_enetaddr[i][4], bip->bi_enetaddr[i][5]);
76 }
77 printk("bi_pci_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
78 bip->bi_pci_enetaddr[0], bip->bi_pci_enetaddr[1],
79 bip->bi_pci_enetaddr[2], bip->bi_pci_enetaddr[3],
80 bip->bi_pci_enetaddr[4], bip->bi_pci_enetaddr[5]);
81
82 printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
83 bip->bi_intfreq, bip->bi_intfreq / 1000000);
84
85 printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
86 bip->bi_busfreq, bip->bi_busfreq / 1000000);
87 printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
88 bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000);
89
90 printk("\n");
91#endif
92 /* RTC step for ash */
93 ash_rtc_base = (void *) ASH_RTC_VADDR;
94 TODC_INIT(TODC_TYPE_DS1743, ash_rtc_base, ash_rtc_base, ash_rtc_base,
95 8);
96}
97
98void __init
99bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
100{
101 /*
102 * Expected PCI mapping:
103 *
104 * PLB addr PCI memory addr
105 * --------------------- ---------------------
106 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
107 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
108 *
109 * PLB addr PCI io addr
110 * --------------------- ---------------------
111 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
112 *
113 * The following code is simplified by assuming that the bootrom
114 * has been well behaved in following this mapping.
115 */
116
117#ifdef DEBUG
118 int i;
119
120 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
121 printk("PCI bridge regs before fixup \n");
122 for (i = 0; i <= 2; i++) {
123 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
124 printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
125 printk(" pmm%dpcila\t0x%x\n", i,
126 in_le32(&(pcip->pmm[i].pcila)));
127 printk(" pmm%dpciha\t0x%x\n", i,
128 in_le32(&(pcip->pmm[i].pciha)));
129 }
130 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
131 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
132 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
133 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
134 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
135 early_read_config_dword(hose, hose->first_busno,
136 PCI_FUNC(hose->first_busno), bar,
137 &bar_response);
138 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
139 hose->first_busno, PCI_SLOT(hose->first_busno),
140 PCI_FUNC(hose->first_busno), bar, bar_response);
141 }
142
143#endif
144 if (ppc_md.progress)
145 ppc_md.progress("bios_fixup(): enter", 0x800);
146
147 /* added for IBM boot rom version 1.15 bios bar changes -AK */
148
149 /* Disable region first */
150 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
151 /* PLB starting addr, PCI: 0x80000000 */
152 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
153 /* PCI start addr, 0x80000000 */
154 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
155 /* 512MB range of PLB to PCI */
156 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
157 /* Enable no pre-fetch, enable region */
158 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
159 (PPC405_PCI_UPPER_MEM -
160 PPC405_PCI_MEM_BASE)) | 0x01));
161
162 /* Disable region one */
163 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
164 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
165 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
166 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
167 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
168
169 /* Disable region two */
170 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
171 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
172 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
173 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
174 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
175
176 /* Enable PTM1 and PTM2, mapped to PLB address 0. */
177
178 out_le32((void *) &(pcip->ptm1la), 0x00000000);
179 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
180 out_le32((void *) &(pcip->ptm2la), 0x00000000);
181 out_le32((void *) &(pcip->ptm2ms), 0x00000001);
182
183 /* Write zero to PTM1 BAR. */
184
185 early_write_config_dword(hose, hose->first_busno,
186 PCI_FUNC(hose->first_busno),
187 PCI_BASE_ADDRESS_1,
188 0x00000000);
189
190 /* Disable PTM2 (unused) */
191
192 out_le32((void *) &(pcip->ptm2la), 0x00000000);
193 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
194
195 /* end work arround */
196 if (ppc_md.progress)
197 ppc_md.progress("bios_fixup(): done", 0x800);
198
199#ifdef DEBUG
200 printk("PCI bridge regs after fixup \n");
201 for (i = 0; i <= 2; i++) {
202 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
203 printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
204 printk(" pmm%dpcila\t0x%x\n", i,
205 in_le32(&(pcip->pmm[i].pcila)));
206 printk(" pmm%dpciha\t0x%x\n", i,
207 in_le32(&(pcip->pmm[i].pciha)));
208 }
209 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
210 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
211 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
212 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
213
214 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
215 early_read_config_dword(hose, hose->first_busno,
216 PCI_FUNC(hose->first_busno), bar,
217 &bar_response);
218 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
219 hose->first_busno, PCI_SLOT(hose->first_busno),
220 PCI_FUNC(hose->first_busno), bar, bar_response);
221 }
222
223
224#endif
225}
226
227void __init
228ash_map_io(void)
229{
230 ppc4xx_map_io();
231 io_block_mapping(ASH_RTC_VADDR, ASH_RTC_PADDR, ASH_RTC_SIZE, _PAGE_IO);
232}
233
234void __init
235platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
236 unsigned long r6, unsigned long r7)
237{
238 ppc4xx_init(r3, r4, r5, r6, r7);
239
240 ppc_md.setup_arch = ash_setup_arch;
241 ppc_md.setup_io_mappings = ash_map_io;
242
243#ifdef CONFIG_PPC_RTC
244 ppc_md.time_init = todc_time_init;
245 ppc_md.set_rtc_time = todc_set_rtc_time;
246 ppc_md.get_rtc_time = todc_get_rtc_time;
247 ppc_md.nvram_read_val = todc_direct_read_val;
248 ppc_md.nvram_write_val = todc_direct_write_val;
249#endif
250}
diff --git a/arch/ppc/platforms/4xx/ash.h b/arch/ppc/platforms/4xx/ash.h
new file mode 100644
index 000000000000..5f7448ea418d
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ash.h
@@ -0,0 +1,83 @@
1/*
2 * arch/ppc/platforms/4xx/ash.h
3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC
5 * Ash eval board.
6 *
7 * Author: Armin Kuster <akuster@mvista.com>
8 *
9 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_ASH_H__
17#define __ASM_ASH_H__
18#include <platforms/4xx/ibmnp405h.h>
19
20#ifndef __ASSEMBLY__
21/*
22 * Data structure defining board information maintained by the boot
23 * ROM on IBM's "Ash" evaluation board. An effort has been made to
24 * keep the field names consistent with the 8xx 'bd_t' board info
25 * structures.
26 */
27
28typedef struct board_info {
29 unsigned char bi_s_version[4]; /* Version of this structure */
30 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
31 unsigned int bi_memsize; /* DRAM installed, in bytes */
32 unsigned char bi_enetaddr[4][6]; /* Local Ethernet MAC address */
33 unsigned char bi_pci_enetaddr[6];
34 unsigned int bi_intfreq; /* Processor speed, in Hz */
35 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
36 unsigned int bi_pci_busfreq; /* PCI speed in Hz */
37} bd_t;
38
39/* Some 4xx parts use a different timebase frequency from the internal clock.
40*/
41#define bi_tbfreq bi_intfreq
42
43/* Memory map for the IBM "Ash" NP405H evaluation board.
44 */
45
46extern void *ash_rtc_base;
47#define ASH_RTC_PADDR ((uint)0xf0000000)
48#define ASH_RTC_VADDR ASH_RTC_PADDR
49#define ASH_RTC_SIZE ((uint)8*1024)
50
51
52/* Early initialization address mapping for block_io.
53 * Standard 405GP map.
54 */
55#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
56#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
57#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
58#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
59#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
60#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
61#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
62#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
63#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
64#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
65#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
66#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
67
68#define NR_BOARD_IRQS 32
69
70#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
71#define BASE_BAUD 201600
72#else
73#define BASE_BAUD 691200
74#endif
75
76#define PPC4xx_MACHINE_NAME "IBM NP405H Ash"
77
78extern char pci_irq_table[][4];
79
80
81#endif /* !__ASSEMBLY__ */
82#endif /* __ASM_ASH_H__ */
83#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/bubinga.c b/arch/ppc/platforms/4xx/bubinga.c
new file mode 100644
index 000000000000..3678abf86313
--- /dev/null
+++ b/arch/ppc/platforms/4xx/bubinga.c
@@ -0,0 +1,263 @@
1/*
2 * Support for IBM PPC 405EP evaluation board (Bubinga).
3 *
4 * Author: SAW (IBM), derived from walnut.c.
5 * Maintained by MontaVista Software <source@mvista.com>
6 *
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/smp.h>
16#include <linux/threads.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/blkdev.h>
20#include <linux/pci.h>
21#include <linux/rtc.h>
22#include <linux/tty.h>
23#include <linux/serial.h>
24#include <linux/serial_core.h>
25
26#include <asm/system.h>
27#include <asm/pci-bridge.h>
28#include <asm/processor.h>
29#include <asm/machdep.h>
30#include <asm/page.h>
31#include <asm/time.h>
32#include <asm/io.h>
33#include <asm/todc.h>
34#include <asm/kgdb.h>
35#include <asm/ocp.h>
36#include <asm/ibm_ocp_pci.h>
37
38#include <platforms/4xx/ibm405ep.h>
39
40#undef DEBUG
41
42#ifdef DEBUG
43#define DBG(x...) printk(x)
44#else
45#define DBG(x...)
46#endif
47
48extern bd_t __res;
49
50void *bubinga_rtc_base;
51
52/* Some IRQs unique to the board
53 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
54 */
55int __init
56ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
57{
58 static char pci_irq_table[][4] =
59 /*
60 * PCI IDSEL/INTPIN->INTLINE
61 * A B C D
62 */
63 {
64 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
65 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
66 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
67 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
68 };
69
70 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
71 return PCI_IRQ_TABLE_LOOKUP;
72};
73
74/* The serial clock for the chip is an internal clock determined by
75 * different clock speeds/dividers.
76 * Calculate the proper input baud rate and setup the serial driver.
77 */
78static void __init
79bubinga_early_serial_map(void)
80{
81 u32 uart_div;
82 int uart_clock;
83 struct uart_port port;
84
85 /* Calculate the serial clock input frequency
86 *
87 * The base baud is the PLL OUTA (provided in the board info
88 * structure) divided by the external UART Divisor, divided
89 * by 16.
90 */
91 uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
92 uart_clock = __res.bi_pllouta_freq / uart_div;
93
94 /* Setup serial port access */
95 memset(&port, 0, sizeof(port));
96 port.membase = (void*)ACTING_UART0_IO_BASE;
97 port.irq = ACTING_UART0_INT;
98 port.uartclk = uart_clock;
99 port.regshift = 0;
100 port.iotype = SERIAL_IO_MEM;
101 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
102 port.line = 0;
103
104 if (early_serial_setup(&port) != 0) {
105 printk("Early serial init of port 0 failed\n");
106 }
107
108 port.membase = (void*)ACTING_UART1_IO_BASE;
109 port.irq = ACTING_UART1_INT;
110 port.line = 1;
111
112 if (early_serial_setup(&port) != 0) {
113 printk("Early serial init of port 1 failed\n");
114 }
115}
116
117void __init
118bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
119{
120
121 unsigned int bar_response, bar;
122 /*
123 * Expected PCI mapping:
124 *
125 * PLB addr PCI memory addr
126 * --------------------- ---------------------
127 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
128 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
129 *
130 * PLB addr PCI io addr
131 * --------------------- ---------------------
132 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
133 *
134 * The following code is simplified by assuming that the bootrom
135 * has been well behaved in following this mapping.
136 */
137
138#ifdef DEBUG
139 int i;
140
141 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
142 printk("PCI bridge regs before fixup \n");
143 for (i = 0; i <= 3; i++) {
144 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
145 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
146 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
147 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
148 }
149 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
150 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
151 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
152 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
153
154#endif
155
156 /* added for IBM boot rom version 1.15 bios bar changes -AK */
157
158 /* Disable region first */
159 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
160 /* PLB starting addr, PCI: 0x80000000 */
161 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
162 /* PCI start addr, 0x80000000 */
163 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
164 /* 512MB range of PLB to PCI */
165 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
166 /* Enable no pre-fetch, enable region */
167 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
168 (PPC405_PCI_UPPER_MEM -
169 PPC405_PCI_MEM_BASE)) | 0x01));
170
171 /* Disable region one */
172 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
173 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
174 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
175 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
176 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
177 out_le32((void *) &(pcip->ptm1ms), 0x00000001);
178
179 /* Disable region two */
180 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
181 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
182 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
183 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
184 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
185 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
186 out_le32((void *) &(pcip->ptm2la), 0x00000000);
187
188 /* Zero config bars */
189 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
190 early_write_config_dword(hose, hose->first_busno,
191 PCI_FUNC(hose->first_busno), bar,
192 0x00000000);
193 early_read_config_dword(hose, hose->first_busno,
194 PCI_FUNC(hose->first_busno), bar,
195 &bar_response);
196 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
197 hose->first_busno, PCI_SLOT(hose->first_busno),
198 PCI_FUNC(hose->first_busno), bar, bar_response);
199 }
200 /* end work arround */
201
202#ifdef DEBUG
203 printk("PCI bridge regs after fixup \n");
204 for (i = 0; i <= 3; i++) {
205 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
206 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
207 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
208 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
209 }
210 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
211 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
212 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
213 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
214
215#endif
216}
217
218void __init
219bubinga_setup_arch(void)
220{
221 ppc4xx_setup_arch();
222
223 ibm_ocp_set_emac(0, 1);
224
225 bubinga_early_serial_map();
226
227 /* RTC step for the evb405ep */
228 bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR;
229 TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base,
230 bubinga_rtc_base, 8);
231 /* Identify the system */
232 printk("IBM Bubinga port (MontaVista Software, Inc. <source@mvista.com>)\n");
233}
234
235void __init
236bubinga_map_io(void)
237{
238 ppc4xx_map_io();
239 io_block_mapping(BUBINGA_RTC_VADDR,
240 BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO);
241}
242
243void __init
244platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
245 unsigned long r6, unsigned long r7)
246{
247 ppc4xx_init(r3, r4, r5, r6, r7);
248
249 ppc_md.setup_arch = bubinga_setup_arch;
250 ppc_md.setup_io_mappings = bubinga_map_io;
251
252#ifdef CONFIG_GEN_RTC
253 ppc_md.time_init = todc_time_init;
254 ppc_md.set_rtc_time = todc_set_rtc_time;
255 ppc_md.get_rtc_time = todc_get_rtc_time;
256 ppc_md.nvram_read_val = todc_direct_read_val;
257 ppc_md.nvram_write_val = todc_direct_write_val;
258#endif
259#ifdef CONFIG_KGDB
260 ppc_md.early_serial_map = bubinga_early_serial_map;
261#endif
262}
263
diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h
new file mode 100644
index 000000000000..b1df856f8e22
--- /dev/null
+++ b/arch/ppc/platforms/4xx/bubinga.h
@@ -0,0 +1,69 @@
1/*
2 * Support for IBM PPC 405EP evaluation board (Bubinga).
3 *
4 * Author: SAW (IBM), derived from walnut.h.
5 * Maintained by MontaVista Software <source@mvista.com>
6 *
7 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifdef __KERNEL__
14#ifndef __BUBINGA_H__
15#define __BUBINGA_H__
16
17/* 405EP */
18#include <platforms/4xx/ibm405ep.h>
19
20#ifndef __ASSEMBLY__
21/*
22 * Data structure defining board information maintained by the boot
23 * ROM on IBM's evaluation board. An effort has been made to
24 * keep the field names consistent with the 8xx 'bd_t' board info
25 * structures.
26 */
27
28typedef struct board_info {
29 unsigned char bi_s_version[4]; /* Version of this structure */
30 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
31 unsigned int bi_memsize; /* DRAM installed, in bytes */
32 unsigned char bi_enetaddr[2][6]; /* Local Ethernet MAC address */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
33 unsigned int bi_intfreq; /* Processor speed, in Hz */
34 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
35 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
36 unsigned int bi_opb_busfreq; /* OPB Bus speed, in Hz */
37 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
38} bd_t;
39
40/* Some 4xx parts use a different timebase frequency from the internal clock.
41*/
42#define bi_tbfreq bi_intfreq
43
44
45/* Memory map for the Bubinga board.
46 * Generic 4xx plus RTC.
47 */
48
49extern void *bubinga_rtc_base;
50#define BUBINGA_RTC_PADDR ((uint)0xf0000000)
51#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR
52#define BUBINGA_RTC_SIZE ((uint)8*1024)
53
54/* The UART clock is based off an internal clock -
55 * define BASE_BAUD based on the internal clock and divider(s).
56 * Since BASE_BAUD must be a constant, we will initialize it
57 * using clock/divider values which OpenBIOS initializes
58 * for typical configurations at various CPU speeds.
59 * The base baud is calculated as (FWDA / EXT UART DIV / 16)
60 */
61#define BASE_BAUD 0
62
63#define BUBINGA_FPGA_BASE 0xF0300000
64
65#define PPC4xx_MACHINE_NAME "IBM Bubinga"
66
67#endif /* !__ASSEMBLY__ */
68#endif /* __BUBINGA_H__ */
69#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/cpci405.c b/arch/ppc/platforms/4xx/cpci405.c
new file mode 100644
index 000000000000..ff966773a0bf
--- /dev/null
+++ b/arch/ppc/platforms/4xx/cpci405.c
@@ -0,0 +1,84 @@
1/*
2 * arch/ppc/platforms/cpci405.c
3 *
4 * Board setup routines for the esd CPCI-405 cPCI Board.
5 *
6 * Author: Stefan Roese
7 * stefan.roese@esd-electronics.com
8 *
9 * Copyright 2001 esd electronic system design - hannover germany
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#include <linux/config.h>
19#include <linux/init.h>
20#include <linux/pci.h>
21#include <asm/system.h>
22#include <asm/pci-bridge.h>
23#include <asm/machdep.h>
24#include <asm/todc.h>
25#include <asm/ocp.h>
26
27void *cpci405_nvram;
28
29/*
30 * Some IRQs unique to CPCI-405.
31 */
32int __init
33ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
34{
35 static char pci_irq_table[][4] =
36 /*
37 * PCI IDSEL/INTPIN->INTLINE
38 * A B C D
39 */
40 {
41 {28, 28, 28, 28}, /* IDSEL 15 - cPCI slot 8 */
42 {29, 29, 29, 29}, /* IDSEL 16 - cPCI slot 7 */
43 {30, 30, 30, 30}, /* IDSEL 17 - cPCI slot 6 */
44 {27, 27, 27, 27}, /* IDSEL 18 - cPCI slot 5 */
45 {28, 28, 28, 28}, /* IDSEL 19 - cPCI slot 4 */
46 {29, 29, 29, 29}, /* IDSEL 20 - cPCI slot 3 */
47 {30, 30, 30, 30}, /* IDSEL 21 - cPCI slot 2 */
48 };
49 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
50 return PCI_IRQ_TABLE_LOOKUP;
51};
52
53void __init
54cpci405_setup_arch(void)
55{
56 ppc4xx_setup_arch();
57
58 ibm_ocp_set_emac(0, 0);
59
60 TODC_INIT(TODC_TYPE_MK48T35, cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
61}
62
63void __init
64cpci405_map_io(void)
65{
66 ppc4xx_map_io();
67 cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
68}
69
70void __init
71platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
72 unsigned long r6, unsigned long r7)
73{
74 ppc4xx_init(r3, r4, r5, r6, r7);
75
76 ppc_md.setup_arch = cpci405_setup_arch;
77 ppc_md.setup_io_mappings = cpci405_map_io;
78
79 ppc_md.time_init = todc_time_init;
80 ppc_md.set_rtc_time = todc_set_rtc_time;
81 ppc_md.get_rtc_time = todc_get_rtc_time;
82 ppc_md.nvram_read_val = todc_direct_read_val;
83 ppc_md.nvram_write_val = todc_direct_write_val;
84}
diff --git a/arch/ppc/platforms/4xx/cpci405.h b/arch/ppc/platforms/4xx/cpci405.h
new file mode 100644
index 000000000000..e27f7cb650d8
--- /dev/null
+++ b/arch/ppc/platforms/4xx/cpci405.h
@@ -0,0 +1,37 @@
1/*
2 * CPCI-405 board specific definitions
3 *
4 * Copyright (c) 2001 Stefan Roese (stefan.roese@esd-electronics.com)
5 */
6
7#ifdef __KERNEL__
8#ifndef __ASM_CPCI405_H__
9#define __ASM_CPCI405_H__
10
11#include <linux/config.h>
12
13/* We have a 405GP core */
14#include <platforms/4xx/ibm405gp.h>
15
16#include <asm/ppcboot.h>
17
18#ifndef __ASSEMBLY__
19/* Some 4xx parts use a different timebase frequency from the internal clock.
20*/
21#define bi_tbfreq bi_intfreq
22
23/* Map for the NVRAM space */
24#define CPCI405_NVRAM_PADDR ((uint)0xf0200000)
25#define CPCI405_NVRAM_SIZE ((uint)32*1024)
26
27#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
28#define BASE_BAUD 201600
29#else
30#define BASE_BAUD 691200
31#endif
32
33#define PPC4xx_MACHINE_NAME "esd CPCI-405"
34
35#endif /* !__ASSEMBLY__ */
36#endif /* __ASM_CPCI405_H__ */
37#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
new file mode 100644
index 000000000000..f63bca83e757
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ebony.c
@@ -0,0 +1,356 @@
1/*
2 * arch/ppc/platforms/4xx/ebony.c
3 *
4 * Ebony board specific routines
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 * Copyright 2002-2005 MontaVista Software Inc.
8 *
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/config.h>
19#include <linux/stddef.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/reboot.h>
24#include <linux/pci.h>
25#include <linux/kdev_t.h>
26#include <linux/types.h>
27#include <linux/major.h>
28#include <linux/blkdev.h>
29#include <linux/console.h>
30#include <linux/delay.h>
31#include <linux/ide.h>
32#include <linux/initrd.h>
33#include <linux/irq.h>
34#include <linux/seq_file.h>
35#include <linux/root_dev.h>
36#include <linux/tty.h>
37#include <linux/serial.h>
38#include <linux/serial_core.h>
39
40#include <asm/system.h>
41#include <asm/pgtable.h>
42#include <asm/page.h>
43#include <asm/dma.h>
44#include <asm/io.h>
45#include <asm/machdep.h>
46#include <asm/ocp.h>
47#include <asm/pci-bridge.h>
48#include <asm/time.h>
49#include <asm/todc.h>
50#include <asm/bootinfo.h>
51#include <asm/ppc4xx_pic.h>
52#include <asm/ppcboot.h>
53
54#include <syslib/gen550.h>
55#include <syslib/ibm440gp_common.h>
56
57/*
58 * This is a horrible kludge, we eventually need to abstract this
59 * generic PHY stuff, so the standard phy mode defines can be
60 * easily used from arch code.
61 */
62#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
63
64bd_t __res;
65
66static struct ibm44x_clocks clocks __initdata;
67
68/*
69 * Ebony external IRQ triggering/polarity settings
70 */
71unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */
77 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */
85};
86
87static void __init
88ebony_calibrate_decr(void)
89{
90 unsigned int freq;
91
92 /*
93 * Determine system clock speed
94 *
95 * If we are on Rev. B silicon, then use
96 * default external system clock. If we are
97 * on Rev. C silicon then errata forces us to
98 * use the internal clock.
99 */
100 switch (PVR_REV(mfspr(SPRN_PVR))) {
101 case PVR_REV(PVR_440GP_RB):
102 freq = EBONY_440GP_RB_SYSCLK;
103 break;
104 case PVR_REV(PVR_440GP_RC1):
105 default:
106 freq = EBONY_440GP_RC_SYSCLK;
107 break;
108 }
109
110 ibm44x_calibrate_decr(freq);
111}
112
113static int
114ebony_show_cpuinfo(struct seq_file *m)
115{
116 seq_printf(m, "vendor\t\t: IBM\n");
117 seq_printf(m, "machine\t\t: Ebony\n");
118
119 return 0;
120}
121
122static inline int
123ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
124{
125 static char pci_irq_table[][4] =
126 /*
127 * PCI IDSEL/INTPIN->INTLINE
128 * A B C D
129 */
130 {
131 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
132 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
133 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
134 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
135 };
136
137 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
138 return PCI_IRQ_TABLE_LOOKUP;
139}
140
141#define PCIX_WRITEL(value, offset) \
142 (writel(value, pcix_reg_base + offset))
143
144/*
145 * FIXME: This is only here to "make it work". This will move
146 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
147 * configuration library. -Matt
148 */
149static void __init
150ebony_setup_pcix(void)
151{
152 void *pcix_reg_base;
153
154 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
155
156 /* Disable all windows */
157 PCIX_WRITEL(0, PCIX0_POM0SA);
158 PCIX_WRITEL(0, PCIX0_POM1SA);
159 PCIX_WRITEL(0, PCIX0_POM2SA);
160 PCIX_WRITEL(0, PCIX0_PIM0SA);
161 PCIX_WRITEL(0, PCIX0_PIM1SA);
162 PCIX_WRITEL(0, PCIX0_PIM2SA);
163
164 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
165 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
166 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
167 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
168 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
169 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
170
171 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
172 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
173 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
174 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
175
176 eieio();
177}
178
179static void __init
180ebony_setup_hose(void)
181{
182 struct pci_controller *hose;
183
184 /* Configure windows on the PCI-X host bridge */
185 ebony_setup_pcix();
186
187 hose = pcibios_alloc_controller();
188
189 if (!hose)
190 return;
191
192 hose->first_busno = 0;
193 hose->last_busno = 0xff;
194
195 hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
196
197 pci_init_resource(&hose->io_resource,
198 EBONY_PCI_LOWER_IO,
199 EBONY_PCI_UPPER_IO,
200 IORESOURCE_IO,
201 "PCI host bridge");
202
203 pci_init_resource(&hose->mem_resources[0],
204 EBONY_PCI_LOWER_MEM,
205 EBONY_PCI_UPPER_MEM,
206 IORESOURCE_MEM,
207 "PCI host bridge");
208
209 hose->io_space.start = EBONY_PCI_LOWER_IO;
210 hose->io_space.end = EBONY_PCI_UPPER_IO;
211 hose->mem_space.start = EBONY_PCI_LOWER_MEM;
212 hose->mem_space.end = EBONY_PCI_UPPER_MEM;
213 isa_io_base =
214 (unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
215 hose->io_base_virt = (void *)isa_io_base;
216
217 setup_indirect_pci(hose,
218 EBONY_PCI_CFGA_PLB32,
219 EBONY_PCI_CFGD_PLB32);
220 hose->set_cfg_type = 1;
221
222 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
223
224 ppc_md.pci_swizzle = common_swizzle;
225 ppc_md.pci_map_irq = ebony_map_irq;
226}
227
228TODC_ALLOC();
229
230static void __init
231ebony_early_serial_map(void)
232{
233 struct uart_port port;
234
235 /* Setup ioremapped serial port access */
236 memset(&port, 0, sizeof(port));
237 port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
238 port.irq = 0;
239 port.uartclk = clocks.uart0;
240 port.regshift = 0;
241 port.iotype = SERIAL_IO_MEM;
242 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
243 port.line = 0;
244
245 if (early_serial_setup(&port) != 0) {
246 printk("Early serial init of port 0 failed\n");
247 }
248
249#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
250 /* Configure debug serial access */
251 gen550_init(0, &port);
252#endif
253
254 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
255 port.irq = 1;
256 port.uartclk = clocks.uart1;
257 port.line = 1;
258
259 if (early_serial_setup(&port) != 0) {
260 printk("Early serial init of port 1 failed\n");
261 }
262
263#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
264 /* Configure debug serial access */
265 gen550_init(1, &port);
266#endif
267}
268
269static void __init
270ebony_setup_arch(void)
271{
272 struct ocp_def *def;
273 struct ocp_func_emac_data *emacdata;
274
275 /* Set mac_addr for each EMAC */
276 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
277 emacdata = def->additions;
278 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
279 emacdata->phy_mode = PHY_MODE_RMII;
280 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
281
282 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
283 emacdata = def->additions;
284 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
285 emacdata->phy_mode = PHY_MODE_RMII;
286 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
287
288 /*
289 * Determine various clocks.
290 * To be completely correct we should get SysClk
291 * from FPGA, because it can be changed by on-board switches
292 * --ebs
293 */
294 ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
295 ocp_sys_info.opb_bus_freq = clocks.opb;
296
297 /* Setup TODC access */
298 TODC_INIT(TODC_TYPE_DS1743,
299 0,
300 0,
301 ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
302 8);
303
304 /* init to some ~sane value until calibrate_delay() runs */
305 loops_per_jiffy = 50000000/HZ;
306
307 /* Setup PCI host bridge */
308 ebony_setup_hose();
309
310#ifdef CONFIG_BLK_DEV_INITRD
311 if (initrd_start)
312 ROOT_DEV = Root_RAM0;
313 else
314#endif
315#ifdef CONFIG_ROOT_NFS
316 ROOT_DEV = Root_NFS;
317#else
318 ROOT_DEV = Root_HDA1;
319#endif
320
321 ebony_early_serial_map();
322
323 /* Identify the system */
324 printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
325}
326
327void __init platform_init(unsigned long r3, unsigned long r4,
328 unsigned long r5, unsigned long r6, unsigned long r7)
329{
330 parse_bootinfo(find_bootinfo());
331
332 /*
333 * If we were passed in a board information, copy it into the
334 * residual data area.
335 */
336 if (r3)
337 __res = *(bd_t *)(r3 + KERNELBASE);
338
339 ibm44x_platform_init();
340
341 ppc_md.setup_arch = ebony_setup_arch;
342 ppc_md.show_cpuinfo = ebony_show_cpuinfo;
343 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
344
345 ppc_md.calibrate_decr = ebony_calibrate_decr;
346 ppc_md.time_init = todc_time_init;
347 ppc_md.set_rtc_time = todc_set_rtc_time;
348 ppc_md.get_rtc_time = todc_get_rtc_time;
349
350 ppc_md.nvram_read_val = todc_direct_read_val;
351 ppc_md.nvram_write_val = todc_direct_write_val;
352#ifdef CONFIG_KGDB
353 ppc_md.early_serial_map = ebony_early_serial_map;
354#endif
355}
356
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
new file mode 100644
index 000000000000..47c391c9174d
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ebony.h
@@ -0,0 +1,91 @@
1/*
2 * arch/ppc/platforms/ebony.h
3 *
4 * Ebony board definitions
5 *
6 * Matt Porter <mporter@mvista.com>
7 *
8 * Copyright 2002 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_EBONY_H__
18#define __ASM_EBONY_H__
19
20#include <linux/config.h>
21#include <platforms/4xx/ibm440gp.h>
22
23/* F/W TLB mapping used in bootloader glue to reset EMAC */
24#define PPC44x_EMAC0_MR0 0xE0000800
25
26/* Where to find the MAC info */
27#define EBONY_OPENBIOS_MAC_BASE 0xfffffe0c
28#define EBONY_OPENBIOS_MAC_OFFSET 0x0c
29
30/* Default clock rates for Rev. B and Rev. C silicon */
31#define EBONY_440GP_RB_SYSCLK 33000000
32#define EBONY_440GP_RC_SYSCLK 400000000
33
34/* RTC/NVRAM location */
35#define EBONY_RTC_ADDR 0x0000000148000000ULL
36#define EBONY_RTC_SIZE 0x2000
37
38/* Flash */
39#define EBONY_FPGA_ADDR 0x0000000148300000ULL
40#define EBONY_BOOT_SMALL_FLASH(x) (x & 0x20)
41#define EBONY_ONBRD_FLASH_EN(x) (x & 0x02)
42#define EBONY_FLASH_SEL(x) (x & 0x01)
43#define EBONY_SMALL_FLASH_LOW1 0x00000001ff800000ULL
44#define EBONY_SMALL_FLASH_LOW2 0x00000001ff880000ULL
45#define EBONY_SMALL_FLASH_HIGH1 0x00000001fff00000ULL
46#define EBONY_SMALL_FLASH_HIGH2 0x00000001fff80000ULL
47#define EBONY_SMALL_FLASH_SIZE 0x80000
48#define EBONY_LARGE_FLASH_LOW 0x00000001ff800000ULL
49#define EBONY_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
50#define EBONY_LARGE_FLASH_SIZE 0x400000
51
52#define EBONY_SMALL_FLASH_BASE 0x00000001fff80000ULL
53#define EBONY_LARGE_FLASH_BASE 0x00000001ff800000ULL
54
55/*
56 * Serial port defines
57 */
58
59/* OpenBIOS defined UART mappings, used before early_serial_setup */
60#define UART0_IO_BASE 0xE0000200
61#define UART1_IO_BASE 0xE0000300
62
63/* external Epson SG-615P */
64#define BASE_BAUD 691200
65
66#define STD_UART_OP(num) \
67 { 0, BASE_BAUD, 0, UART##num##_INT, \
68 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
69 iomem_base: UART##num##_IO_BASE, \
70 io_type: SERIAL_IO_MEM},
71
72#define SERIAL_PORT_DFNS \
73 STD_UART_OP(0) \
74 STD_UART_OP(1)
75
76/* PCI support */
77#define EBONY_PCI_LOWER_IO 0x00000000
78#define EBONY_PCI_UPPER_IO 0x0000ffff
79#define EBONY_PCI_LOWER_MEM 0x80002000
80#define EBONY_PCI_UPPER_MEM 0xffffefff
81
82#define EBONY_PCI_CFGREGS_BASE 0x000000020ec00000
83#define EBONY_PCI_CFGA_PLB32 0x0ec00000
84#define EBONY_PCI_CFGD_PLB32 0x0ec00004
85
86#define EBONY_PCI_IO_BASE 0x0000000208000000ULL
87#define EBONY_PCI_IO_SIZE 0x00010000
88#define EBONY_PCI_MEM_OFFSET 0x00000000
89
90#endif /* __ASM_EBONY_H__ */
91#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ep405.c b/arch/ppc/platforms/4xx/ep405.c
new file mode 100644
index 000000000000..26a07cdb30ec
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ep405.c
@@ -0,0 +1,197 @@
1/*
2 * arch/ppc/platforms/4xx/ep405.c
3 *
4 * Embedded Planet 405GP board
5 * http://www.embeddedplanet.com
6 *
7 * Author: Matthew Locke <mlocke@mvista.com>
8 *
9 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <asm/system.h>
18#include <asm/pci-bridge.h>
19#include <asm/machdep.h>
20#include <asm/todc.h>
21#include <asm/ocp.h>
22#include <asm/ibm_ocp_pci.h>
23
24#undef DEBUG
25#ifdef DEBUG
26#define DBG(x...) printk(x)
27#else
28#define DBG(x...)
29#endif
30
31u8 *ep405_bcsr;
32u8 *ep405_nvram;
33
34static struct {
35 u8 cpld_xirq_select;
36 int pci_idsel;
37 int irq;
38} ep405_devtable[] = {
39#ifdef CONFIG_EP405PC
40 {0x07, 0x0E, 25}, /* EP405PC: USB */
41#endif
42};
43
44int __init
45ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
46{
47 int i;
48
49 /* AFAICT this is only called a few times during PCI setup, so
50 performance is not critical */
51 for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
52 if (idsel == ep405_devtable[i].pci_idsel)
53 return ep405_devtable[i].irq;
54 }
55 return -1;
56};
57
58void __init
59ep405_setup_arch(void)
60{
61 ppc4xx_setup_arch();
62
63 ibm_ocp_set_emac(0, 0);
64
65 if (__res.bi_nvramsize == 512*1024) {
66 /* FIXME: we should properly handle NVRTCs of different sizes */
67 TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
68 }
69}
70
71void __init
72bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
73{
74 unsigned int bar_response, bar;
75 /*
76 * Expected PCI mapping:
77 *
78 * PLB addr PCI memory addr
79 * --------------------- ---------------------
80 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
81 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
82 *
83 * PLB addr PCI io addr
84 * --------------------- ---------------------
85 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
86 *
87 */
88
89 /* Disable region zero first */
90 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
91 /* PLB starting addr, PCI: 0x80000000 */
92 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
93 /* PCI start addr, 0x80000000 */
94 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
95 /* 512MB range of PLB to PCI */
96 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
97 /* Enable no pre-fetch, enable region */
98 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
99 (PPC405_PCI_UPPER_MEM -
100 PPC405_PCI_MEM_BASE)) | 0x01));
101
102 /* Disable region one */
103 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
104 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
105 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
106 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
107 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
108 out_le32((void *) &(pcip->ptm1ms), 0x00000000);
109
110 /* Disable region two */
111 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
112 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
113 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
114 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
115 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
116 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
117
118 /* Configure PTM (PCI->PLB) region 1 */
119 out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
120 /* Disable PTM region 2 */
121 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
122
123 /* Zero config bars */
124 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
125 early_write_config_dword(hose, hose->first_busno,
126 PCI_FUNC(hose->first_busno), bar,
127 0x00000000);
128 early_read_config_dword(hose, hose->first_busno,
129 PCI_FUNC(hose->first_busno), bar,
130 &bar_response);
131 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
132 hose->first_busno, PCI_SLOT(hose->first_busno),
133 PCI_FUNC(hose->first_busno), bar, bar_response);
134 }
135 /* end work arround */
136}
137
138void __init
139ep405_map_io(void)
140{
141 bd_t *bip = &__res;
142
143 ppc4xx_map_io();
144
145 ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
146
147 if (bip->bi_nvramsize > 0) {
148 ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize);
149 }
150}
151
152void __init
153ep405_init_IRQ(void)
154{
155 int i;
156
157 ppc4xx_init_IRQ();
158
159 /* Workaround for a bug in the firmware it incorrectly sets
160 the IRQ polarities for XIRQ0 and XIRQ1 */
161 mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
162 mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
163
164 /* Activate the XIRQs from the CPLD */
165 writeb(0xf0, ep405_bcsr+10);
166
167 /* Set up IRQ routing */
168 for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
169 if ( (ep405_devtable[i].irq >= 25)
170 && (ep405_devtable[i].irq) <= 31) {
171 writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
172 writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6);
173 }
174 }
175}
176
177void __init
178platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
179 unsigned long r6, unsigned long r7)
180{
181 ppc4xx_init(r3, r4, r5, r6, r7);
182
183 ppc_md.setup_arch = ep405_setup_arch;
184 ppc_md.setup_io_mappings = ep405_map_io;
185 ppc_md.init_IRQ = ep405_init_IRQ;
186
187 ppc_md.nvram_read_val = todc_direct_read_val;
188 ppc_md.nvram_write_val = todc_direct_write_val;
189
190 if (__res.bi_nvramsize == 512*1024) {
191 ppc_md.time_init = todc_time_init;
192 ppc_md.set_rtc_time = todc_set_rtc_time;
193 ppc_md.get_rtc_time = todc_get_rtc_time;
194 } else {
195 printk("EP405: NVRTC size is not 512k (not a DS1557). Not sure what to do with it\n");
196 }
197}
diff --git a/arch/ppc/platforms/4xx/ep405.h b/arch/ppc/platforms/4xx/ep405.h
new file mode 100644
index 000000000000..ea3eb21338fb
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ep405.h
@@ -0,0 +1,54 @@
1/*
2 * arch/ppc/platforms/4xx/ep405.h
3 *
4 * Embedded Planet 405GP board
5 * http://www.embeddedplanet.com
6 *
7 * Author: Matthew Locke <mlocke@mvista.com>
8 *
9 * 2000 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_EP405_H__
17#define __ASM_EP405_H__
18
19/* We have a 405GP core */
20#include <platforms/4xx/ibm405gp.h>
21
22#ifndef __ASSEMBLY__
23
24#include <linux/types.h>
25
26typedef struct board_info {
27 unsigned int bi_memsize; /* DRAM installed, in bytes */
28 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
29 unsigned int bi_intfreq; /* Processor speed, in Hz */
30 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
31 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
32 unsigned int bi_nvramsize; /* Size of the NVRAM/RTC */
33} bd_t;
34
35/* Some 4xx parts use a different timebase frequency from the internal clock.
36*/
37#define bi_tbfreq bi_intfreq
38
39extern u8 *ep405_bcsr;
40extern u8 *ep405_nvram;
41
42/* Map for the BCSR and NVRAM space */
43#define EP405_BCSR_PADDR ((uint)0xf4000000)
44#define EP405_BCSR_SIZE ((uint)16)
45#define EP405_NVRAM_PADDR ((uint)0xf4200000)
46
47/* serial defines */
48#define BASE_BAUD 399193
49
50#define PPC4xx_MACHINE_NAME "Embedded Planet 405GP"
51
52#endif /* !__ASSEMBLY__ */
53#endif /* __ASM_EP405_H__ */
54#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c
new file mode 100644
index 000000000000..6d44567f4dd2
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm405ep.c
@@ -0,0 +1,143 @@
1/*
2 * arch/ppc/platforms/ibm405ep.c
3 *
4 * Support for IBM PPC 405EP processors.
5 *
6 * Author: SAW (IBM), derived from ibmnp405l.c.
7 * Maintained by MontaVista Software <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#include <linux/config.h>
16#include <linux/init.h>
17#include <linux/smp.h>
18#include <linux/threads.h>
19#include <linux/param.h>
20#include <linux/string.h>
21
22#include <asm/ibm4xx.h>
23#include <asm/ocp.h>
24#include <asm/ppc4xx_pic.h>
25
26#include <platforms/4xx/ibm405ep.h>
27
28static struct ocp_func_mal_data ibm405ep_mal0_def = {
29 .num_tx_chans = 4, /* Number of TX channels */
30 .num_rx_chans = 2, /* Number of RX channels */
31 .txeob_irq = 11, /* TX End Of Buffer IRQ */
32 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
33 .txde_irq = 13, /* TX Descriptor Error IRQ */
34 .rxde_irq = 14, /* RX Descriptor Error IRQ */
35 .serr_irq = 10, /* MAL System Error IRQ */
36};
37OCP_SYSFS_MAL_DATA()
38
39static struct ocp_func_emac_data ibm405ep_emac0_def = {
40 .rgmii_idx = -1, /* No RGMII */
41 .rgmii_mux = -1, /* No RGMII */
42 .zmii_idx = -1, /* ZMII device index */
43 .zmii_mux = 0, /* ZMII input of this EMAC */
44 .mal_idx = 0, /* MAL device index */
45 .mal_rx_chan = 0, /* MAL rx channel number */
46 .mal_tx_chan = 0, /* MAL tx channel number */
47 .wol_irq = 9, /* WOL interrupt number */
48 .mdio_idx = 0, /* MDIO via EMAC0 */
49 .tah_idx = -1, /* No TAH */
50};
51
52static struct ocp_func_emac_data ibm405ep_emac1_def = {
53 .rgmii_idx = -1, /* No RGMII */
54 .rgmii_mux = -1, /* No RGMII */
55 .zmii_idx = -1, /* ZMII device index */
56 .zmii_mux = 0, /* ZMII input of this EMAC */
57 .mal_idx = 0, /* MAL device index */
58 .mal_rx_chan = 1, /* MAL rx channel number */
59 .mal_tx_chan = 2, /* MAL tx channel number */
60 .wol_irq = 9, /* WOL interrupt number */
61 .mdio_idx = 0, /* MDIO via EMAC0 */
62 .tah_idx = -1, /* No TAH */
63};
64OCP_SYSFS_EMAC_DATA()
65
66static struct ocp_func_iic_data ibm405ep_iic0_def = {
67 .fast_mode = 0, /* Use standad mode (100Khz) */
68};
69OCP_SYSFS_IIC_DATA()
70
71struct ocp_def core_ocp[] = {
72 { .vendor = OCP_VENDOR_IBM,
73 .function = OCP_FUNC_OPB,
74 .index = 0,
75 .paddr = 0xEF600000,
76 .irq = OCP_IRQ_NA,
77 .pm = OCP_CPM_NA,
78 },
79 { .vendor = OCP_VENDOR_IBM,
80 .function = OCP_FUNC_16550,
81 .index = 0,
82 .paddr = UART0_IO_BASE,
83 .irq = UART0_INT,
84 .pm = IBM_CPM_UART0
85 },
86 { .vendor = OCP_VENDOR_IBM,
87 .function = OCP_FUNC_16550,
88 .index = 1,
89 .paddr = UART1_IO_BASE,
90 .irq = UART1_INT,
91 .pm = IBM_CPM_UART1
92 },
93 { .vendor = OCP_VENDOR_IBM,
94 .function = OCP_FUNC_IIC,
95 .paddr = 0xEF600500,
96 .irq = 2,
97 .pm = IBM_CPM_IIC0,
98 .additions = &ibm405ep_iic0_def,
99 .show = &ocp_show_iic_data
100 },
101 { .vendor = OCP_VENDOR_IBM,
102 .function = OCP_FUNC_GPIO,
103 .paddr = 0xEF600700,
104 .irq = OCP_IRQ_NA,
105 .pm = IBM_CPM_GPIO0
106 },
107 { .vendor = OCP_VENDOR_IBM,
108 .function = OCP_FUNC_MAL,
109 .paddr = OCP_PADDR_NA,
110 .irq = OCP_IRQ_NA,
111 .pm = OCP_CPM_NA,
112 .additions = &ibm405ep_mal0_def,
113 .show = &ocp_show_mal_data
114 },
115 { .vendor = OCP_VENDOR_IBM,
116 .function = OCP_FUNC_EMAC,
117 .index = 0,
118 .paddr = EMAC0_BASE,
119 .irq = 15,
120 .pm = OCP_CPM_NA,
121 .additions = &ibm405ep_emac0_def,
122 .show = &ocp_show_emac_data
123 },
124 { .vendor = OCP_VENDOR_IBM,
125 .function = OCP_FUNC_EMAC,
126 .index = 1,
127 .paddr = 0xEF600900,
128 .irq = 17,
129 .pm = OCP_CPM_NA,
130 .additions = &ibm405ep_emac1_def,
131 .show = &ocp_show_emac_data
132 },
133 { .vendor = OCP_VENDOR_INVALID
134 }
135};
136
137/* Polarity and triggering settings for internal interrupt sources */
138struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
139 { .polarity = 0xffff7f80,
140 .triggering = 0x00000000,
141 .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
142 }
143};
diff --git a/arch/ppc/platforms/4xx/ibm405ep.h b/arch/ppc/platforms/4xx/ibm405ep.h
new file mode 100644
index 000000000000..e051e3fe8c63
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm405ep.h
@@ -0,0 +1,148 @@
1/*
2 * arch/ppc/platforms/4xx/ibm405ep.h
3 *
4 * IBM PPC 405EP processor defines.
5 *
6 * Author: SAW (IBM), derived from ibm405gp.h.
7 * Maintained by MontaVista Software <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Softare Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_IBM405EP_H__
17#define __ASM_IBM405EP_H__
18
19#include <linux/config.h>
20
21/* ibm405.h at bottom of this file */
22
23/* PCI
24 * PCI Bridge config reg definitions
25 * see 17-19 of manual
26 */
27
28#define PPC405_PCI_CONFIG_ADDR 0xeec00000
29#define PPC405_PCI_CONFIG_DATA 0xeec00004
30
31#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
32 /* setbat */
33#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
34#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
35#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
36
37#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
38#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
39#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
40#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
41
42#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
43
44#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
45#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
46#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
47#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
48#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
49#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
50#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
51#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
52#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
53#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
54#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
55#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
56
57/* serial port defines */
58#define RS_TABLE_SIZE 2
59
60#define UART0_INT 0
61#define UART1_INT 1
62
63#define PCIL0_BASE 0xEF400000
64#define UART0_IO_BASE 0xEF600300
65#define UART1_IO_BASE 0xEF600400
66#define EMAC0_BASE 0xEF600800
67
68#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
69
70#if defined(CONFIG_UART0_TTYS0)
71#define ACTING_UART0_IO_BASE UART0_IO_BASE
72#define ACTING_UART1_IO_BASE UART1_IO_BASE
73#define ACTING_UART0_INT UART0_INT
74#define ACTING_UART1_INT UART1_INT
75#else
76#define ACTING_UART0_IO_BASE UART1_IO_BASE
77#define ACTING_UART1_IO_BASE UART0_IO_BASE
78#define ACTING_UART0_INT UART1_INT
79#define ACTING_UART1_INT UART0_INT
80#endif
81
82#define STD_UART_OP(num) \
83 { 0, BASE_BAUD, 0, ACTING_UART##num##_INT, \
84 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
85 iomem_base: (u8 *)ACTING_UART##num##_IO_BASE, \
86 io_type: SERIAL_IO_MEM},
87
88#define SERIAL_DEBUG_IO_BASE ACTING_UART0_IO_BASE
89#define SERIAL_PORT_DFNS \
90 STD_UART_OP(0) \
91 STD_UART_OP(1)
92
93/* DCR defines */
94#define DCRN_CPMSR_BASE 0x0BA
95#define DCRN_CPMFR_BASE 0x0B9
96
97#define DCRN_CPC0_PLLMR0_BASE 0x0F0
98#define DCRN_CPC0_BOOT_BASE 0x0F1
99#define DCRN_CPC0_CR1_BASE 0x0F2
100#define DCRN_CPC0_EPRCSR_BASE 0x0F3
101#define DCRN_CPC0_PLLMR1_BASE 0x0F4
102#define DCRN_CPC0_UCR_BASE 0x0F5
103#define DCRN_CPC0_UCR_U0DIV 0x07F
104#define DCRN_CPC0_SRR_BASE 0x0F6
105#define DCRN_CPC0_JTAGID_BASE 0x0F7
106#define DCRN_CPC0_SPARE_BASE 0x0F8
107#define DCRN_CPC0_PCI_BASE 0x0F9
108
109
110#define IBM_CPM_GPT 0x80000000 /* GPT interface */
111#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
112#define IBM_CPM_UIC 0x00010000 /* Universal Int Controller */
113#define IBM_CPM_CPU 0x00008000 /* processor core */
114#define IBM_CPM_EBC 0x00002000 /* EBC controller */
115#define IBM_CPM_SDRAM0 0x00004000 /* SDRAM memory controller */
116#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO */
117#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
118#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
119#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
120#define IBM_CPM_DMA 0x00000040 /* DMA controller */
121#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
122#define IBM_CPM_UART1 0x00000002 /* serial port 0 */
123#define IBM_CPM_UART0 0x00000001 /* serial port 1 */
124#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
125 | IBM_CPM_OPB | IBM_CPM_EBC \
126 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
127 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
128#define DCRN_DMA0_BASE 0x100
129#define DCRN_DMA1_BASE 0x108
130#define DCRN_DMA2_BASE 0x110
131#define DCRN_DMA3_BASE 0x118
132#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
133#define DCRN_DMASR_BASE 0x120
134#define DCRN_EBC_BASE 0x012
135#define DCRN_DCP0_BASE 0x014
136#define DCRN_MAL_BASE 0x180
137#define DCRN_OCM0_BASE 0x018
138#define DCRN_PLB0_BASE 0x084
139#define DCRN_PLLMR_BASE 0x0B0
140#define DCRN_POB0_BASE 0x0A0
141#define DCRN_SDRAM0_BASE 0x010
142#define DCRN_UIC0_BASE 0x0C0
143#define UIC0 DCRN_UIC0_BASE
144
145#include <asm/ibm405.h>
146
147#endif /* __ASM_IBM405EP_H__ */
148#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405gp.c b/arch/ppc/platforms/4xx/ibm405gp.c
new file mode 100644
index 000000000000..dfd7ef3ba5f8
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm405gp.c
@@ -0,0 +1,120 @@
1/*
2 *
3 * Copyright 2000-2001 MontaVista Software Inc.
4 * Original author: Armin Kuster akuster@mvista.com
5 *
6 * Module name: ibm405gp.c
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/config.h>
17#include <linux/init.h>
18#include <linux/smp.h>
19#include <linux/threads.h>
20#include <linux/param.h>
21#include <linux/string.h>
22#include <platforms/4xx/ibm405gp.h>
23#include <asm/ibm4xx.h>
24#include <asm/ocp.h>
25#include <asm/ppc4xx_pic.h>
26
27static struct ocp_func_emac_data ibm405gp_emac0_def = {
28 .rgmii_idx = -1, /* No RGMII */
29 .rgmii_mux = -1, /* No RGMII */
30 .zmii_idx = -1, /* ZMII device index */
31 .zmii_mux = 0, /* ZMII input of this EMAC */
32 .mal_idx = 0, /* MAL device index */
33 .mal_rx_chan = 0, /* MAL rx channel number */
34 .mal_tx_chan = 0, /* MAL tx channel number */
35 .wol_irq = 9, /* WOL interrupt number */
36 .mdio_idx = -1, /* No shared MDIO */
37 .tah_idx = -1, /* No TAH */
38};
39OCP_SYSFS_EMAC_DATA()
40
41static struct ocp_func_mal_data ibm405gp_mal0_def = {
42 .num_tx_chans = 1, /* Number of TX channels */
43 .num_rx_chans = 1, /* Number of RX channels */
44 .txeob_irq = 11, /* TX End Of Buffer IRQ */
45 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
46 .txde_irq = 13, /* TX Descriptor Error IRQ */
47 .rxde_irq = 14, /* RX Descriptor Error IRQ */
48 .serr_irq = 10, /* MAL System Error IRQ */
49};
50OCP_SYSFS_MAL_DATA()
51
52static struct ocp_func_iic_data ibm405gp_iic0_def = {
53 .fast_mode = 0, /* Use standad mode (100Khz) */
54};
55OCP_SYSFS_IIC_DATA()
56
57struct ocp_def core_ocp[] = {
58 { .vendor = OCP_VENDOR_IBM,
59 .function = OCP_FUNC_OPB,
60 .index = 0,
61 .paddr = 0xEF600000,
62 .irq = OCP_IRQ_NA,
63 .pm = OCP_CPM_NA,
64 },
65 { .vendor = OCP_VENDOR_IBM,
66 .function = OCP_FUNC_16550,
67 .index = 0,
68 .paddr = UART0_IO_BASE,
69 .irq = UART0_INT,
70 .pm = IBM_CPM_UART0
71 },
72 { .vendor = OCP_VENDOR_IBM,
73 .function = OCP_FUNC_16550,
74 .index = 1,
75 .paddr = UART1_IO_BASE,
76 .irq = UART1_INT,
77 .pm = IBM_CPM_UART1
78 },
79 { .vendor = OCP_VENDOR_IBM,
80 .function = OCP_FUNC_IIC,
81 .paddr = 0xEF600500,
82 .irq = 2,
83 .pm = IBM_CPM_IIC0,
84 .additions = &ibm405gp_iic0_def,
85 .show = &ocp_show_iic_data,
86 },
87 { .vendor = OCP_VENDOR_IBM,
88 .function = OCP_FUNC_GPIO,
89 .paddr = 0xEF600700,
90 .irq = OCP_IRQ_NA,
91 .pm = IBM_CPM_GPIO0
92 },
93 { .vendor = OCP_VENDOR_IBM,
94 .function = OCP_FUNC_MAL,
95 .paddr = OCP_PADDR_NA,
96 .irq = OCP_IRQ_NA,
97 .pm = OCP_CPM_NA,
98 .additions = &ibm405gp_mal0_def,
99 .show = &ocp_show_mal_data,
100 },
101 { .vendor = OCP_VENDOR_IBM,
102 .function = OCP_FUNC_EMAC,
103 .index = 0,
104 .paddr = EMAC0_BASE,
105 .irq = 15,
106 .pm = IBM_CPM_EMAC0,
107 .additions = &ibm405gp_emac0_def,
108 .show = &ocp_show_emac_data,
109 },
110 { .vendor = OCP_VENDOR_INVALID
111 }
112};
113
114/* Polarity and triggering settings for internal interrupt sources */
115struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
116 { .polarity = 0xffffff80,
117 .triggering = 0x10000000,
118 .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */
119 }
120};
diff --git a/arch/ppc/platforms/4xx/ibm405gp.h b/arch/ppc/platforms/4xx/ibm405gp.h
new file mode 100644
index 000000000000..b2b642e81af7
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm405gp.h
@@ -0,0 +1,151 @@
1/*
2 * arch/ppc/platforms/4xx/ibm405gp.h
3 *
4 * Author: Armin Kuster akuster@mvista.com
5 *
6 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifdef __KERNEL__
13#ifndef __ASM_IBM405GP_H__
14#define __ASM_IBM405GP_H__
15
16#include <linux/config.h>
17
18/* ibm405.h at bottom of this file */
19
20/* PCI
21 * PCI Bridge config reg definitions
22 * see 17-19 of manual
23 */
24
25#define PPC405_PCI_CONFIG_ADDR 0xeec00000
26#define PPC405_PCI_CONFIG_DATA 0xeec00004
27
28#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
29 /* setbat */
30#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
31#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
32#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
33
34#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
35#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
36#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
37#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
38
39#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
40
41#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
42#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
43#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
44#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
45#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
46#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
47#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
48#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
49#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
50#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
51#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
52#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
53
54/* serial port defines */
55#define RS_TABLE_SIZE 2
56
57#define UART0_INT 0
58#define UART1_INT 1
59
60#define PCIL0_BASE 0xEF400000
61#define UART0_IO_BASE 0xEF600300
62#define UART1_IO_BASE 0xEF600400
63#define EMAC0_BASE 0xEF600800
64
65#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
66
67#define STD_UART_OP(num) \
68 { 0, BASE_BAUD, 0, UART##num##_INT, \
69 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
70 iomem_base: (u8 *)UART##num##_IO_BASE, \
71 io_type: SERIAL_IO_MEM},
72
73#if defined(CONFIG_UART0_TTYS0)
74#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
75#define SERIAL_PORT_DFNS \
76 STD_UART_OP(0) \
77 STD_UART_OP(1)
78#endif
79
80#if defined(CONFIG_UART0_TTYS1)
81#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
82#define SERIAL_PORT_DFNS \
83 STD_UART_OP(1) \
84 STD_UART_OP(0)
85#endif
86
87/* DCR defines */
88#define DCRN_CHCR_BASE 0x0B1
89#define DCRN_CHPSR_BASE 0x0B4
90#define DCRN_CPMSR_BASE 0x0B8
91#define DCRN_CPMFR_BASE 0x0BA
92
93#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */
94#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */
95#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */
96#define CHR1_CETE 0x00800000 /* CPU external timer enable */
97
98#define DCRN_CHPSR_BASE 0x0B4
99#define PSR_PLL_FWD_MASK 0xC0000000
100#define PSR_PLL_FDBACK_MASK 0x30000000
101#define PSR_PLL_TUNING_MASK 0x0E000000
102#define PSR_PLB_CPU_MASK 0x01800000
103#define PSR_OPB_PLB_MASK 0x00600000
104#define PSR_PCI_PLB_MASK 0x00180000
105#define PSR_EB_PLB_MASK 0x00060000
106#define PSR_ROM_WIDTH_MASK 0x00018000
107#define PSR_ROM_LOC 0x00004000
108#define PSR_PCI_ASYNC_EN 0x00001000
109#define PSR_PCI_ARBIT_EN 0x00000400
110
111#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
112#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
113#define IBM_CPM_CPU 0x20000000 /* processor core */
114#define IBM_CPM_DMA 0x10000000 /* DMA controller */
115#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */
116#define IBM_CPM_DCP 0x04000000 /* CodePack */
117#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
118#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
119#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
120#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
121#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
122#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
123#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
124#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
125#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */
126#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
127 | IBM_CPM_OPB | IBM_CPM_EBC \
128 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
129 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
130
131#define DCRN_DMA0_BASE 0x100
132#define DCRN_DMA1_BASE 0x108
133#define DCRN_DMA2_BASE 0x110
134#define DCRN_DMA3_BASE 0x118
135#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
136#define DCRN_DMASR_BASE 0x120
137#define DCRN_EBC_BASE 0x012
138#define DCRN_DCP0_BASE 0x014
139#define DCRN_MAL_BASE 0x180
140#define DCRN_OCM0_BASE 0x018
141#define DCRN_PLB0_BASE 0x084
142#define DCRN_PLLMR_BASE 0x0B0
143#define DCRN_POB0_BASE 0x0A0
144#define DCRN_SDRAM0_BASE 0x010
145#define DCRN_UIC0_BASE 0x0C0
146#define UIC0 DCRN_UIC0_BASE
147
148#include <asm/ibm405.h>
149
150#endif /* __ASM_IBM405GP_H__ */
151#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c
new file mode 100644
index 000000000000..01c8ccbc7214
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm405gpr.c
@@ -0,0 +1,117 @@
1/*
2 * arch/ppc/platforms/4xx/ibm405gpr.c
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/config.h>
13#include <linux/init.h>
14#include <linux/smp.h>
15#include <linux/threads.h>
16#include <linux/param.h>
17#include <linux/string.h>
18#include <platforms/4xx/ibm405gpr.h>
19#include <asm/ibm4xx.h>
20#include <asm/ocp.h>
21#include <asm/ppc4xx_pic.h>
22
23static struct ocp_func_emac_data ibm405gpr_emac0_def = {
24 .rgmii_idx = -1, /* No RGMII */
25 .rgmii_mux = -1, /* No RGMII */
26 .zmii_idx = -1, /* ZMII device index */
27 .zmii_mux = 0, /* ZMII input of this EMAC */
28 .mal_idx = 0, /* MAL device index */
29 .mal_rx_chan = 0, /* MAL rx channel number */
30 .mal_tx_chan = 0, /* MAL tx channel number */
31 .wol_irq = 9, /* WOL interrupt number */
32 .mdio_idx = -1, /* No shared MDIO */
33 .tah_idx = -1, /* No TAH */
34};
35OCP_SYSFS_EMAC_DATA()
36
37static struct ocp_func_mal_data ibm405gpr_mal0_def = {
38 .num_tx_chans = 1, /* Number of TX channels */
39 .num_rx_chans = 1, /* Number of RX channels */
40 .txeob_irq = 11, /* TX End Of Buffer IRQ */
41 .rxeob_irq = 12, /* RX End Of Buffer IRQ */
42 .txde_irq = 13, /* TX Descriptor Error IRQ */
43 .rxde_irq = 14, /* RX Descriptor Error IRQ */
44 .serr_irq = 10, /* MAL System Error IRQ */
45};
46OCP_SYSFS_MAL_DATA()
47
48static struct ocp_func_iic_data ibm405gpr_iic0_def = {
49 .fast_mode = 0, /* Use standad mode (100Khz) */
50};
51
52OCP_SYSFS_IIC_DATA()
53
54struct ocp_def core_ocp[] = {
55 { .vendor = OCP_VENDOR_IBM,
56 .function = OCP_FUNC_OPB,
57 .index = 0,
58 .paddr = 0xEF600000,
59 .irq = OCP_IRQ_NA,
60 .pm = OCP_CPM_NA,
61 },
62 { .vendor = OCP_VENDOR_IBM,
63 .function = OCP_FUNC_16550,
64 .index = 0,
65 .paddr = UART0_IO_BASE,
66 .irq = UART0_INT,
67 .pm = IBM_CPM_UART0
68 },
69 { .vendor = OCP_VENDOR_IBM,
70 .function = OCP_FUNC_16550,
71 .index = 1,
72 .paddr = UART1_IO_BASE,
73 .irq = UART1_INT,
74 .pm = IBM_CPM_UART1
75 },
76 { .vendor = OCP_VENDOR_IBM,
77 .function = OCP_FUNC_IIC,
78 .paddr = 0xEF600500,
79 .irq = 2,
80 .pm = IBM_CPM_IIC0,
81 .additions = &ibm405gpr_iic0_def,
82 .show = &ocp_show_iic_data,
83 },
84 { .vendor = OCP_VENDOR_IBM,
85 .function = OCP_FUNC_GPIO,
86 .paddr = 0xEF600700,
87 .irq = OCP_IRQ_NA,
88 .pm = IBM_CPM_GPIO0
89 },
90 { .vendor = OCP_VENDOR_IBM,
91 .function = OCP_FUNC_MAL,
92 .paddr = OCP_PADDR_NA,
93 .irq = OCP_IRQ_NA,
94 .pm = OCP_CPM_NA,
95 .additions = &ibm405gpr_mal0_def,
96 .show = &ocp_show_mal_data,
97 },
98 { .vendor = OCP_VENDOR_IBM,
99 .function = OCP_FUNC_EMAC,
100 .index = 0,
101 .paddr = EMAC0_BASE,
102 .irq = 15,
103 .pm = IBM_CPM_EMAC0,
104 .additions = &ibm405gpr_emac0_def,
105 .show = &ocp_show_emac_data,
106 },
107 { .vendor = OCP_VENDOR_INVALID
108 }
109};
110
111/* Polarity and triggering settings for internal interrupt sources */
112struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
113 { .polarity = 0xffffe000,
114 .triggering = 0x10000000,
115 .ext_irq_mask = 0x00001fff, /* IRQ7 - IRQ12, IRQ0 - IRQ6 */
116 }
117};
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.h b/arch/ppc/platforms/4xx/ibm405gpr.h
new file mode 100644
index 000000000000..45412fb4368f
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm405gpr.h
@@ -0,0 +1,151 @@
1/*
2 * arch/ppc/platforms/4xx/ibm405gpr.h
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifdef __KERNEL__
13#ifndef __ASM_IBM405GPR_H__
14#define __ASM_IBM405GPR_H__
15
16#include <linux/config.h>
17
18/* ibm405.h at bottom of this file */
19
20/* PCI
21 * PCI Bridge config reg definitions
22 * see 17-19 of manual
23 */
24
25#define PPC405_PCI_CONFIG_ADDR 0xeec00000
26#define PPC405_PCI_CONFIG_DATA 0xeec00004
27
28#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
29 /* setbat */
30#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
31#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
32#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
33
34#define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */
35#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
36#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
37#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
38
39#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
40
41#define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE)
42#define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR
43#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
44#define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR)
45#define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR
46#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
47#define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000)
48#define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR
49#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
50#define PPC4xx_ONB_IO_PADDR ((uint)0xef600000)
51#define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR
52#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
53
54/* serial port defines */
55#define RS_TABLE_SIZE 2
56
57#define UART0_INT 0
58#define UART1_INT 1
59
60#define PCIL0_BASE 0xEF400000
61#define UART0_IO_BASE 0xEF600300
62#define UART1_IO_BASE 0xEF600400
63#define EMAC0_BASE 0xEF600800
64
65#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
66
67#define STD_UART_OP(num) \
68 { 0, BASE_BAUD, 0, UART##num##_INT, \
69 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
70 iomem_base: (u8 *)UART##num##_IO_BASE, \
71 io_type: SERIAL_IO_MEM},
72
73#if defined(CONFIG_UART0_TTYS0)
74#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
75#define SERIAL_PORT_DFNS \
76 STD_UART_OP(0) \
77 STD_UART_OP(1)
78#endif
79
80#if defined(CONFIG_UART0_TTYS1)
81#define SERIAL_DEBUG_IO_BASE UART1_IO_BASE
82#define SERIAL_PORT_DFNS \
83 STD_UART_OP(1) \
84 STD_UART_OP(0)
85#endif
86
87/* DCR defines */
88#define DCRN_CHCR_BASE 0x0B1
89#define DCRN_CHPSR_BASE 0x0B4
90#define DCRN_CPMSR_BASE 0x0B8
91#define DCRN_CPMFR_BASE 0x0BA
92
93#define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */
94#define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */
95#define CHR0_UDIV 0x0000003E /* UART internal clock divisor */
96#define CHR1_CETE 0x00800000 /* CPU external timer enable */
97
98#define DCRN_CHPSR_BASE 0x0B4
99#define PSR_PLL_FWD_MASK 0xC0000000
100#define PSR_PLL_FDBACK_MASK 0x30000000
101#define PSR_PLL_TUNING_MASK 0x0E000000
102#define PSR_PLB_CPU_MASK 0x01800000
103#define PSR_OPB_PLB_MASK 0x00600000
104#define PSR_PCI_PLB_MASK 0x00180000
105#define PSR_EB_PLB_MASK 0x00060000
106#define PSR_ROM_WIDTH_MASK 0x00018000
107#define PSR_ROM_LOC 0x00004000
108#define PSR_PCI_ASYNC_EN 0x00001000
109#define PSR_PCI_ARBIT_EN 0x00000400
110
111#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
112#define IBM_CPM_PCI 0x40000000 /* PCI bridge */
113#define IBM_CPM_CPU 0x20000000 /* processor core */
114#define IBM_CPM_DMA 0x10000000 /* DMA controller */
115#define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */
116#define IBM_CPM_DCP 0x04000000 /* CodePack */
117#define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */
118#define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */
119#define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */
120#define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */
121#define IBM_CPM_UART0 0x00200000 /* serial port 0 */
122#define IBM_CPM_UART1 0x00100000 /* serial port 1 */
123#define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */
124#define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */
125#define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */
126#define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
127 | IBM_CPM_OPB | IBM_CPM_EBC \
128 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
129 | IBM_CPM_UIC | IBM_CPM_TMRCLK)
130
131#define DCRN_DMA0_BASE 0x100
132#define DCRN_DMA1_BASE 0x108
133#define DCRN_DMA2_BASE 0x110
134#define DCRN_DMA3_BASE 0x118
135#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
136#define DCRN_DMASR_BASE 0x120
137#define DCRN_EBC_BASE 0x012
138#define DCRN_DCP0_BASE 0x014
139#define DCRN_MAL_BASE 0x180
140#define DCRN_OCM0_BASE 0x018
141#define DCRN_PLB0_BASE 0x084
142#define DCRN_PLLMR_BASE 0x0B0
143#define DCRN_POB0_BASE 0x0A0
144#define DCRN_SDRAM0_BASE 0x010
145#define DCRN_UIC0_BASE 0x0C0
146#define UIC0 DCRN_UIC0_BASE
147
148#include <asm/ibm405.h>
149
150#endif /* __ASM_IBM405GPR_H__ */
151#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c
new file mode 100644
index 000000000000..27615ef8309c
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440gp.c
@@ -0,0 +1,164 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440gp.c
3 *
4 * PPC440GP I/O descriptions
5 *
6 * Matt Porter <mporter@mvista.com>
7 * Copyright 2002-2004 MontaVista Software Inc.
8 *
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18#include <linux/init.h>
19#include <linux/module.h>
20#include <platforms/4xx/ibm440gp.h>
21#include <asm/ocp.h>
22#include <asm/ppc4xx_pic.h>
23
24static struct ocp_func_emac_data ibm440gp_emac0_def = {
25 .rgmii_idx = -1, /* No RGMII */
26 .rgmii_mux = -1, /* No RGMII */
27 .zmii_idx = 0, /* ZMII device index */
28 .zmii_mux = 0, /* ZMII input of this EMAC */
29 .mal_idx = 0, /* MAL device index */
30 .mal_rx_chan = 0, /* MAL rx channel number */
31 .mal_tx_chan = 0, /* MAL tx channel number */
32 .wol_irq = 61, /* WOL interrupt number */
33 .mdio_idx = -1, /* No shared MDIO */
34 .tah_idx = -1, /* No TAH */
35};
36
37static struct ocp_func_emac_data ibm440gp_emac1_def = {
38 .rgmii_idx = -1, /* No RGMII */
39 .rgmii_mux = -1, /* No RGMII */
40 .zmii_idx = 0, /* ZMII device index */
41 .zmii_mux = 1, /* ZMII input of this EMAC */
42 .mal_idx = 0, /* MAL device index */
43 .mal_rx_chan = 1, /* MAL rx channel number */
44 .mal_tx_chan = 2, /* MAL tx channel number */
45 .wol_irq = 63, /* WOL interrupt number */
46 .mdio_idx = -1, /* No shared MDIO */
47 .tah_idx = -1, /* No TAH */
48};
49OCP_SYSFS_EMAC_DATA()
50
51static struct ocp_func_mal_data ibm440gp_mal0_def = {
52 .num_tx_chans = 4, /* Number of TX channels */
53 .num_rx_chans = 2, /* Number of RX channels */
54 .txeob_irq = 10, /* TX End Of Buffer IRQ */
55 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
56 .txde_irq = 33, /* TX Descriptor Error IRQ */
57 .rxde_irq = 34, /* RX Descriptor Error IRQ */
58 .serr_irq = 32, /* MAL System Error IRQ */
59};
60OCP_SYSFS_MAL_DATA()
61
62static struct ocp_func_iic_data ibm440gp_iic0_def = {
63 .fast_mode = 0, /* Use standad mode (100Khz) */
64};
65
66static struct ocp_func_iic_data ibm440gp_iic1_def = {
67 .fast_mode = 0, /* Use standad mode (100Khz) */
68};
69OCP_SYSFS_IIC_DATA()
70
71struct ocp_def core_ocp[] = {
72 { .vendor = OCP_VENDOR_IBM,
73 .function = OCP_FUNC_OPB,
74 .index = 0,
75 .paddr = 0x0000000140000000ULL,
76 .irq = OCP_IRQ_NA,
77 .pm = OCP_CPM_NA,
78 },
79 { .vendor = OCP_VENDOR_IBM,
80 .function = OCP_FUNC_16550,
81 .index = 0,
82 .paddr = PPC440GP_UART0_ADDR,
83 .irq = UART0_INT,
84 .pm = IBM_CPM_UART0,
85 },
86 { .vendor = OCP_VENDOR_IBM,
87 .function = OCP_FUNC_16550,
88 .index = 1,
89 .paddr = PPC440GP_UART1_ADDR,
90 .irq = UART1_INT,
91 .pm = IBM_CPM_UART1,
92 },
93 { .vendor = OCP_VENDOR_IBM,
94 .function = OCP_FUNC_IIC,
95 .index = 0,
96 .paddr = 0x0000000140000400ULL,
97 .irq = 2,
98 .pm = IBM_CPM_IIC0,
99 .additions = &ibm440gp_iic0_def,
100 .show = &ocp_show_iic_data
101 },
102 { .vendor = OCP_VENDOR_IBM,
103 .function = OCP_FUNC_IIC,
104 .index = 1,
105 .paddr = 0x0000000140000500ULL,
106 .irq = 3,
107 .pm = IBM_CPM_IIC1,
108 .additions = &ibm440gp_iic1_def,
109 .show = &ocp_show_iic_data
110 },
111 { .vendor = OCP_VENDOR_IBM,
112 .function = OCP_FUNC_GPIO,
113 .index = 0,
114 .paddr = 0x0000000140000700ULL,
115 .irq = OCP_IRQ_NA,
116 .pm = IBM_CPM_GPIO0,
117 },
118 { .vendor = OCP_VENDOR_IBM,
119 .function = OCP_FUNC_MAL,
120 .paddr = OCP_PADDR_NA,
121 .irq = OCP_IRQ_NA,
122 .pm = OCP_CPM_NA,
123 .additions = &ibm440gp_mal0_def,
124 .show = &ocp_show_mal_data,
125 },
126 { .vendor = OCP_VENDOR_IBM,
127 .function = OCP_FUNC_EMAC,
128 .index = 0,
129 .paddr = 0x0000000140000800ULL,
130 .irq = 60,
131 .pm = OCP_CPM_NA,
132 .additions = &ibm440gp_emac0_def,
133 .show = &ocp_show_emac_data,
134 },
135 { .vendor = OCP_VENDOR_IBM,
136 .function = OCP_FUNC_EMAC,
137 .index = 1,
138 .paddr = 0x0000000140000900ULL,
139 .irq = 62,
140 .pm = OCP_CPM_NA,
141 .additions = &ibm440gp_emac1_def,
142 .show = &ocp_show_emac_data,
143 },
144 { .vendor = OCP_VENDOR_IBM,
145 .function = OCP_FUNC_ZMII,
146 .paddr = 0x0000000140000780ULL,
147 .irq = OCP_IRQ_NA,
148 .pm = OCP_CPM_NA,
149 },
150 { .vendor = OCP_VENDOR_INVALID
151 }
152};
153
154/* Polarity and triggering settings for internal interrupt sources */
155struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
156 { .polarity = 0xfffffe03,
157 .triggering = 0x01c00000,
158 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
159 },
160 { .polarity = 0xffffc0ff,
161 .triggering = 0x00ff8000,
162 .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
163 },
164};
diff --git a/arch/ppc/platforms/4xx/ibm440gp.h b/arch/ppc/platforms/4xx/ibm440gp.h
new file mode 100644
index 000000000000..ae1efc03b295
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440gp.h
@@ -0,0 +1,66 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440gp.h
3 *
4 * PPC440GP definitions
5 *
6 * Roland Dreier <roland@digitalvampire.org>
7 *
8 * Copyright 2002 Roland Dreier
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * This file contains code that was originally in the files ibm44x.h
16 * and ebony.h, which were written by Matt Porter of MontaVista Software Inc.
17 */
18
19#ifdef __KERNEL__
20#ifndef __PPC_PLATFORMS_IBM440GP_H
21#define __PPC_PLATFORMS_IBM440GP_H
22
23#include <linux/config.h>
24
25/* UART */
26#define PPC440GP_UART0_ADDR 0x0000000140000200ULL
27#define PPC440GP_UART1_ADDR 0x0000000140000300ULL
28#define UART0_INT 0
29#define UART1_INT 1
30
31/* Clock and Power Management */
32#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
33#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
34#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
35#define IBM_CPM_CPU 0x02000000 /* processor core */
36#define IBM_CPM_DMA 0x01000000 /* DMA controller */
37#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
38#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
39#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
40#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
41#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
42#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
43#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
44#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
45#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
46#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
47#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
48#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
49#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
50#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
51#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
52
53#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
54 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
55 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
56 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI)
57/*
58 * Serial port defines
59 */
60#define RS_TABLE_SIZE 2
61
62#include <asm/ibm44x.h>
63#include <syslib/ibm440gp_common.h>
64
65#endif /* __PPC_PLATFORMS_IBM440GP_H */
66#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c
new file mode 100644
index 000000000000..1f38f42835b4
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440gx.c
@@ -0,0 +1,234 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440gx.c
3 *
4 * PPC440GX I/O descriptions
5 *
6 * Matt Porter <mporter@mvista.com>
7 * Copyright 2002-2004 MontaVista Software Inc.
8 *
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18#include <linux/init.h>
19#include <linux/module.h>
20#include <platforms/4xx/ibm440gx.h>
21#include <asm/ocp.h>
22#include <asm/ppc4xx_pic.h>
23
24static struct ocp_func_emac_data ibm440gx_emac0_def = {
25 .rgmii_idx = -1, /* No RGMII */
26 .rgmii_mux = -1, /* No RGMII */
27 .zmii_idx = 0, /* ZMII device index */
28 .zmii_mux = 0, /* ZMII input of this EMAC */
29 .mal_idx = 0, /* MAL device index */
30 .mal_rx_chan = 0, /* MAL rx channel number */
31 .mal_tx_chan = 0, /* MAL tx channel number */
32 .wol_irq = 61, /* WOL interrupt number */
33 .mdio_idx = -1, /* No shared MDIO */
34 .tah_idx = -1, /* No TAH */
35};
36
37static struct ocp_func_emac_data ibm440gx_emac1_def = {
38 .rgmii_idx = -1, /* No RGMII */
39 .rgmii_mux = -1, /* No RGMII */
40 .zmii_idx = 0, /* ZMII device index */
41 .zmii_mux = 1, /* ZMII input of this EMAC */
42 .mal_idx = 0, /* MAL device index */
43 .mal_rx_chan = 1, /* MAL rx channel number */
44 .mal_tx_chan = 1, /* MAL tx channel number */
45 .wol_irq = 63, /* WOL interrupt number */
46 .mdio_idx = -1, /* No shared MDIO */
47 .tah_idx = -1, /* No TAH */
48};
49
50static struct ocp_func_emac_data ibm440gx_emac2_def = {
51 .rgmii_idx = 0, /* RGMII device index */
52 .rgmii_mux = 0, /* RGMII input of this EMAC */
53 .zmii_idx = 0, /* ZMII device index */
54 .zmii_mux = 2, /* ZMII input of this EMAC */
55 .mal_idx = 0, /* MAL device index */
56 .mal_rx_chan = 2, /* MAL rx channel number */
57 .mal_tx_chan = 2, /* MAL tx channel number */
58 .wol_irq = 65, /* WOL interrupt number */
59 .mdio_idx = -1, /* No shared MDIO */
60 .tah_idx = 0, /* TAH device index */
61 .jumbo = 1, /* Jumbo frames supported */
62};
63
64static struct ocp_func_emac_data ibm440gx_emac3_def = {
65 .rgmii_idx = 0, /* RGMII device index */
66 .rgmii_mux = 1, /* RGMII input of this EMAC */
67 .zmii_idx = 0, /* ZMII device index */
68 .zmii_mux = 3, /* ZMII input of this EMAC */
69 .mal_idx = 0, /* MAL device index */
70 .mal_rx_chan = 3, /* MAL rx channel number */
71 .mal_tx_chan = 3, /* MAL tx channel number */
72 .wol_irq = 67, /* WOL interrupt number */
73 .mdio_idx = -1, /* No shared MDIO */
74 .tah_idx = 1, /* TAH device index */
75 .jumbo = 1, /* Jumbo frames supported */
76};
77OCP_SYSFS_EMAC_DATA()
78
79static struct ocp_func_mal_data ibm440gx_mal0_def = {
80 .num_tx_chans = 4, /* Number of TX channels */
81 .num_rx_chans = 4, /* Number of RX channels */
82 .txeob_irq = 10, /* TX End Of Buffer IRQ */
83 .rxeob_irq = 11, /* RX End Of Buffer IRQ */
84 .txde_irq = 33, /* TX Descriptor Error IRQ */
85 .rxde_irq = 34, /* RX Descriptor Error IRQ */
86 .serr_irq = 32, /* MAL System Error IRQ */
87};
88OCP_SYSFS_MAL_DATA()
89
90static struct ocp_func_iic_data ibm440gx_iic0_def = {
91 .fast_mode = 0, /* Use standad mode (100Khz) */
92};
93
94static struct ocp_func_iic_data ibm440gx_iic1_def = {
95 .fast_mode = 0, /* Use standad mode (100Khz) */
96};
97OCP_SYSFS_IIC_DATA()
98
99struct ocp_def core_ocp[] = {
100 { .vendor = OCP_VENDOR_IBM,
101 .function = OCP_FUNC_OPB,
102 .index = 0,
103 .paddr = 0x0000000140000000ULL,
104 .irq = OCP_IRQ_NA,
105 .pm = OCP_CPM_NA,
106 },
107 { .vendor = OCP_VENDOR_IBM,
108 .function = OCP_FUNC_16550,
109 .index = 0,
110 .paddr = PPC440GX_UART0_ADDR,
111 .irq = UART0_INT,
112 .pm = IBM_CPM_UART0,
113 },
114 { .vendor = OCP_VENDOR_IBM,
115 .function = OCP_FUNC_16550,
116 .index = 1,
117 .paddr = PPC440GX_UART1_ADDR,
118 .irq = UART1_INT,
119 .pm = IBM_CPM_UART1,
120 },
121 { .vendor = OCP_VENDOR_IBM,
122 .function = OCP_FUNC_IIC,
123 .index = 0,
124 .paddr = 0x0000000140000400ULL,
125 .irq = 2,
126 .pm = IBM_CPM_IIC0,
127 .additions = &ibm440gx_iic0_def,
128 .show = &ocp_show_iic_data
129 },
130 { .vendor = OCP_VENDOR_IBM,
131 .function = OCP_FUNC_IIC,
132 .index = 1,
133 .paddr = 0x0000000140000500ULL,
134 .irq = 3,
135 .pm = IBM_CPM_IIC1,
136 .additions = &ibm440gx_iic1_def,
137 .show = &ocp_show_iic_data
138 },
139 { .vendor = OCP_VENDOR_IBM,
140 .function = OCP_FUNC_GPIO,
141 .index = 0,
142 .paddr = 0x0000000140000700ULL,
143 .irq = OCP_IRQ_NA,
144 .pm = IBM_CPM_GPIO0,
145 },
146 { .vendor = OCP_VENDOR_IBM,
147 .function = OCP_FUNC_MAL,
148 .paddr = OCP_PADDR_NA,
149 .irq = OCP_IRQ_NA,
150 .pm = OCP_CPM_NA,
151 .additions = &ibm440gx_mal0_def,
152 .show = &ocp_show_mal_data,
153 },
154 { .vendor = OCP_VENDOR_IBM,
155 .function = OCP_FUNC_EMAC,
156 .index = 0,
157 .paddr = 0x0000000140000800ULL,
158 .irq = 60,
159 .pm = OCP_CPM_NA,
160 .additions = &ibm440gx_emac0_def,
161 .show = &ocp_show_emac_data,
162 },
163 { .vendor = OCP_VENDOR_IBM,
164 .function = OCP_FUNC_EMAC,
165 .index = 1,
166 .paddr = 0x0000000140000900ULL,
167 .irq = 62,
168 .pm = OCP_CPM_NA,
169 .additions = &ibm440gx_emac1_def,
170 .show = &ocp_show_emac_data,
171 },
172 { .vendor = OCP_VENDOR_IBM,
173 .function = OCP_FUNC_EMAC,
174 .index = 2,
175 .paddr = 0x0000000140000C00ULL,
176 .irq = 64,
177 .pm = OCP_CPM_NA,
178 .additions = &ibm440gx_emac2_def,
179 .show = &ocp_show_emac_data,
180 },
181 { .vendor = OCP_VENDOR_IBM,
182 .function = OCP_FUNC_EMAC,
183 .index = 3,
184 .paddr = 0x0000000140000E00ULL,
185 .irq = 66,
186 .pm = OCP_CPM_NA,
187 .additions = &ibm440gx_emac3_def,
188 .show = &ocp_show_emac_data,
189 },
190 { .vendor = OCP_VENDOR_IBM,
191 .function = OCP_FUNC_RGMII,
192 .paddr = 0x0000000140000790ULL,
193 .irq = OCP_IRQ_NA,
194 .pm = OCP_CPM_NA,
195 },
196 { .vendor = OCP_VENDOR_IBM,
197 .function = OCP_FUNC_ZMII,
198 .paddr = 0x0000000140000780ULL,
199 .irq = OCP_IRQ_NA,
200 .pm = OCP_CPM_NA,
201 },
202 { .vendor = OCP_VENDOR_IBM,
203 .function = OCP_FUNC_TAH,
204 .index = 0,
205 .paddr = 0x0000000140000b50ULL,
206 .irq = 68,
207 .pm = OCP_CPM_NA,
208 },
209 { .vendor = OCP_VENDOR_IBM,
210 .function = OCP_FUNC_TAH,
211 .index = 1,
212 .paddr = 0x0000000140000d50ULL,
213 .irq = 69,
214 .pm = OCP_CPM_NA,
215 },
216 { .vendor = OCP_VENDOR_INVALID
217 }
218};
219
220/* Polarity and triggering settings for internal interrupt sources */
221struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
222 { .polarity = 0xfffffe03,
223 .triggering = 0x01c00000,
224 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
225 },
226 { .polarity = 0xffffc0ff,
227 .triggering = 0x00ff8000,
228 .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
229 },
230 { .polarity = 0xffff83ff,
231 .triggering = 0x000f83c0,
232 .ext_irq_mask = 0x00007c00, /* IRQ13 - IRQ17 */
233 },
234};
diff --git a/arch/ppc/platforms/4xx/ibm440gx.h b/arch/ppc/platforms/4xx/ibm440gx.h
new file mode 100644
index 000000000000..0b59d8dcd03c
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440gx.h
@@ -0,0 +1,74 @@
1/*
2 * arch/ppc/platforms/ibm440gx.h
3 *
4 * PPC440GX definitions
5 *
6 * Matt Porter <mporter@mvista.com>
7 *
8 * Copyright 2002 Roland Dreier
9 * Copyright 2003 MontaVista Software, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18#ifdef __KERNEL__
19#ifndef __PPC_PLATFORMS_IBM440GX_H
20#define __PPC_PLATFORMS_IBM440GX_H
21
22#include <linux/config.h>
23
24#include <asm/ibm44x.h>
25
26/* UART */
27#define PPC440GX_UART0_ADDR 0x0000000140000200ULL
28#define PPC440GX_UART1_ADDR 0x0000000140000300ULL
29#define UART0_INT 0
30#define UART1_INT 1
31
32/* Clock and Power Management */
33#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
34#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
35#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
36#define IBM_CPM_RGMII 0x10000000 /* RGMII */
37#define IBM_CPM_TAHOE0 0x08000000 /* TAHOE 0 */
38#define IBM_CPM_TAHOE1 0x04000000 /* TAHOE 1 */
39#define IBM_CPM_CPU 0x02000000 /* processor core */
40#define IBM_CPM_DMA 0x01000000 /* DMA controller */
41#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
42#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
43#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
44#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
45#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
46#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
47#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
48#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
49#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
50#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
51#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
52#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
53#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
54#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
55#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
56#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
57#define IBM_CPM_EMAC1 0x00000010 /* EMAC 1 */
58#define IBM_CPM_EMAC2 0x00000008 /* EMAC 2 */
59#define IBM_CPM_EMAC3 0x00000004 /* EMAC 3 */
60
61#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
62 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
63 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
64 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
65 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
66 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
67 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
68/*
69 * Serial port defines
70 */
71#define RS_TABLE_SIZE 2
72
73#endif /* __PPC_PLATFORMS_IBM440GX_H */
74#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
new file mode 100644
index 000000000000..a203efb47aba
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440sp.c
@@ -0,0 +1,131 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440sp.c
3 *
4 * PPC440SP I/O descriptions
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 * Copyright 2002-2005 MontaVista Software Inc.
8 *
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18#include <linux/init.h>
19#include <linux/module.h>
20#include <platforms/4xx/ibm440sp.h>
21#include <asm/ocp.h>
22
23static struct ocp_func_emac_data ibm440sp_emac0_def = {
24 .rgmii_idx = -1, /* No RGMII */
25 .rgmii_mux = -1, /* No RGMII */
26 .zmii_idx = -1, /* No ZMII */
27 .zmii_mux = -1, /* No ZMII */
28 .mal_idx = 0, /* MAL device index */
29 .mal_rx_chan = 0, /* MAL rx channel number */
30 .mal_tx_chan = 0, /* MAL tx channel number */
31 .wol_irq = 61, /* WOL interrupt number */
32 .mdio_idx = -1, /* No shared MDIO */
33 .tah_idx = -1, /* No TAH */
34 .jumbo = 1, /* Jumbo frames supported */
35};
36OCP_SYSFS_EMAC_DATA()
37
38static struct ocp_func_mal_data ibm440sp_mal0_def = {
39 .num_tx_chans = 4, /* Number of TX channels */
40 .num_rx_chans = 4, /* Number of RX channels */
41 .txeob_irq = 38, /* TX End Of Buffer IRQ */
42 .rxeob_irq = 39, /* RX End Of Buffer IRQ */
43 .txde_irq = 34, /* TX Descriptor Error IRQ */
44 .rxde_irq = 35, /* RX Descriptor Error IRQ */
45 .serr_irq = 33, /* MAL System Error IRQ */
46};
47OCP_SYSFS_MAL_DATA()
48
49static struct ocp_func_iic_data ibm440sp_iic0_def = {
50 .fast_mode = 0, /* Use standad mode (100Khz) */
51};
52
53static struct ocp_func_iic_data ibm440sp_iic1_def = {
54 .fast_mode = 0, /* Use standad mode (100Khz) */
55};
56OCP_SYSFS_IIC_DATA()
57
58struct ocp_def core_ocp[] = {
59 { .vendor = OCP_VENDOR_IBM,
60 .function = OCP_FUNC_OPB,
61 .index = 0,
62 .paddr = 0x0000000140000000ULL,
63 .irq = OCP_IRQ_NA,
64 .pm = OCP_CPM_NA,
65 },
66 { .vendor = OCP_VENDOR_IBM,
67 .function = OCP_FUNC_16550,
68 .index = 0,
69 .paddr = PPC440SP_UART0_ADDR,
70 .irq = UART0_INT,
71 .pm = IBM_CPM_UART0,
72 },
73 { .vendor = OCP_VENDOR_IBM,
74 .function = OCP_FUNC_16550,
75 .index = 1,
76 .paddr = PPC440SP_UART1_ADDR,
77 .irq = UART1_INT,
78 .pm = IBM_CPM_UART1,
79 },
80 { .vendor = OCP_VENDOR_IBM,
81 .function = OCP_FUNC_16550,
82 .index = 2,
83 .paddr = PPC440SP_UART2_ADDR,
84 .irq = UART2_INT,
85 .pm = IBM_CPM_UART2,
86 },
87 { .vendor = OCP_VENDOR_IBM,
88 .function = OCP_FUNC_IIC,
89 .index = 0,
90 .paddr = 0x00000001f0000400ULL,
91 .irq = 2,
92 .pm = IBM_CPM_IIC0,
93 .additions = &ibm440sp_iic0_def,
94 .show = &ocp_show_iic_data
95 },
96 { .vendor = OCP_VENDOR_IBM,
97 .function = OCP_FUNC_IIC,
98 .index = 1,
99 .paddr = 0x00000001f0000500ULL,
100 .irq = 3,
101 .pm = IBM_CPM_IIC1,
102 .additions = &ibm440sp_iic1_def,
103 .show = &ocp_show_iic_data
104 },
105 { .vendor = OCP_VENDOR_IBM,
106 .function = OCP_FUNC_GPIO,
107 .index = 0,
108 .paddr = 0x00000001f0000700ULL,
109 .irq = OCP_IRQ_NA,
110 .pm = IBM_CPM_GPIO0,
111 },
112 { .vendor = OCP_VENDOR_IBM,
113 .function = OCP_FUNC_MAL,
114 .paddr = OCP_PADDR_NA,
115 .irq = OCP_IRQ_NA,
116 .pm = OCP_CPM_NA,
117 .additions = &ibm440sp_mal0_def,
118 .show = &ocp_show_mal_data,
119 },
120 { .vendor = OCP_VENDOR_IBM,
121 .function = OCP_FUNC_EMAC,
122 .index = 0,
123 .paddr = 0x00000001f0000800ULL,
124 .irq = 60,
125 .pm = OCP_CPM_NA,
126 .additions = &ibm440sp_emac0_def,
127 .show = &ocp_show_emac_data,
128 },
129 { .vendor = OCP_VENDOR_INVALID
130 }
131};
diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h
new file mode 100644
index 000000000000..c71e46a18b9e
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440sp.h
@@ -0,0 +1,64 @@
1/*
2 * arch/ppc/platforms/4xx/ibm440sp.h
3 *
4 * PPC440SP definitions
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 *
8 * Copyright 2004-2005 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __PPC_PLATFORMS_IBM440SP_H
18#define __PPC_PLATFORMS_IBM440SP_H
19
20#include <linux/config.h>
21
22#include <asm/ibm44x.h>
23
24/* UART */
25#define PPC440SP_UART0_ADDR 0x00000001f0000200ULL
26#define PPC440SP_UART1_ADDR 0x00000001f0000300ULL
27#define PPC440SP_UART2_ADDR 0x00000001f0000600ULL
28#define UART0_INT 0
29#define UART1_INT 1
30#define UART2_INT 2
31
32/* Clock and Power Management */
33#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
34#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
35#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
36#define IBM_CPM_CPU 0x02000000 /* processor core */
37#define IBM_CPM_DMA 0x01000000 /* DMA controller */
38#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
39#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
40#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
41#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
42#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
43#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
44#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
45#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
46#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
47#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
48#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
49#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
50#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
51#define IBM_CPM_UART2 0x00000100 /* serial port 1 */
52#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
53#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
54#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
55
56#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
57 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
58 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
59 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
60 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
61 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
62 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
63#endif /* __PPC_PLATFORMS_IBM440SP_H */
64#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.c b/arch/ppc/platforms/4xx/ibmnp405h.c
new file mode 100644
index 000000000000..ecdc5be6ae28
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibmnp405h.c
@@ -0,0 +1,172 @@
1/*
2 * arch/ppc/platforms/4xx/ibmnp405h.c
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/config.h>
13#include <linux/init.h>
14#include <asm/ocp.h>
15#include <platforms/4xx/ibmnp405h.h>
16
17static struct ocp_func_emac_data ibmnp405h_emac0_def = {
18 .rgmii_idx = -1, /* No RGMII */
19 .rgmii_mux = -1, /* No RGMII */
20 .zmii_idx = 0, /* ZMII device index */
21 .zmii_mux = 0, /* ZMII input of this EMAC */
22 .mal_idx = 0, /* MAL device index */
23 .mal_rx_chan = 0, /* MAL rx channel number */
24 .mal_tx_chan = 0, /* MAL tx channel number */
25 .wol_irq = 41, /* WOL interrupt number */
26 .mdio_idx = -1, /* No shared MDIO */
27 .tah_idx = -1, /* No TAH */
28};
29
30static struct ocp_func_emac_data ibmnp405h_emac1_def = {
31 .rgmii_idx = -1, /* No RGMII */
32 .rgmii_mux = -1, /* No RGMII */
33 .zmii_idx = 0, /* ZMII device index */
34 .zmii_mux = 1, /* ZMII input of this EMAC */
35 .mal_idx = 0, /* MAL device index */
36 .mal_rx_chan = 1, /* MAL rx channel number */
37 .mal_tx_chan = 1, /* MAL tx channel number */
38 .wol_irq = 41, /* WOL interrupt number */
39 .mdio_idx = -1, /* No shared MDIO */
40 .tah_idx = -1, /* No TAH */
41};
42static struct ocp_func_emac_data ibmnp405h_emac2_def = {
43 .rgmii_idx = -1, /* No RGMII */
44 .rgmii_mux = -1, /* No RGMII */
45 .zmii_idx = 0, /* ZMII device index */
46 .zmii_mux = 2, /* ZMII input of this EMAC */
47 .mal_idx = 0, /* MAL device index */
48 .mal_rx_chan = 2, /* MAL rx channel number */
49 .mal_tx_chan = 2, /* MAL tx channel number */
50 .wol_irq = 41, /* WOL interrupt number */
51 .mdio_idx = -1, /* No shared MDIO */
52 .tah_idx = -1, /* No TAH */
53};
54static struct ocp_func_emac_data ibmnp405h_emac3_def = {
55 .rgmii_idx = -1, /* No RGMII */
56 .rgmii_mux = -1, /* No RGMII */
57 .zmii_idx = 0, /* ZMII device index */
58 .zmii_mux = 3, /* ZMII input of this EMAC */
59 .mal_idx = 0, /* MAL device index */
60 .mal_rx_chan = 3, /* MAL rx channel number */
61 .mal_tx_chan = 3, /* MAL tx channel number */
62 .wol_irq = 41, /* WOL interrupt number */
63 .mdio_idx = -1, /* No shared MDIO */
64 .tah_idx = -1, /* No TAH */
65};
66OCP_SYSFS_EMAC_DATA()
67
68static struct ocp_func_mal_data ibmnp405h_mal0_def = {
69 .num_tx_chans = 8, /* Number of TX channels */
70 .num_rx_chans = 4, /* Number of RX channels */
71 .txeob_irq = 17, /* TX End Of Buffer IRQ */
72 .rxeob_irq = 18, /* RX End Of Buffer IRQ */
73 .txde_irq = 46, /* TX Descriptor Error IRQ */
74 .rxde_irq = 47, /* RX Descriptor Error IRQ */
75 .serr_irq = 45, /* MAL System Error IRQ */
76};
77OCP_SYSFS_MAL_DATA()
78
79static struct ocp_func_iic_data ibmnp405h_iic0_def = {
80 .fast_mode = 0, /* Use standad mode (100Khz) */
81};
82OCP_SYSFS_IIC_DATA()
83
84struct ocp_def core_ocp[] = {
85 { .vendor = OCP_VENDOR_IBM,
86 .function = OCP_FUNC_OPB,
87 .index = 0,
88 .paddr = 0xEF600000,
89 .irq = OCP_IRQ_NA,
90 .pm = OCP_CPM_NA,
91 },
92 { .vendor = OCP_VENDOR_IBM,
93 .function = OCP_FUNC_16550,
94 .index = 0,
95 .paddr = UART0_IO_BASE,
96 .irq = UART0_INT,
97 .pm = IBM_CPM_UART0
98 },
99 { .vendor = OCP_VENDOR_IBM,
100 .function = OCP_FUNC_16550,
101 .index = 1,
102 .paddr = UART1_IO_BASE,
103 .irq = UART1_INT,
104 .pm = IBM_CPM_UART1
105 },
106 { .vendor = OCP_VENDOR_IBM,
107 .function = OCP_FUNC_IIC,
108 .paddr = 0xEF600500,
109 .irq = 2,
110 .pm = IBM_CPM_IIC0,
111 .additions = &ibmnp405h_iic0_def,
112 .show = &ocp_show_iic_data
113 },
114 { .vendor = OCP_VENDOR_IBM,
115 .function = OCP_FUNC_GPIO,
116 .paddr = 0xEF600700,
117 .irq = OCP_IRQ_NA,
118 .pm = IBM_CPM_GPIO0
119 },
120 { .vendor = OCP_VENDOR_IBM,
121 .function = OCP_FUNC_MAL,
122 .paddr = OCP_PADDR_NA,
123 .irq = OCP_IRQ_NA,
124 .pm = OCP_CPM_NA,
125 .additions = &ibmnp405h_mal0_def,
126 .show = &ocp_show_mal_data,
127 },
128 { .vendor = OCP_VENDOR_IBM,
129 .function = OCP_FUNC_EMAC,
130 .index = 0,
131 .paddr = EMAC0_BASE,
132 .irq = 37,
133 .pm = IBM_CPM_EMAC0,
134 .additions = &ibmnp405h_emac0_def,
135 .show = &ocp_show_emac_data,
136 },
137 { .vendor = OCP_VENDOR_IBM,
138 .function = OCP_FUNC_EMAC,
139 .index = 1,
140 .paddr = 0xEF600900,
141 .irq = 38,
142 .pm = IBM_CPM_EMAC1,
143 .additions = &ibmnp405h_emac1_def,
144 .show = &ocp_show_emac_data,
145 },
146 { .vendor = OCP_VENDOR_IBM,
147 .function = OCP_FUNC_EMAC,
148 .index = 2,
149 .paddr = 0xEF600a00,
150 .irq = 39,
151 .pm = IBM_CPM_EMAC2,
152 .additions = &ibmnp405h_emac2_def,
153 .show = &ocp_show_emac_data,
154 },
155 { .vendor = OCP_VENDOR_IBM,
156 .function = OCP_FUNC_EMAC,
157 .index = 3,
158 .paddr = 0xEF600b00,
159 .irq = 40,
160 .pm = IBM_CPM_EMAC3,
161 .additions = &ibmnp405h_emac3_def,
162 .show = &ocp_show_emac_data,
163 },
164 { .vendor = OCP_VENDOR_IBM,
165 .function = OCP_FUNC_ZMII,
166 .paddr = 0xEF600C10,
167 .irq = OCP_IRQ_NA,
168 .pm = OCP_CPM_NA,
169 },
170 { .vendor = OCP_VENDOR_INVALID
171 }
172};
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.h b/arch/ppc/platforms/4xx/ibmnp405h.h
new file mode 100644
index 000000000000..e2c2b06128c8
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibmnp405h.h
@@ -0,0 +1,157 @@
1/*
2 * arch/ppc/platforms/4xx/ibmnp405h.h
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifdef __KERNEL__
13#ifndef __ASM_IBMNP405H_H__
14#define __ASM_IBMNP405H_H__
15
16#include <linux/config.h>
17
18/* ibm405.h at bottom of this file */
19
20#define PPC405_PCI_CONFIG_ADDR 0xeec00000
21#define PPC405_PCI_CONFIG_DATA 0xeec00004
22#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
23 /* setbat */
24#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
25#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
26#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
27
28#define PPC405_PCI_LOWER_MEM 0x00000000 /* hose_a->mem_space.start */
29#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
30#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
31#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
32
33#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
34
35#define PPC4xx_PCI_IO_ADDR ((uint)PPC405_PCI_PHY_IO_BASE)
36#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
37#define PPC4xx_PCI_CFG_ADDR ((uint)PPC405_PCI_CONFIG_ADDR)
38#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
39#define PPC4xx_PCI_LCFG_ADDR ((uint)0xef400000)
40#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
41#define PPC4xx_ONB_IO_ADDR ((uint)0xef600000)
42#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
43
44/* serial port defines */
45#define RS_TABLE_SIZE 4
46
47#define UART0_INT 0
48#define UART1_INT 1
49#define PCIL0_BASE 0xEF400000
50#define UART0_IO_BASE 0xEF600300
51#define UART1_IO_BASE 0xEF600400
52#define OPB0_BASE 0xEF600600
53#define EMAC0_BASE 0xEF600800
54
55#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
56
57#define STD_UART_OP(num) \
58 { 0, BASE_BAUD, 0, UART##num##_INT, \
59 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
60 iomem_base:(u8 *) UART##num##_IO_BASE, \
61 io_type: SERIAL_IO_MEM},
62
63#if defined(CONFIG_UART0_TTYS0)
64#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
65#define SERIAL_PORT_DFNS \
66 STD_UART_OP(0) \
67 STD_UART_OP(1)
68#endif
69
70#if defined(CONFIG_UART0_TTYS1)
71#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
72#define SERIAL_PORT_DFNS \
73 STD_UART_OP(1) \
74 STD_UART_OP(0)
75#endif
76
77/* DCR defines */
78/* ------------------------------------------------------------------------- */
79
80#define DCRN_CHCR_BASE 0x0F1
81#define DCRN_CHPSR_BASE 0x0B4
82#define DCRN_CPMSR_BASE 0x0BA
83#define DCRN_CPMFR_BASE 0x0B9
84#define DCRN_CPMER_BASE 0x0B8
85
86/* CPM Clocking & Power Mangement defines */
87#define IBM_CPM_PCI 0x40000000 /* PCI */
88#define IBM_CPM_EMAC2 0x20000000 /* EMAC 2 MII */
89#define IBM_CPM_EMAC3 0x04000000 /* EMAC 3 MII */
90#define IBM_CPM_EMAC0 0x00800000 /* EMAC 0 MII */
91#define IBM_CPM_EMAC1 0x00100000 /* EMAC 1 MII */
92#define IBM_CPM_EMMII 0 /* Shift value for MII */
93#define IBM_CPM_EMRX 1 /* Shift value for recv */
94#define IBM_CPM_EMTX 2 /* Shift value for MAC */
95#define IBM_CPM_UIC1 0x00020000 /* Universal Interrupt Controller */
96#define IBM_CPM_UIC0 0x00010000 /* Universal Interrupt Controller */
97#define IBM_CPM_CPU 0x00008000 /* processor core */
98#define IBM_CPM_EBC 0x00004000 /* ROM/SRAM peripheral controller */
99#define IBM_CPM_SDRAM0 0x00002000 /* SDRAM memory controller */
100#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO (??) */
101#define IBM_CPM_HDLC 0x00000800 /* HDCL */
102#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
103#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
104#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
105#define IBM_CPM_DMA 0x00000040 /* DMA controller */
106#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
107#define IBM_CPM_UART0 0x00000002 /* serial port 0 */
108#define IBM_CPM_UART1 0x00000001 /* serial port 1 */
109/* this is the default setting for devices put to sleep when booting */
110
111#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
112 | IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
113 | IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA \
114 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2 \
115 | IBM_CPM_EMAC3 | IBM_CPM_PCI)
116
117#define DCRN_DMA0_BASE 0x100
118#define DCRN_DMA1_BASE 0x108
119#define DCRN_DMA2_BASE 0x110
120#define DCRN_DMA3_BASE 0x118
121#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
122#define DCRN_DMASR_BASE 0x120
123#define DCRN_EBC_BASE 0x012
124#define DCRN_DCP0_BASE 0x014
125#define DCRN_MAL_BASE 0x180
126#define DCRN_OCM0_BASE 0x018
127#define DCRN_PLB0_BASE 0x084
128#define DCRN_PLLMR_BASE 0x0B0
129#define DCRN_POB0_BASE 0x0A0
130#define DCRN_SDRAM0_BASE 0x010
131#define DCRN_UIC0_BASE 0x0C0
132#define DCRN_UIC1_BASE 0x0D0
133#define DCRN_CPC0_EPRCSR 0x0F3
134
135#define UIC0_UIC1NC 0x00000002
136
137#define CHR1_CETE 0x00000004 /* CPU external timer enable */
138#define UIC0 DCRN_UIC0_BASE
139#define UIC1 DCRN_UIC1_BASE
140
141#undef NR_UICS
142#define NR_UICS 2
143
144/* EMAC DCRN's FIXME: armin */
145#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
146#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
147#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
148#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
149#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
150#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
151#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
152#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
153
154#include <asm/ibm405.h>
155
156#endif /* __ASM_IBMNP405H_H__ */
157#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c
new file mode 100644
index 000000000000..874d16bab73c
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibmstb4.c
@@ -0,0 +1,83 @@
1/*
2 * arch/ppc/platforms/4xx/ibmstb4.c
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/init.h>
13#include <asm/ocp.h>
14#include <platforms/4xx/ibmstb4.h>
15
16static struct ocp_func_iic_data ibmstb4_iic0_def = {
17 .fast_mode = 0, /* Use standad mode (100Khz) */
18};
19
20static struct ocp_func_iic_data ibmstb4_iic1_def = {
21 .fast_mode = 0, /* Use standad mode (100Khz) */
22};
23OCP_SYSFS_IIC_DATA()
24
25struct ocp_def core_ocp[] __initdata = {
26 { .vendor = OCP_VENDOR_IBM,
27 .function = OCP_FUNC_16550,
28 .index = 0,
29 .paddr = UART0_IO_BASE,
30 .irq = UART0_INT,
31 .pm = IBM_CPM_UART0,
32 },
33 { .vendor = OCP_VENDOR_IBM,
34 .function = OCP_FUNC_16550,
35 .index = 1,
36 .paddr = UART1_IO_BASE,
37 .irq = UART1_INT,
38 .pm = IBM_CPM_UART1,
39 },
40 { .vendor = OCP_VENDOR_IBM,
41 .function = OCP_FUNC_16550,
42 .index = 2,
43 .paddr = UART2_IO_BASE,
44 .irq = UART2_INT,
45 .pm = IBM_CPM_UART2,
46 },
47 { .vendor = OCP_VENDOR_IBM,
48 .function = OCP_FUNC_IIC,
49 .paddr = IIC0_BASE,
50 .irq = IIC0_IRQ,
51 .pm = IBM_CPM_IIC0,
52 .additions = &ibmstb4_iic0_def,
53 .show = &ocp_show_iic_data
54 },
55 { .vendor = OCP_VENDOR_IBM,
56 .function = OCP_FUNC_IIC,
57 .paddr = IIC1_BASE,
58 .irq = IIC1_IRQ,
59 .pm = IBM_CPM_IIC1,
60 .additions = &ibmstb4_iic1_def,
61 .show = &ocp_show_iic_data
62 },
63 { .vendor = OCP_VENDOR_IBM,
64 .function = OCP_FUNC_GPIO,
65 .paddr = GPIO0_BASE,
66 .irq = OCP_IRQ_NA,
67 .pm = IBM_CPM_GPIO0,
68 },
69 { .vendor = OCP_VENDOR_IBM,
70 .function = OCP_FUNC_IDE,
71 .paddr = IDE0_BASE,
72 .irq = IDE0_IRQ,
73 .pm = OCP_CPM_NA,
74 },
75 { .vendor = OCP_VENDOR_IBM,
76 .function = OCP_FUNC_USB,
77 .paddr = USB0_BASE,
78 .irq = USB0_IRQ,
79 .pm = OCP_CPM_NA,
80 },
81 { .vendor = OCP_VENDOR_INVALID,
82 }
83};
diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h
new file mode 100644
index 000000000000..bcb4b1ee71f2
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibmstb4.h
@@ -0,0 +1,238 @@
1/*
2 * arch/ppc/platforms/4xx/ibmstb4.h
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifdef __KERNEL__
13#ifndef __ASM_IBMSTB4_H__
14#define __ASM_IBMSTB4_H__
15
16#include <linux/config.h>
17
18/* serial port defines */
19#define STB04xxx_IO_BASE ((uint)0xe0000000)
20#define PPC4xx_PCI_IO_ADDR STB04xxx_IO_BASE
21#define PPC4xx_ONB_IO_PADDR STB04xxx_IO_BASE
22#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
23#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
24
25/*
26 * map STB04xxx internal i/o address (0x400x00xx) to an address
27 * which is below the 2GB limit...
28 *
29 * 4000 000x uart1 -> 0xe000 000x
30 * 4001 00xx ppu
31 * 4002 00xx smart card
32 * 4003 000x iic
33 * 4004 000x uart0
34 * 4005 0xxx timer
35 * 4006 00xx gpio
36 * 4007 00xx smart card
37 * 400b 000x iic
38 * 400c 000x scp
39 * 400d 000x modem
40 * 400e 000x uart2
41*/
42#define STB04xxx_MAP_IO_ADDR(a) (((uint)(a)) + (STB04xxx_IO_BASE - 0x40000000))
43
44#define RS_TABLE_SIZE 3
45#define UART0_INT 20
46
47#ifdef __BOOTER__
48#define UART0_IO_BASE 0x40040000
49#else
50#define UART0_IO_BASE 0xe0040000
51#endif
52
53#define UART1_INT 21
54
55#ifdef __BOOTER__
56#define UART1_IO_BASE 0x40000000
57#else
58#define UART1_IO_BASE 0xe0000000
59#endif
60
61#define UART2_INT 31
62#ifdef __BOOTER__
63#define UART2_IO_BASE 0x400e0000
64#else
65#define UART2_IO_BASE 0xe00e0000
66#endif
67
68#define IDE0_BASE 0x400F0000
69#define IDE0_SIZE 0x200
70#define IDE0_IRQ 25
71#define IIC0_BASE 0x40030000
72#define IIC1_BASE 0x400b0000
73#define OPB0_BASE 0x40000000
74#define GPIO0_BASE 0x40060000
75
76#define USB0_IRQ 18
77#define USB0_BASE STB04xxx_MAP_IO_ADDR(0x40010000)
78#define USB0_EXTENT 4096
79
80#define IIC_NUMS 2
81#define UART_NUMS 3
82#define IIC0_IRQ 9
83#define IIC1_IRQ 10
84#define IIC_OWN 0x55
85#define IIC_CLOCK 50
86
87#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
88
89#define STD_UART_OP(num) \
90 { 0, BASE_BAUD, 0, UART##num##_INT, \
91 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
92 iomem_base: (u8 *)UART##num##_IO_BASE, \
93 io_type: SERIAL_IO_MEM},
94
95#if defined(CONFIG_UART0_TTYS0)
96#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
97#define SERIAL_PORT_DFNS \
98 STD_UART_OP(0) \
99 STD_UART_OP(1) \
100 STD_UART_OP(2)
101#endif
102
103#if defined(CONFIG_UART0_TTYS1)
104#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
105#define SERIAL_PORT_DFNS \
106 STD_UART_OP(1) \
107 STD_UART_OP(0) \
108 STD_UART_OP(2)
109#endif
110
111#if defined(CONFIG_UART0_TTYS2)
112#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
113#define SERIAL_PORT_DFNS \
114 STD_UART_OP(2) \
115 STD_UART_OP(0) \
116 STD_UART_OP(1)
117#endif
118
119#define DCRN_BE_BASE 0x090
120#define DCRN_DMA0_BASE 0x0C0
121#define DCRN_DMA1_BASE 0x0C8
122#define DCRN_DMA2_BASE 0x0D0
123#define DCRN_DMA3_BASE 0x0D8
124#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
125#define DCRN_DMASR_BASE 0x0E0
126#define DCRN_PLB0_BASE 0x054
127#define DCRN_PLB1_BASE 0x064
128#define DCRN_POB0_BASE 0x0B0
129#define DCRN_SCCR_BASE 0x120
130#define DCRN_UIC0_BASE 0x040
131#define DCRN_BE_BASE 0x090
132#define DCRN_DMA0_BASE 0x0C0
133#define DCRN_DMA1_BASE 0x0C8
134#define DCRN_DMA2_BASE 0x0D0
135#define DCRN_DMA3_BASE 0x0D8
136#define DCRN_CIC_BASE 0x030
137#define DCRN_DMASR_BASE 0x0E0
138#define DCRN_EBIMC_BASE 0x070
139#define DCRN_DCRX_BASE 0x020
140#define DCRN_CPMFR_BASE 0x102
141#define DCRN_SCCR_BASE 0x120
142#define UIC0 DCRN_UIC0_BASE
143
144#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
145#define IBM_CPM_USB0 0x40000000 /* IEEE-1284 */
146#define IBM_CPM_IIC1 0x20000000 /* IIC 1 interface */
147#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
148#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
149#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
150#define IBM_CPM_SDRAM1 0x02000000 /* SDRAM 1 memory controller */
151#define IBM_CPM_DMA 0x01000000 /* DMA controller */
152#define IBM_CPM_DMA1 0x00800000 /* reserved */
153#define IBM_CPM_XPT1 0x00400000 /* reserved */
154#define IBM_CPM_XPT2 0x00200000 /* reserved */
155#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
156#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
157#define IBM_CPM_EPI 0x00040000 /* DCR Extension */
158#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
159#define IBM_CPM_VID 0x00010000 /* reserved */
160#define IBM_CPM_SC1 0x00008000 /* Smart Card 1 */
161#define IBM_CPM_USBSDRA 0x00004000 /* SDRAM 0 memory controller */
162#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
163#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
164#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
165#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
166#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
167#define IBM_CPM_TMRCLK 0x00000100 /* CPU timers */
168#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
169#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
170#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
171#define IBM_CPM_UART2 0x00000008 /* Serial Control Port */
172#define IBM_CPM_DDIO 0x00000004 /* Descrambler */
173#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
174
175#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
176 | IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \
177 | IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \
178 | IBM_CPM_XPT27 | IBM_CPM_UIC )
179
180#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
181#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
182/* DCRN_BESR */
183#define BESR_DSES 0x80000000 /* Data-Side Error Status */
184#define BESR_DMES 0x40000000 /* DMA Error Status */
185#define BESR_RWS 0x20000000 /* Read/Write Status */
186#define BESR_ETMASK 0x1C000000 /* Error Type */
187#define ET_PROT 0
188#define ET_PARITY 1
189#define ET_NCFG 2
190#define ET_BUSERR 4
191#define ET_BUSTO 6
192
193#define CHR1_CETE 0x00800000 /* CPU external timer enable */
194#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
195
196#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
197#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
198#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
199#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
200#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
201#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
202#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
203#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
204#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
205
206#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
207#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
208#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
209#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
210#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
211#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
212#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
213#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
214
215#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
216#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
217#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
218#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
219#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
220#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
221#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
222#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
223#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
224#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
225#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
226#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
227#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
228#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
229#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
230#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
231#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
232#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
233#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
234
235#include <asm/ibm405.h>
236
237#endif /* __ASM_IBMSTB4_H__ */
238#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmstbx25.c b/arch/ppc/platforms/4xx/ibmstbx25.c
new file mode 100644
index 000000000000..b895b9cca57d
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibmstbx25.c
@@ -0,0 +1,68 @@
1/*
2 * arch/ppc/platforms/4xx/ibmstbx25.c
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/init.h>
13#include <asm/ocp.h>
14#include <platforms/4xx/ibmstbx25.h>
15#include <asm/ppc4xx_pic.h>
16
17static struct ocp_func_iic_data ibmstbx25_iic0_def = {
18 .fast_mode = 0, /* Use standad mode (100Khz) */
19};
20OCP_SYSFS_IIC_DATA()
21
22struct ocp_def core_ocp[] __initdata = {
23 { .vendor = OCP_VENDOR_IBM,
24 .function = OCP_FUNC_16550,
25 .index = 0,
26 .paddr = UART0_IO_BASE,
27 .irq = UART0_INT,
28 .pm = IBM_CPM_UART0,
29 },
30 { .vendor = OCP_VENDOR_IBM,
31 .function = OCP_FUNC_16550,
32 .index = 1,
33 .paddr = UART1_IO_BASE,
34 .irq = UART1_INT,
35 .pm = IBM_CPM_UART1,
36 },
37 { .vendor = OCP_VENDOR_IBM,
38 .function = OCP_FUNC_16550,
39 .index = 2,
40 .paddr = UART2_IO_BASE,
41 .irq = UART2_INT,
42 .pm = IBM_CPM_UART2,
43 },
44 { .vendor = OCP_VENDOR_IBM,
45 .function = OCP_FUNC_IIC,
46 .paddr = IIC0_BASE,
47 .irq = IIC0_IRQ,
48 .pm = IBM_CPM_IIC0,
49 .additions = &ibmstbx25_iic0_def,
50 .show = &ocp_show_iic_data
51 },
52 { .vendor = OCP_VENDOR_IBM,
53 .function = OCP_FUNC_GPIO,
54 .paddr = GPIO0_BASE,
55 .irq = OCP_IRQ_NA,
56 .pm = IBM_CPM_GPIO0,
57 },
58 { .vendor = OCP_VENDOR_INVALID
59 }
60};
61
62/* Polarity and triggering settings for internal interrupt sources */
63struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
64 { .polarity = 0xffff8f80,
65 .triggering = 0x00000000,
66 .ext_irq_mask = 0x0000707f, /* IRQ7 - IRQ9, IRQ0 - IRQ6 */
67 }
68};
diff --git a/arch/ppc/platforms/4xx/ibmstbx25.h b/arch/ppc/platforms/4xx/ibmstbx25.h
new file mode 100644
index 000000000000..9a2efc366e9c
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibmstbx25.h
@@ -0,0 +1,261 @@
1/*
2 * arch/ppc/platforms/4xx/ibmstbx25.h
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#ifdef __KERNEL__
13#ifndef __ASM_IBMSTBX25_H__
14#define __ASM_IBMSTBX25_H__
15
16#include <linux/config.h>
17
18/* serial port defines */
19#define STBx25xx_IO_BASE ((uint)0xe0000000)
20#define PPC4xx_ONB_IO_PADDR STBx25xx_IO_BASE
21#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
22#define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024)
23
24/*
25 * map STBxxxx internal i/o address (0x400x00xx) to an address
26 * which is below the 2GB limit...
27 *
28 * 4000 000x uart1 -> 0xe000 000x
29 * 4001 00xx uart2
30 * 4002 00xx smart card
31 * 4003 000x iic
32 * 4004 000x uart0
33 * 4005 0xxx timer
34 * 4006 00xx gpio
35 * 4007 00xx smart card
36 * 400b 000x iic
37 * 400c 000x scp
38 * 400d 000x modem
39 * 400e 000x uart2
40*/
41#define STBx25xx_MAP_IO_ADDR(a) (((uint)(a)) + (STBx25xx_IO_BASE - 0x40000000))
42
43#define RS_TABLE_SIZE 3
44
45#define OPB_BASE_START 0x40000000
46#define EBIU_BASE_START 0xF0100000
47#define DCR_BASE_START 0x0000
48
49#ifdef __BOOTER__
50#define UART1_IO_BASE 0x40000000
51#define UART2_IO_BASE 0x40010000
52#else
53#define UART1_IO_BASE 0xe0000000
54#define UART2_IO_BASE 0xe0010000
55#endif
56#define SC0_BASE 0x40020000 /* smart card #0 */
57#define IIC0_BASE 0x40030000
58#ifdef __BOOTER__
59#define UART0_IO_BASE 0x40040000
60#else
61#define UART0_IO_BASE 0xe0040000
62#endif
63#define SCC0_BASE 0x40040000 /* Serial 0 controller IrdA */
64#define GPT0_BASE 0x40050000 /* General purpose timers */
65#define GPIO0_BASE 0x40060000
66#define SC1_BASE 0x40070000 /* smart card #1 */
67#define SCP0_BASE 0x400C0000 /* Serial Controller Port */
68#define SSP0_BASE 0x400D0000 /* Sync serial port */
69
70#define IDE0_BASE 0xf0100000
71#define REDWOOD_IDE_CTRL 0xf1100000
72
73#define RTCFPC_IRQ 0
74#define XPORT_IRQ 1
75#define AUD_IRQ 2
76#define AID_IRQ 3
77#define DMA0 4
78#define DMA1_IRQ 5
79#define DMA2_IRQ 6
80#define DMA3_IRQ 7
81#define SC0_IRQ 8
82#define IIC0_IRQ 9
83#define IIR0_IRQ 10
84#define GPT0_IRQ 11
85#define GPT1_IRQ 12
86#define SCP0_IRQ 13
87#define SSP0_IRQ 14
88#define GPT2_IRQ 15 /* count down timer */
89#define SC1_IRQ 16
90/* IRQ 17 - 19 external */
91#define UART0_INT 20
92#define UART1_INT 21
93#define UART2_INT 22
94#define XPTDMA_IRQ 23
95#define DCRIDE_IRQ 24
96/* IRQ 25 - 30 external */
97#define IDE0_IRQ 26
98
99#define IIC_NUMS 1
100#define UART_NUMS 3
101#define IIC_OWN 0x55
102#define IIC_CLOCK 50
103
104#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
105
106#define STD_UART_OP(num) \
107 { 0, BASE_BAUD, 0, UART##num##_INT, \
108 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
109 iomem_base: (u8 *)UART##num##_IO_BASE, \
110 io_type: SERIAL_IO_MEM},
111
112#if defined(CONFIG_UART0_TTYS0)
113#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
114#define SERIAL_PORT_DFNS \
115 STD_UART_OP(0) \
116 STD_UART_OP(1) \
117 STD_UART_OP(2)
118#endif
119
120#if defined(CONFIG_UART0_TTYS1)
121#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
122#define SERIAL_PORT_DFNS \
123 STD_UART_OP(1) \
124 STD_UART_OP(0) \
125 STD_UART_OP(2)
126#endif
127
128#if defined(CONFIG_UART0_TTYS2)
129#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
130#define SERIAL_PORT_DFNS \
131 STD_UART_OP(2) \
132 STD_UART_OP(0) \
133 STD_UART_OP(1)
134#endif
135
136#define DCRN_BE_BASE 0x090
137#define DCRN_DMA0_BASE 0x0C0
138#define DCRN_DMA1_BASE 0x0C8
139#define DCRN_DMA2_BASE 0x0D0
140#define DCRN_DMA3_BASE 0x0D8
141#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
142#define DCRN_DMASR_BASE 0x0E0
143#define DCRN_PLB0_BASE 0x054
144#define DCRN_PLB1_BASE 0x064
145#define DCRN_POB0_BASE 0x0B0
146#define DCRN_SCCR_BASE 0x120
147#define DCRN_UIC0_BASE 0x040
148#define DCRN_BE_BASE 0x090
149#define DCRN_DMA0_BASE 0x0C0
150#define DCRN_DMA1_BASE 0x0C8
151#define DCRN_DMA2_BASE 0x0D0
152#define DCRN_DMA3_BASE 0x0D8
153#define DCRN_CIC_BASE 0x030
154#define DCRN_DMASR_BASE 0x0E0
155#define DCRN_EBIMC_BASE 0x070
156#define DCRN_DCRX_BASE 0x020
157#define DCRN_CPMFR_BASE 0x102
158#define DCRN_SCCR_BASE 0x120
159#define DCRN_RTCFP_BASE 0x310
160
161#define UIC0 DCRN_UIC0_BASE
162
163#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
164#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
165#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
166#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
167#define IBM_CPM_IRR 0x02000000 /* Infrared receiver */
168#define IBM_CPM_DMA 0x01000000 /* DMA controller */
169#define IBM_CPM_UART2 0x00200000 /* Serial Control Port */
170#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
171#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
172#define IBM_PM_DCRIDE 0x00040000 /* DCR timeout & IDE line Mode clock */
173#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
174#define IBM_CPM_VID 0x00010000 /* reserved */
175#define IBM_CPM_SC1 0x00008000 /* Smart Card 0 */
176#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
177#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
178#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
179#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
180#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
181#define IBM_CPM_C405T 0x00000100 /* CPU timers */
182#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
183#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
184#define IBM_CPM_RTCFPC 0x00000020 /* Realtime clock and front panel */
185#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
186#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
187#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_DMA \
188 | IBM_CPM_CBS | IBM_CPM_XPT0 | IBM_CPM_C405T \
189 | IBM_CPM_XPT27 | IBM_CPM_UIC)
190
191#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
192#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
193/* DCRN_BESR */
194#define BESR_DSES 0x80000000 /* Data-Side Error Status */
195#define BESR_DMES 0x40000000 /* DMA Error Status */
196#define BESR_RWS 0x20000000 /* Read/Write Status */
197#define BESR_ETMASK 0x1C000000 /* Error Type */
198#define ET_PROT 0
199#define ET_PARITY 1
200#define ET_NCFG 2
201#define ET_BUSERR 4
202#define ET_BUSTO 6
203
204#define CHR1_CETE 0x00800000 /* CPU external timer enable */
205#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
206
207#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
208#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
209#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
210#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
211#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
212#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
213#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
214#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
215#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
216
217#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
218#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
219#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
220#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
221#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
222#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
223#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
224#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
225
226#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
227#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
228#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
229#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
230#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
231#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
232#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
233#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
234#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
235#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
236#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
237#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
238#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
239#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
240#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
241#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
242#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
243#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
244#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
245
246#define DCRN_RTC_FPC0_CNTL (DCRN_RTCFP_BASE + 0x00) /* RTC cntl */
247#define DCRN_RTC_FPC0_INT (DCRN_RTCFP_BASE + 0x01) /* RTC Interrupt */
248#define DCRN_RTC_FPC0_TIME (DCRN_RTCFP_BASE + 0x02) /* RTC time reg */
249#define DCRN_RTC_FPC0_ALRM (DCRN_RTCFP_BASE + 0x03) /* RTC Alarm reg */
250#define DCRN_RTC_FPC0_D1 (DCRN_RTCFP_BASE + 0x04) /* LED Data 1 */
251#define DCRN_RTC_FPC0_D2 (DCRN_RTCFP_BASE + 0x05) /* LED Data 2 */
252#define DCRN_RTC_FPC0_D3 (DCRN_RTCFP_BASE + 0x06) /* LED Data 3 */
253#define DCRN_RTC_FPC0_D4 (DCRN_RTCFP_BASE + 0x07) /* LED Data 4 */
254#define DCRN_RTC_FPC0_D5 (DCRN_RTCFP_BASE + 0x08) /* LED Data 5 */
255#define DCRN_RTC_FPC0_FCNTL (DCRN_RTCFP_BASE + 0x09) /* LED control */
256#define DCRN_RTC_FPC0_BRT (DCRN_RTCFP_BASE + 0x0A) /* Brightness cntl */
257
258#include <asm/ibm405.h>
259
260#endif /* __ASM_IBMSTBX25_H__ */
261#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c
new file mode 100644
index 000000000000..1df2339f1f6c
--- /dev/null
+++ b/arch/ppc/platforms/4xx/luan.c
@@ -0,0 +1,387 @@
1/*
2 * arch/ppc/platforms/4xx/luan.c
3 *
4 * Luan board specific routines
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 *
8 * Copyright 2004-2005 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/config.h>
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/types.h>
25#include <linux/major.h>
26#include <linux/blkdev.h>
27#include <linux/console.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/initrd.h>
31#include <linux/irq.h>
32#include <linux/seq_file.h>
33#include <linux/root_dev.h>
34#include <linux/tty.h>
35#include <linux/serial.h>
36#include <linux/serial_core.h>
37
38#include <asm/system.h>
39#include <asm/pgtable.h>
40#include <asm/page.h>
41#include <asm/dma.h>
42#include <asm/io.h>
43#include <asm/machdep.h>
44#include <asm/ocp.h>
45#include <asm/pci-bridge.h>
46#include <asm/time.h>
47#include <asm/todc.h>
48#include <asm/bootinfo.h>
49#include <asm/ppc4xx_pic.h>
50#include <asm/ppcboot.h>
51
52#include <syslib/ibm44x_common.h>
53#include <syslib/ibm440gx_common.h>
54#include <syslib/ibm440sp_common.h>
55
56/*
57 * This is a horrible kludge, we eventually need to abstract this
58 * generic PHY stuff, so the standard phy mode defines can be
59 * easily used from arch code.
60 */
61#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
62
63bd_t __res;
64
65static struct ibm44x_clocks clocks __initdata;
66
67static void __init
68luan_calibrate_decr(void)
69{
70 unsigned int freq;
71
72 if (mfspr(SPRN_CCR1) & CCR1_TCS)
73 freq = LUAN_TMR_CLK;
74 else
75 freq = clocks.cpu;
76
77 ibm44x_calibrate_decr(freq);
78}
79
80static int
81luan_show_cpuinfo(struct seq_file *m)
82{
83 seq_printf(m, "vendor\t\t: IBM\n");
84 seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n");
85
86 return 0;
87}
88
89static inline int
90luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
91{
92 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
93
94 /* PCIX0 in adapter mode, no host interrupt routing */
95
96 /* PCIX1 */
97 if (hose->index == 0) {
98 static char pci_irq_table[][4] =
99 /*
100 * PCI IDSEL/INTPIN->INTLINE
101 * A B C D
102 */
103 {
104 { 49, 49, 49, 49 }, /* IDSEL 1 - PCIX1 Slot 0 */
105 { 49, 49, 49, 49 }, /* IDSEL 2 - PCIX1 Slot 1 */
106 { 49, 49, 49, 49 }, /* IDSEL 3 - PCIX1 Slot 2 */
107 { 49, 49, 49, 49 }, /* IDSEL 4 - PCIX1 Slot 3 */
108 };
109 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
110 return PCI_IRQ_TABLE_LOOKUP;
111 /* PCIX2 */
112 } else if (hose->index == 1) {
113 static char pci_irq_table[][4] =
114 /*
115 * PCI IDSEL/INTPIN->INTLINE
116 * A B C D
117 */
118 {
119 { 50, 50, 50, 50 }, /* IDSEL 1 - PCIX2 Slot 0 */
120 { 50, 50, 50, 50 }, /* IDSEL 2 - PCIX2 Slot 1 */
121 { 50, 50, 50, 50 }, /* IDSEL 3 - PCIX2 Slot 2 */
122 { 50, 50, 50, 50 }, /* IDSEL 4 - PCIX2 Slot 3 */
123 };
124 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
125 return PCI_IRQ_TABLE_LOOKUP;
126 }
127 return -1;
128}
129
130static void __init luan_set_emacdata(void)
131{
132 struct ocp_def *def;
133 struct ocp_func_emac_data *emacdata;
134
135 /* Set phy_map, phy_mode, and mac_addr for the EMAC */
136 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
137 emacdata = def->additions;
138 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
139 emacdata->phy_mode = PHY_MODE_GMII;
140 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
141}
142
143#define PCIX_READW(offset) \
144 (readw((void *)((u32)pcix_reg_base+offset)))
145
146#define PCIX_WRITEW(value, offset) \
147 (writew(value, (void *)((u32)pcix_reg_base+offset)))
148
149#define PCIX_WRITEL(value, offset) \
150 (writel(value, (void *)((u32)pcix_reg_base+offset)))
151
152static void __init
153luan_setup_pcix(void)
154{
155 int i;
156 void *pcix_reg_base;
157
158 for (i=0;i<3;i++) {
159 pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE);
160
161 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
162 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
163
164 /* Disable all windows */
165 PCIX_WRITEL(0, PCIX0_POM0SA);
166 PCIX_WRITEL(0, PCIX0_POM1SA);
167 PCIX_WRITEL(0, PCIX0_POM2SA);
168 PCIX_WRITEL(0, PCIX0_PIM0SA);
169 PCIX_WRITEL(0, PCIX0_PIM0SAH);
170 PCIX_WRITEL(0, PCIX0_PIM1SA);
171 PCIX_WRITEL(0, PCIX0_PIM2SA);
172 PCIX_WRITEL(0, PCIX0_PIM2SAH);
173
174 /*
175 * Setup 512MB PLB->PCI outbound mem window
176 * (a_n000_0000->0_n000_0000)
177 * */
178 PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
179 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
180 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
181 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
182 PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
183
184 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
185 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
186 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
187 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
188 PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
189
190 iounmap(pcix_reg_base);
191 }
192
193 eieio();
194}
195
196static void __init
197luan_setup_hose(struct pci_controller *hose,
198 int lower_mem,
199 int upper_mem,
200 int cfga,
201 int cfgd,
202 u64 pcix_io_base)
203{
204 char name[20];
205
206 sprintf(name, "PCIX%d host bridge", hose->index);
207
208 hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
209
210 pci_init_resource(&hose->io_resource,
211 LUAN_PCIX_LOWER_IO,
212 LUAN_PCIX_UPPER_IO,
213 IORESOURCE_IO,
214 name);
215
216 pci_init_resource(&hose->mem_resources[0],
217 lower_mem,
218 upper_mem,
219 IORESOURCE_MEM,
220 name);
221
222 hose->io_space.start = LUAN_PCIX_LOWER_IO;
223 hose->io_space.end = LUAN_PCIX_UPPER_IO;
224 hose->mem_space.start = lower_mem;
225 hose->mem_space.end = upper_mem;
226 isa_io_base =
227 (unsigned long)ioremap64(pcix_io_base, PCIX_IO_SIZE);
228 hose->io_base_virt = (void *)isa_io_base;
229
230 setup_indirect_pci(hose, cfga, cfgd);
231 hose->set_cfg_type = 1;
232}
233
234static void __init
235luan_setup_hoses(void)
236{
237 struct pci_controller *hose1, *hose2;
238
239 /* Configure windows on the PCI-X host bridge */
240 luan_setup_pcix();
241
242 /* Allocate hoses for PCIX1 and PCIX2 */
243 hose1 = pcibios_alloc_controller();
244 hose2 = pcibios_alloc_controller();
245 if (!hose1 || !hose2)
246 return;
247
248 /* Setup PCIX1 */
249 hose1->first_busno = 0;
250 hose1->last_busno = 0xff;
251
252 luan_setup_hose(hose1,
253 LUAN_PCIX1_LOWER_MEM,
254 LUAN_PCIX1_UPPER_MEM,
255 PCIX1_CFGA,
256 PCIX1_CFGD,
257 PCIX1_IO_BASE);
258
259 hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
260
261 /* Setup PCIX2 */
262 hose2->first_busno = hose1->last_busno + 1;
263 hose2->last_busno = 0xff;
264
265 luan_setup_hose(hose2,
266 LUAN_PCIX2_LOWER_MEM,
267 LUAN_PCIX2_UPPER_MEM,
268 PCIX2_CFGA,
269 PCIX2_CFGD,
270 PCIX2_IO_BASE);
271
272 hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
273
274 ppc_md.pci_swizzle = common_swizzle;
275 ppc_md.pci_map_irq = luan_map_irq;
276}
277
278TODC_ALLOC();
279
280static void __init
281luan_early_serial_map(void)
282{
283 struct uart_port port;
284
285 /* Setup ioremapped serial port access */
286 memset(&port, 0, sizeof(port));
287 port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
288 port.irq = UART0_INT;
289 port.uartclk = clocks.uart0;
290 port.regshift = 0;
291 port.iotype = SERIAL_IO_MEM;
292 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
293 port.line = 0;
294
295 if (early_serial_setup(&port) != 0) {
296 printk("Early serial init of port 0 failed\n");
297 }
298
299 port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
300 port.irq = UART1_INT;
301 port.uartclk = clocks.uart1;
302 port.line = 1;
303
304 if (early_serial_setup(&port) != 0) {
305 printk("Early serial init of port 1 failed\n");
306 }
307
308 port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
309 port.irq = UART2_INT;
310 port.uartclk = BASE_BAUD;
311 port.line = 2;
312
313 if (early_serial_setup(&port) != 0) {
314 printk("Early serial init of port 2 failed\n");
315 }
316}
317
318static void __init
319luan_setup_arch(void)
320{
321 luan_set_emacdata();
322
323#if !defined(CONFIG_BDI_SWITCH)
324 /*
325 * The Abatron BDI JTAG debugger does not tolerate others
326 * mucking with the debug registers.
327 */
328 mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
329#endif
330
331 /*
332 * Determine various clocks.
333 * To be completely correct we should get SysClk
334 * from FPGA, because it can be changed by on-board switches
335 * --ebs
336 */
337 /* 440GX and 440SP clocking is the same -mdp */
338 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
339 ocp_sys_info.opb_bus_freq = clocks.opb;
340
341 /* init to some ~sane value until calibrate_delay() runs */
342 loops_per_jiffy = 50000000/HZ;
343
344 /* Setup PCIXn host bridges */
345 luan_setup_hoses();
346
347#ifdef CONFIG_BLK_DEV_INITRD
348 if (initrd_start)
349 ROOT_DEV = Root_RAM0;
350 else
351#endif
352#ifdef CONFIG_ROOT_NFS
353 ROOT_DEV = Root_NFS;
354#else
355 ROOT_DEV = Root_HDA1;
356#endif
357
358 luan_early_serial_map();
359
360 /* Identify the system */
361 printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n");
362}
363
364void __init platform_init(unsigned long r3, unsigned long r4,
365 unsigned long r5, unsigned long r6, unsigned long r7)
366{
367 parse_bootinfo(find_bootinfo());
368
369 /*
370 * If we were passed in a board information, copy it into the
371 * residual data area.
372 */
373 if (r3)
374 __res = *(bd_t *)(r3 + KERNELBASE);
375
376 ibm44x_platform_init();
377
378 ppc_md.setup_arch = luan_setup_arch;
379 ppc_md.show_cpuinfo = luan_show_cpuinfo;
380 ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
381 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
382
383 ppc_md.calibrate_decr = luan_calibrate_decr;
384#ifdef CONFIG_KGDB
385 ppc_md.early_serial_map = luan_early_serial_map;
386#endif
387}
diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h
new file mode 100644
index 000000000000..09b444c87816
--- /dev/null
+++ b/arch/ppc/platforms/4xx/luan.h
@@ -0,0 +1,80 @@
1/*
2 * arch/ppc/platforms/4xx/luan.h
3 *
4 * Luan board definitions
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 *
8 * Copyright 2004-2005 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifdef __KERNEL__
18#ifndef __ASM_LUAN_H__
19#define __ASM_LUAN_H__
20
21#include <linux/config.h>
22#include <platforms/4xx/ibm440sp.h>
23
24/* F/W TLB mapping used in bootloader glue to reset EMAC */
25#define PPC44x_EMAC0_MR0 0xa0000800
26
27/* Location of MAC addresses in PIBS image */
28#define PIBS_FLASH_BASE 0xffe00000
29#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400)
30
31/* External timer clock frequency */
32#define LUAN_TMR_CLK 25000000
33
34/* Flash */
35#define LUAN_FPGA_REG_0 0x0000000148300000ULL
36#define LUAN_BOOT_LARGE_FLASH(x) (x & 0x40)
37#define LUAN_SMALL_FLASH_LOW 0x00000001ff900000ULL
38#define LUAN_SMALL_FLASH_HIGH 0x00000001ffe00000ULL
39#define LUAN_SMALL_FLASH_SIZE 0x100000
40#define LUAN_LARGE_FLASH_LOW 0x00000001ff800000ULL
41#define LUAN_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
42#define LUAN_LARGE_FLASH_SIZE 0x400000
43
44/*
45 * Serial port defines
46 */
47#define RS_TABLE_SIZE 3
48
49/* PIBS defined UART mappings, used before early_serial_setup */
50#define UART0_IO_BASE 0xa0000200
51#define UART1_IO_BASE 0xa0000300
52#define UART2_IO_BASE 0xa0000600
53
54#define BASE_BAUD 11059200
55#define STD_UART_OP(num) \
56 { 0, BASE_BAUD, 0, UART##num##_INT, \
57 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
58 iomem_base: UART##num##_IO_BASE, \
59 io_type: SERIAL_IO_MEM},
60
61#define SERIAL_PORT_DFNS \
62 STD_UART_OP(0) \
63 STD_UART_OP(1) \
64 STD_UART_OP(2)
65
66/* PCI support */
67#define LUAN_PCIX_LOWER_IO 0x00000000
68#define LUAN_PCIX_UPPER_IO 0x0000ffff
69#define LUAN_PCIX0_LOWER_MEM 0x80000000
70#define LUAN_PCIX0_UPPER_MEM 0x9fffffff
71#define LUAN_PCIX1_LOWER_MEM 0xa0000000
72#define LUAN_PCIX1_UPPER_MEM 0xbfffffff
73#define LUAN_PCIX2_LOWER_MEM 0xc0000000
74#define LUAN_PCIX2_UPPER_MEM 0xdfffffff
75
76#define LUAN_PCIX_MEM_SIZE 0x20000000
77#define LUAN_PCIX_MEM_OFFSET 0x00000000
78
79#endif /* __ASM_LUAN_H__ */
80#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/oak.c b/arch/ppc/platforms/4xx/oak.c
new file mode 100644
index 000000000000..fa25ee1fa733
--- /dev/null
+++ b/arch/ppc/platforms/4xx/oak.c
@@ -0,0 +1,255 @@
1/*
2 *
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
4 *
5 * Module name: oak.c
6 *
7 * Description:
8 * Architecture- / platform-specific boot-time initialization code for
9 * the IBM PowerPC 403GCX "Oak" evaluation board. Adapted from original
10 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
11 * <dan@net4x.com>.
12 *
13 */
14
15#include <linux/config.h>
16#include <linux/init.h>
17#include <linux/smp.h>
18#include <linux/threads.h>
19#include <linux/param.h>
20#include <linux/string.h>
21#include <linux/initrd.h>
22#include <linux/irq.h>
23#include <linux/seq_file.h>
24
25#include <asm/board.h>
26#include <asm/machdep.h>
27#include <asm/page.h>
28#include <asm/bootinfo.h>
29#include <asm/ppc4xx_pic.h>
30#include <asm/time.h>
31
32#include "oak.h"
33
34/* Function Prototypes */
35
36extern void abort(void);
37
38/* Global Variables */
39
40unsigned char __res[sizeof(bd_t)];
41
42
43/*
44 * void __init oak_init()
45 *
46 * Description:
47 * This routine...
48 *
49 * Input(s):
50 * r3 - Optional pointer to a board information structure.
51 * r4 - Optional pointer to the physical starting address of the init RAM
52 * disk.
53 * r5 - Optional pointer to the physical ending address of the init RAM
54 * disk.
55 * r6 - Optional pointer to the physical starting address of any kernel
56 * command-line parameters.
57 * r7 - Optional pointer to the physical ending address of any kernel
58 * command-line parameters.
59 *
60 * Output(s):
61 * N/A
62 *
63 * Returns:
64 * N/A
65 *
66 */
67void __init
68platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
69 unsigned long r6, unsigned long r7)
70{
71 parse_bootinfo(find_bootinfo());
72
73 /*
74 * If we were passed in a board information, copy it into the
75 * residual data area.
76 */
77 if (r3) {
78 memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t));
79 }
80
81#if defined(CONFIG_BLK_DEV_INITRD)
82 /*
83 * If the init RAM disk has been configured in, and there's a valid
84 * starting address for it, set it up.
85 */
86 if (r4) {
87 initrd_start = r4 + KERNELBASE;
88 initrd_end = r5 + KERNELBASE;
89 }
90#endif /* CONFIG_BLK_DEV_INITRD */
91
92 /* Copy the kernel command line arguments to a safe place. */
93
94 if (r6) {
95 *(char *)(r7 + KERNELBASE) = 0;
96 strcpy(cmd_line, (char *)(r6 + KERNELBASE));
97 }
98
99 /* Initialize machine-dependency vectors */
100
101 ppc_md.setup_arch = oak_setup_arch;
102 ppc_md.show_percpuinfo = oak_show_percpuinfo;
103 ppc_md.irq_canonicalize = NULL;
104 ppc_md.init_IRQ = ppc4xx_pic_init;
105 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
106 ppc_md.init = NULL;
107
108 ppc_md.restart = oak_restart;
109 ppc_md.power_off = oak_power_off;
110 ppc_md.halt = oak_halt;
111
112 ppc_md.time_init = oak_time_init;
113 ppc_md.set_rtc_time = oak_set_rtc_time;
114 ppc_md.get_rtc_time = oak_get_rtc_time;
115 ppc_md.calibrate_decr = oak_calibrate_decr;
116}
117
118/*
119 * Document me.
120 */
121void __init
122oak_setup_arch(void)
123{
124 /* XXX - Implement me */
125}
126
127/*
128 * int oak_show_percpuinfo()
129 *
130 * Description:
131 * This routine pretty-prints the platform's internal CPU and bus clock
132 * frequencies into the buffer for usage in /proc/cpuinfo.
133 *
134 * Input(s):
135 * *buffer - Buffer into which CPU and bus clock frequencies are to be
136 * printed.
137 *
138 * Output(s):
139 * *buffer - Buffer with the CPU and bus clock frequencies.
140 *
141 * Returns:
142 * The number of bytes copied into 'buffer' if OK, otherwise zero or less
143 * on error.
144 */
145int
146oak_show_percpuinfo(struct seq_file *m, int i)
147{
148 bd_t *bp = (bd_t *)__res;
149
150 seq_printf(m, "clock\t\t: %dMHz\n"
151 "bus clock\t\t: %dMHz\n",
152 bp->bi_intfreq / 1000000,
153 bp->bi_busfreq / 1000000);
154
155 return 0;
156}
157
158/*
159 * Document me.
160 */
161void
162oak_restart(char *cmd)
163{
164 abort();
165}
166
167/*
168 * Document me.
169 */
170void
171oak_power_off(void)
172{
173 oak_restart(NULL);
174}
175
176/*
177 * Document me.
178 */
179void
180oak_halt(void)
181{
182 oak_restart(NULL);
183}
184
185/*
186 * Document me.
187 */
188long __init
189oak_time_init(void)
190{
191 /* XXX - Implement me */
192 return 0;
193}
194
195/*
196 * Document me.
197 */
198int __init
199oak_set_rtc_time(unsigned long time)
200{
201 /* XXX - Implement me */
202
203 return (0);
204}
205
206/*
207 * Document me.
208 */
209unsigned long __init
210oak_get_rtc_time(void)
211{
212 /* XXX - Implement me */
213
214 return (0);
215}
216
217/*
218 * void __init oak_calibrate_decr()
219 *
220 * Description:
221 * This routine retrieves the internal processor frequency from the board
222 * information structure, sets up the kernel timer decrementer based on
223 * that value, enables the 403 programmable interval timer (PIT) and sets
224 * it up for auto-reload.
225 *
226 * Input(s):
227 * N/A
228 *
229 * Output(s):
230 * N/A
231 *
232 * Returns:
233 * N/A
234 *
235 */
236void __init
237oak_calibrate_decr(void)
238{
239 unsigned int freq;
240 bd_t *bip = (bd_t *)__res;
241
242 freq = bip->bi_intfreq;
243
244 decrementer_count = freq / HZ;
245 count_period_num = 1;
246 count_period_den = freq;
247
248 /* Enable the PIT and set auto-reload of its value */
249
250 mtspr(SPRN_TCR, TCR_PIE | TCR_ARE);
251
252 /* Clear any pending timer interrupts */
253
254 mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS);
255}
diff --git a/arch/ppc/platforms/4xx/oak.h b/arch/ppc/platforms/4xx/oak.h
new file mode 100644
index 000000000000..1b86a4c66b04
--- /dev/null
+++ b/arch/ppc/platforms/4xx/oak.h
@@ -0,0 +1,96 @@
1/*
2 *
3 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
4 *
5 * Module name: oak.h
6 *
7 * Description:
8 * Macros, definitions, and data structures specific to the IBM PowerPC
9 * 403G{A,B,C,CX} "Oak" evaluation board. Anything specific to the pro-
10 * cessor itself is defined elsewhere.
11 *
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_OAK_H__
16#define __ASM_OAK_H__
17
18/* We have an IBM 403G{A,B,C,CX} core */
19#include <asm/ibm403.h>
20
21#define _IO_BASE 0
22#define _ISA_MEM_BASE 0
23#define PCI_DRAM_OFFSET 0
24
25/* Memory map for the "Oak" evaluation board */
26
27#define PPC403SPU_IO_BASE 0x40000000 /* 403 On-chip serial port */
28#define PPC403SPU_IO_SIZE 0x00000008
29#define OAKSERIAL_IO_BASE 0x7E000000 /* NS16550DV serial port */
30#define OAKSERIAL_IO_SIZE 0x00000008
31#define OAKNET_IO_BASE 0xF4000000 /* NS83902AV Ethernet */
32#define OAKNET_IO_SIZE 0x00000040
33#define OAKPROM_IO_BASE 0xFFFE0000 /* AMD 29F010 Flash ROM */
34#define OAKPROM_IO_SIZE 0x00020000
35
36
37/* Interrupt assignments fixed by the hardware implementation */
38
39/* This is annoying kbuild-2.4 problem. -- Tom */
40
41#define PPC403SPU_RX_INT 4 /* AIC_INT4 */
42#define PPC403SPU_TX_INT 5 /* AIC_INT5 */
43#define OAKNET_INT 27 /* AIC_INT27 */
44#define OAKSERIAL_INT 28 /* AIC_INT28 */
45
46#ifndef __ASSEMBLY__
47/*
48 * Data structure defining board information maintained by the boot
49 * ROM on IBM's "Oak" evaluation board. An effort has been made to
50 * keep the field names consistent with the 8xx 'bd_t' board info
51 * structures.
52 */
53
54typedef struct board_info {
55 unsigned char bi_s_version[4]; /* Version of this structure */
56 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
57 unsigned int bi_memsize; /* DRAM installed, in bytes */
58 unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
59 unsigned int bi_intfreq; /* Processor speed, in Hz */
60 unsigned int bi_busfreq; /* Bus speed, in Hz */
61} bd_t;
62
63#ifdef __cplusplus
64extern "C" {
65#endif
66
67extern void oak_init(unsigned long r3,
68 unsigned long ird_start,
69 unsigned long ird_end,
70 unsigned long cline_start,
71 unsigned long cline_end);
72extern void oak_setup_arch(void);
73extern int oak_setup_residual(char *buffer);
74extern void oak_init_IRQ(void);
75extern int oak_get_irq(struct pt_regs *regs);
76extern void oak_restart(char *cmd);
77extern void oak_power_off(void);
78extern void oak_halt(void);
79extern void oak_time_init(void);
80extern int oak_set_rtc_time(unsigned long now);
81extern unsigned long oak_get_rtc_time(void);
82extern void oak_calibrate_decr(void);
83
84#ifdef __cplusplus
85}
86#endif
87
88/* Some 4xx parts use a different timebase frequency from the internal clock.
89*/
90#define bi_tbfreq bi_intfreq
91
92#define PPC4xx_MACHINE_NAME "IBM Oak"
93
94#endif /* !__ASSEMBLY__ */
95#endif /* __ASM_OAK_H__ */
96#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/oak_setup.h b/arch/ppc/platforms/4xx/oak_setup.h
new file mode 100644
index 000000000000..8648bd084df8
--- /dev/null
+++ b/arch/ppc/platforms/4xx/oak_setup.h
@@ -0,0 +1,50 @@
1/*
2 *
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
4 *
5 * Module name: oak_setup.h
6 *
7 * Description:
8 * Architecture- / platform-specific boot-time initialization code for
9 * the IBM PowerPC 403GCX "Oak" evaluation board. Adapted from original
10 * code by Gary Thomas, Cort Dougan <cort@cs.nmt.edu>, and Dan Malek
11 * <dan@netx4.com>.
12 *
13 */
14
15#ifndef __OAK_SETUP_H__
16#define __OAK_SETUP_H__
17
18#include <asm/ptrace.h>
19#include <asm/board.h>
20
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26extern unsigned char __res[sizeof(bd_t)];
27
28extern void oak_init(unsigned long r3,
29 unsigned long ird_start,
30 unsigned long ird_end,
31 unsigned long cline_start,
32 unsigned long cline_end);
33extern void oak_setup_arch(void);
34extern int oak_setup_residual(char *buffer);
35extern void oak_init_IRQ(void);
36extern int oak_get_irq(struct pt_regs *regs);
37extern void oak_restart(char *cmd);
38extern void oak_power_off(void);
39extern void oak_halt(void);
40extern void oak_time_init(void);
41extern int oak_set_rtc_time(unsigned long now);
42extern unsigned long oak_get_rtc_time(void);
43extern void oak_calibrate_decr(void);
44
45
46#ifdef __cplusplus
47}
48#endif
49
50#endif /* __OAK_SETUP_H__ */
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
new file mode 100644
index 000000000000..28de707434f1
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -0,0 +1,367 @@
1/*
2 * arch/ppc/platforms/4xx/ocotea.c
3 *
4 * Ocotea board specific routines
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 *
8 * Copyright 2003-2005 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/config.h>
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/types.h>
25#include <linux/major.h>
26#include <linux/blkdev.h>
27#include <linux/console.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/initrd.h>
31#include <linux/irq.h>
32#include <linux/seq_file.h>
33#include <linux/root_dev.h>
34#include <linux/tty.h>
35#include <linux/serial.h>
36#include <linux/serial_core.h>
37
38#include <asm/system.h>
39#include <asm/pgtable.h>
40#include <asm/page.h>
41#include <asm/dma.h>
42#include <asm/io.h>
43#include <asm/machdep.h>
44#include <asm/ocp.h>
45#include <asm/pci-bridge.h>
46#include <asm/time.h>
47#include <asm/todc.h>
48#include <asm/bootinfo.h>
49#include <asm/ppc4xx_pic.h>
50#include <asm/ppcboot.h>
51
52#include <syslib/gen550.h>
53#include <syslib/ibm440gx_common.h>
54
55/*
56 * This is a horrible kludge, we eventually need to abstract this
57 * generic PHY stuff, so the standard phy mode defines can be
58 * easily used from arch code.
59 */
60#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
61
62bd_t __res;
63
64static struct ibm44x_clocks clocks __initdata;
65
66static void __init
67ocotea_calibrate_decr(void)
68{
69 unsigned int freq;
70
71 if (mfspr(SPRN_CCR1) & CCR1_TCS)
72 freq = OCOTEA_TMR_CLK;
73 else
74 freq = clocks.cpu;
75
76 ibm44x_calibrate_decr(freq);
77}
78
79static int
80ocotea_show_cpuinfo(struct seq_file *m)
81{
82 seq_printf(m, "vendor\t\t: IBM\n");
83 seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
84 ibm440gx_show_cpuinfo(m);
85 return 0;
86}
87
88static inline int
89ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
90{
91 static char pci_irq_table[][4] =
92 /*
93 * PCI IDSEL/INTPIN->INTLINE
94 * A B C D
95 */
96 {
97 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
98 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
99 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
100 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
101 };
102
103 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
104 return PCI_IRQ_TABLE_LOOKUP;
105}
106
107static void __init ocotea_set_emacdata(void)
108{
109 struct ocp_def *def;
110 struct ocp_func_emac_data *emacdata;
111 int i;
112
113 /*
114 * Note: Current rev. board only operates in Group 4a
115 * mode, so we always set EMAC0-1 for SMII and EMAC2-3
116 * for RGMII (though these could run in RTBI just the same).
117 *
118 * The FPGA reg 3 information isn't even suitable for
119 * determining the phy_mode, so if the board becomes
120 * usable in !4a, it will be necessary to parse an environment
121 * variable from the firmware or similar to properly configure
122 * the phy_map/phy_mode.
123 */
124 /* Set phy_map, phy_mode, and mac_addr for each EMAC */
125 for (i=0; i<4; i++) {
126 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
127 emacdata = def->additions;
128 if (i < 2) {
129 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
130 emacdata->phy_mode = PHY_MODE_SMII;
131 }
132 else {
133 emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
134 emacdata->phy_mode = PHY_MODE_RGMII;
135 }
136 if (i == 0)
137 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
138 else if (i == 1)
139 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
140 else if (i == 2)
141 memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
142 else if (i == 3)
143 memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
144 }
145}
146
147#define PCIX_READW(offset) \
148 (readw(pcix_reg_base+offset))
149
150#define PCIX_WRITEW(value, offset) \
151 (writew(value, pcix_reg_base+offset))
152
153#define PCIX_WRITEL(value, offset) \
154 (writel(value, pcix_reg_base+offset))
155
156/*
157 * FIXME: This is only here to "make it work". This will move
158 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
159 * configuration library. -Matt
160 */
161static void __init
162ocotea_setup_pcix(void)
163{
164 void *pcix_reg_base;
165
166 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
167
168 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
169 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
170
171 /* Disable all windows */
172 PCIX_WRITEL(0, PCIX0_POM0SA);
173 PCIX_WRITEL(0, PCIX0_POM1SA);
174 PCIX_WRITEL(0, PCIX0_POM2SA);
175 PCIX_WRITEL(0, PCIX0_PIM0SA);
176 PCIX_WRITEL(0, PCIX0_PIM0SAH);
177 PCIX_WRITEL(0, PCIX0_PIM1SA);
178 PCIX_WRITEL(0, PCIX0_PIM2SA);
179 PCIX_WRITEL(0, PCIX0_PIM2SAH);
180
181 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
182 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
183 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
184 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
185 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
186 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
187
188 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
189 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
190 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
191 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
192
193 eieio();
194}
195
196static void __init
197ocotea_setup_hose(void)
198{
199 struct pci_controller *hose;
200
201 /* Configure windows on the PCI-X host bridge */
202 ocotea_setup_pcix();
203
204 hose = pcibios_alloc_controller();
205
206 if (!hose)
207 return;
208
209 hose->first_busno = 0;
210 hose->last_busno = 0xff;
211
212 hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
213
214 pci_init_resource(&hose->io_resource,
215 OCOTEA_PCI_LOWER_IO,
216 OCOTEA_PCI_UPPER_IO,
217 IORESOURCE_IO,
218 "PCI host bridge");
219
220 pci_init_resource(&hose->mem_resources[0],
221 OCOTEA_PCI_LOWER_MEM,
222 OCOTEA_PCI_UPPER_MEM,
223 IORESOURCE_MEM,
224 "PCI host bridge");
225
226 hose->io_space.start = OCOTEA_PCI_LOWER_IO;
227 hose->io_space.end = OCOTEA_PCI_UPPER_IO;
228 hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
229 hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
230 isa_io_base =
231 (unsigned long)ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
232 hose->io_base_virt = (void *)isa_io_base;
233
234 setup_indirect_pci(hose,
235 OCOTEA_PCI_CFGA_PLB32,
236 OCOTEA_PCI_CFGD_PLB32);
237 hose->set_cfg_type = 1;
238
239 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
240
241 ppc_md.pci_swizzle = common_swizzle;
242 ppc_md.pci_map_irq = ocotea_map_irq;
243}
244
245
246TODC_ALLOC();
247
248static void __init
249ocotea_early_serial_map(void)
250{
251 struct uart_port port;
252
253 /* Setup ioremapped serial port access */
254 memset(&port, 0, sizeof(port));
255 port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
256 port.irq = UART0_INT;
257 port.uartclk = clocks.uart0;
258 port.regshift = 0;
259 port.iotype = SERIAL_IO_MEM;
260 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
261 port.line = 0;
262
263 if (early_serial_setup(&port) != 0) {
264 printk("Early serial init of port 0 failed\n");
265 }
266
267#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
268 /* Configure debug serial access */
269 gen550_init(0, &port);
270#endif
271
272 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
273 port.irq = UART1_INT;
274 port.uartclk = clocks.uart1;
275 port.line = 1;
276
277 if (early_serial_setup(&port) != 0) {
278 printk("Early serial init of port 1 failed\n");
279 }
280
281#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
282 /* Configure debug serial access */
283 gen550_init(1, &port);
284#endif
285}
286
287static void __init
288ocotea_setup_arch(void)
289{
290 ocotea_set_emacdata();
291
292 ibm440gx_tah_enable();
293
294 /* Setup TODC access */
295 TODC_INIT(TODC_TYPE_DS1743,
296 0,
297 0,
298 ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
299 8);
300
301 /* init to some ~sane value until calibrate_delay() runs */
302 loops_per_jiffy = 50000000/HZ;
303
304 /* Setup PCI host bridge */
305 ocotea_setup_hose();
306
307#ifdef CONFIG_BLK_DEV_INITRD
308 if (initrd_start)
309 ROOT_DEV = Root_RAM0;
310 else
311#endif
312#ifdef CONFIG_ROOT_NFS
313 ROOT_DEV = Root_NFS;
314#else
315 ROOT_DEV = Root_HDA1;
316#endif
317
318 ocotea_early_serial_map();
319
320 /* Identify the system */
321 printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
322}
323
324static void __init ocotea_init(void)
325{
326 ibm440gx_l2c_setup(&clocks);
327}
328
329void __init platform_init(unsigned long r3, unsigned long r4,
330 unsigned long r5, unsigned long r6, unsigned long r7)
331{
332 parse_bootinfo(find_bootinfo());
333
334 /*
335 * If we were passed in a board information, copy it into the
336 * residual data area.
337 */
338 if (r3)
339 __res = *(bd_t *)(r3 + KERNELBASE);
340
341 /*
342 * Determine various clocks.
343 * To be completely correct we should get SysClk
344 * from FPGA, because it can be changed by on-board switches
345 * --ebs
346 */
347 ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
348 ocp_sys_info.opb_bus_freq = clocks.opb;
349
350 ibm44x_platform_init();
351
352 ppc_md.setup_arch = ocotea_setup_arch;
353 ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
354 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
355
356 ppc_md.calibrate_decr = ocotea_calibrate_decr;
357 ppc_md.time_init = todc_time_init;
358 ppc_md.set_rtc_time = todc_set_rtc_time;
359 ppc_md.get_rtc_time = todc_get_rtc_time;
360
361 ppc_md.nvram_read_val = todc_direct_read_val;
362 ppc_md.nvram_write_val = todc_direct_write_val;
363#ifdef CONFIG_KGDB
364 ppc_md.early_serial_map = ocotea_early_serial_map;
365#endif
366 ppc_md.init = ocotea_init;
367}
diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
new file mode 100644
index 000000000000..202dc8251190
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ocotea.h
@@ -0,0 +1,88 @@
1/*
2 * arch/ppc/platforms/ocotea.h
3 *
4 * Ocotea board definitions
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 *
8 * Copyright 2003-2005 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifdef __KERNEL__
18#ifndef __ASM_OCOTEA_H__
19#define __ASM_OCOTEA_H__
20
21#include <linux/config.h>
22#include <platforms/4xx/ibm440gx.h>
23
24/* F/W TLB mapping used in bootloader glue to reset EMAC */
25#define PPC44x_EMAC0_MR0 0xe0000800
26
27/* Location of MAC addresses in PIBS image */
28#define PIBS_FLASH_BASE 0xfff00000
29#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xb0500)
30#define PIBS_MAC_SIZE 0x200
31#define PIBS_MAC_OFFSET 0x100
32
33/* External timer clock frequency */
34#define OCOTEA_TMR_CLK 25000000
35
36/* RTC/NVRAM location */
37#define OCOTEA_RTC_ADDR 0x0000000148000000ULL
38#define OCOTEA_RTC_SIZE 0x2000
39
40/* Flash */
41#define OCOTEA_FPGA_REG_0 0x0000000148300000ULL
42#define OCOTEA_BOOT_LARGE_FLASH(x) (x & 0x40)
43#define OCOTEA_SMALL_FLASH_LOW 0x00000001ff900000ULL
44#define OCOTEA_SMALL_FLASH_HIGH 0x00000001fff00000ULL
45#define OCOTEA_SMALL_FLASH_SIZE 0x100000
46#define OCOTEA_LARGE_FLASH_LOW 0x00000001ff800000ULL
47#define OCOTEA_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
48#define OCOTEA_LARGE_FLASH_SIZE 0x400000
49
50/* FPGA_REG_3 (Ethernet Groups) */
51#define OCOTEA_FPGA_REG_3 0x0000000148300003ULL
52
53/*
54 * Serial port defines
55 */
56#define RS_TABLE_SIZE 2
57
58/* OpenBIOS defined UART mappings, used before early_serial_setup */
59#define UART0_IO_BASE 0xE0000200
60#define UART1_IO_BASE 0xE0000300
61
62#define BASE_BAUD 11059200/16
63#define STD_UART_OP(num) \
64 { 0, BASE_BAUD, 0, UART##num##_INT, \
65 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
66 iomem_base: UART##num##_IO_BASE, \
67 io_type: SERIAL_IO_MEM},
68
69#define SERIAL_PORT_DFNS \
70 STD_UART_OP(0) \
71 STD_UART_OP(1)
72
73/* PCI support */
74#define OCOTEA_PCI_LOWER_IO 0x00000000
75#define OCOTEA_PCI_UPPER_IO 0x0000ffff
76#define OCOTEA_PCI_LOWER_MEM 0x80000000
77#define OCOTEA_PCI_UPPER_MEM 0xffffefff
78
79#define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL
80#define OCOTEA_PCI_CFGA_PLB32 0x0ec00000
81#define OCOTEA_PCI_CFGD_PLB32 0x0ec00004
82
83#define OCOTEA_PCI_IO_BASE 0x0000000208000000ULL
84#define OCOTEA_PCI_IO_SIZE 0x00010000
85#define OCOTEA_PCI_MEM_OFFSET 0x00000000
86
87#endif /* __ASM_OCOTEA_H__ */
88#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c
new file mode 100644
index 000000000000..2f5e410afbc5
--- /dev/null
+++ b/arch/ppc/platforms/4xx/redwood5.c
@@ -0,0 +1,110 @@
1/*
2 * arch/ppc/platforms/4xx/redwood5.c
3 *
4 * Support for the IBM redwood5 eval board file
5 *
6 * Author: Armin Kuster <akuster@mvista.com>
7 *
8 * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/pagemap.h>
17#include <linux/device.h>
18#include <linux/ioport.h>
19#include <asm/io.h>
20#include <asm/machdep.h>
21
22static struct resource smc91x_resources[] = {
23 [0] = {
24 .start = SMC91111_BASE_ADDR,
25 .end = SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1,
26 .flags = IORESOURCE_MEM,
27 },
28 [1] = {
29 .start = SMC91111_IRQ,
30 .end = SMC91111_IRQ,
31 .flags = IORESOURCE_IRQ,
32 },
33};
34
35static struct platform_device smc91x_device = {
36 .name = "smc91x",
37 .id = 0,
38 .num_resources = ARRAY_SIZE(smc91x_resources),
39 .resource = smc91x_resources,
40};
41
42static struct platform_device *redwood5_devs[] __initdata = {
43 &smc91x_device,
44};
45
46static int __init
47redwood5_platform_add_devices(void)
48{
49 return platform_add_devices(redwood5_devs, ARRAY_SIZE(redwood5_devs));
50}
51
52void __init
53redwood5_setup_arch(void)
54{
55 ppc4xx_setup_arch();
56
57#ifdef CONFIG_DEBUG_BRINGUP
58 printk("\n");
59 printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
60 printk("\n");
61 printk("bi_s_version\t %s\n", bip->bi_s_version);
62 printk("bi_r_version\t %s\n", bip->bi_r_version);
63 printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,bip->bi_memsize/(1024*1000));
64 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
65 bip->bi_enetaddr[0], bip->bi_enetaddr[1],
66 bip->bi_enetaddr[2], bip->bi_enetaddr[3],
67 bip->bi_enetaddr[4], bip->bi_enetaddr[5]);
68
69 printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
70 bip->bi_intfreq, bip->bi_intfreq/ 1000000);
71
72 printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
73 bip->bi_busfreq, bip->bi_busfreq / 1000000 );
74 printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n",
75 bip->bi_tbfreq, bip->bi_tbfreq/1000000);
76
77 printk("\n");
78#endif
79 device_initcall(redwood5_platform_add_devices);
80}
81
82void __init
83redwood5_map_io(void)
84{
85 int i;
86
87 ppc4xx_map_io();
88 for (i = 0; i < 16; i++) {
89 unsigned long v, p;
90
91 /* 0x400x0000 -> 0xe00x0000 */
92 p = 0x40000000 | (i << 16);
93 v = STB04xxx_IO_BASE | (i << 16);
94
95 io_block_mapping(v, p, PAGE_SIZE,
96 _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) | _PAGE_GUARDED);
97 }
98
99
100}
101
102void __init
103platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
104 unsigned long r6, unsigned long r7)
105{
106 ppc4xx_init(r3, r4, r5, r6, r7);
107
108 ppc_md.setup_arch = redwood5_setup_arch;
109 ppc_md.setup_io_mappings = redwood5_map_io;
110}
diff --git a/arch/ppc/platforms/4xx/redwood5.h b/arch/ppc/platforms/4xx/redwood5.h
new file mode 100644
index 000000000000..264e34fb3fbd
--- /dev/null
+++ b/arch/ppc/platforms/4xx/redwood5.h
@@ -0,0 +1,54 @@
1/*
2 * arch/ppc/platforms/4xx/redwood5.h
3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC
5 * STB03xxx "Redwood" evaluation board.
6 *
7 * Author: Armin Kuster <akuster@mvista.com>
8 *
9 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_REDWOOD5_H__
17#define __ASM_REDWOOD5_H__
18
19/* Redwood5 has an STB04xxx core */
20#include <platforms/4xx/ibmstb4.h>
21
22#ifndef __ASSEMBLY__
23typedef struct board_info {
24 unsigned char bi_s_version[4]; /* Version of this structure */
25 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
26 unsigned int bi_memsize; /* DRAM installed, in bytes */
27 unsigned int bi_dummy; /* field shouldn't exist */
28 unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
29 unsigned int bi_intfreq; /* Processor speed, in Hz */
30 unsigned int bi_busfreq; /* Bus speed, in Hz */
31 unsigned int bi_tbfreq; /* Software timebase freq */
32} bd_t;
33#endif /* !__ASSEMBLY__ */
34
35
36#define SMC91111_BASE_ADDR 0xf2000300
37#define SMC91111_REG_SIZE 16
38#define SMC91111_IRQ 28
39
40#ifdef MAX_HWIFS
41#undef MAX_HWIFS
42#endif
43#define MAX_HWIFS 1
44
45#define _IO_BASE 0
46#define _ISA_MEM_BASE 0
47#define PCI_DRAM_OFFSET 0
48
49#define BASE_BAUD (378000000 / 18 / 16)
50
51#define PPC4xx_MACHINE_NAME "IBM Redwood5"
52
53#endif /* __ASM_REDWOOD5_H__ */
54#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/redwood6.c b/arch/ppc/platforms/4xx/redwood6.c
new file mode 100644
index 000000000000..8b1012994dfc
--- /dev/null
+++ b/arch/ppc/platforms/4xx/redwood6.c
@@ -0,0 +1,159 @@
1/*
2 * arch/ppc/platforms/4xx/redwood6.c
3 *
4 * Author: Armin Kuster <akuster@mvista.com>
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/config.h>
13#include <linux/init.h>
14#include <linux/pagemap.h>
15#include <linux/device.h>
16#include <linux/ioport.h>
17#include <asm/io.h>
18#include <asm/ppc4xx_pic.h>
19#include <linux/delay.h>
20#include <asm/machdep.h>
21
22/*
23 * Define external IRQ senses and polarities.
24 */
25unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
26 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
27 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
28 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
29 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
30 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
31 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
32 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
33 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
34 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
35 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
36};
37
38static struct resource smc91x_resources[] = {
39 [0] = {
40 .start = SMC91111_BASE_ADDR,
41 .end = SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1,
42 .flags = IORESOURCE_MEM,
43 },
44 [1] = {
45 .start = SMC91111_IRQ,
46 .end = SMC91111_IRQ,
47 .flags = IORESOURCE_IRQ,
48 },
49};
50
51static struct platform_device smc91x_device = {
52 .name = "smc91x",
53 .id = 0,
54 .num_resources = ARRAY_SIZE(smc91x_resources),
55 .resource = smc91x_resources,
56};
57
58static struct platform_device *redwood6_devs[] __initdata = {
59 &smc91x_device,
60};
61
62static int __init
63redwood6_platform_add_devices(void)
64{
65 return platform_add_devices(redwood6_devs, ARRAY_SIZE(redwood6_devs));
66}
67
68
69void __init
70redwood6_setup_arch(void)
71{
72#ifdef CONFIG_IDE
73 void *xilinx, *xilinx_1, *xilinx_2;
74 unsigned short us_reg5;
75#endif
76
77 ppc4xx_setup_arch();
78
79#ifdef CONFIG_IDE
80 xilinx = (unsigned long) ioremap(IDE_XLINUX_MUX_BASE, 0x10);
81 /* init xilinx control registers - enable ide mux, clear reset bit */
82 if (!xilinx) {
83 printk(KERN_CRIT
84 "redwood6_setup_arch() xilinxi ioremap failed\n");
85 return;
86 }
87 xilinx_1 = xilinx + 0xa;
88 xilinx_2 = xilinx + 0xe;
89
90 us_reg5 = readb(xilinx_1);
91 writeb(0x01d1, xilinx_1);
92 writeb(0x0008, xilinx_2);
93
94 udelay(10 * 1000);
95
96 writeb(0x01d1, xilinx_1);
97 writeb(0x0008, xilinx_2);
98#endif
99
100#ifdef DEBUG_BRINGUP
101 bd_t *bip = (bd_t *) __res;
102 printk("\n");
103 printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
104 printk("\n");
105 printk("bi_s_version\t %s\n", bip->bi_s_version);
106 printk("bi_r_version\t %s\n", bip->bi_r_version);
107 printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
108 bip->bi_memsize / (1024 * 1000));
109 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
110 bip->bi_enetaddr[0], bip->bi_enetaddr[1], bip->bi_enetaddr[2],
111 bip->bi_enetaddr[3], bip->bi_enetaddr[4], bip->bi_enetaddr[5]);
112
113 printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
114 bip->bi_intfreq, bip->bi_intfreq / 1000000);
115
116 printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
117 bip->bi_busfreq, bip->bi_busfreq / 1000000);
118 printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n",
119 bip->bi_tbfreq, bip->bi_tbfreq / 1000000);
120
121 printk("\n");
122#endif
123
124 /* Identify the system */
125 printk(KERN_INFO "IBM Redwood6 (STBx25XX) Platform\n");
126 printk(KERN_INFO
127 "Port by MontaVista Software, Inc. (source@mvista.com)\n");
128
129 device_initcall(redwood6_platform_add_devices);
130}
131
132void __init
133redwood6_map_io(void)
134{
135 int i;
136
137 ppc4xx_map_io();
138 for (i = 0; i < 16; i++) {
139 unsigned long v, p;
140
141 /* 0x400x0000 -> 0xe00x0000 */
142 p = 0x40000000 | (i << 16);
143 v = STBx25xx_IO_BASE | (i << 16);
144
145 io_block_mapping(v, p, PAGE_SIZE,
146 _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) |
147 _PAGE_GUARDED);
148 }
149}
150
151void __init
152platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
153 unsigned long r6, unsigned long r7)
154{
155 ppc4xx_init(r3, r4, r5, r6, r7);
156
157 ppc_md.setup_arch = redwood6_setup_arch;
158 ppc_md.setup_io_mappings = redwood6_map_io;
159}
diff --git a/arch/ppc/platforms/4xx/redwood6.h b/arch/ppc/platforms/4xx/redwood6.h
new file mode 100644
index 000000000000..1814b9f5fc3a
--- /dev/null
+++ b/arch/ppc/platforms/4xx/redwood6.h
@@ -0,0 +1,55 @@
1/*
2 * arch/ppc/platforms/4xx/redwood6.h
3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC
5 * STBx25xx "Redwood6" evaluation board.
6 *
7 * Author: Armin Kuster <akuster@mvista.com>
8 *
9 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_REDWOOD5_H__
17#define __ASM_REDWOOD5_H__
18
19/* Redwood6 has an STBx25xx core */
20#include <platforms/4xx/ibmstbx25.h>
21
22#ifndef __ASSEMBLY__
23typedef struct board_info {
24 unsigned char bi_s_version[4]; /* Version of this structure */
25 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
26 unsigned int bi_memsize; /* DRAM installed, in bytes */
27 unsigned int bi_dummy; /* field shouldn't exist */
28 unsigned char bi_enetaddr[6]; /* Ethernet MAC address */
29 unsigned int bi_intfreq; /* Processor speed, in Hz */
30 unsigned int bi_busfreq; /* Bus speed, in Hz */
31 unsigned int bi_tbfreq; /* Software timebase freq */
32} bd_t;
33#endif /* !__ASSEMBLY__ */
34
35#define SMC91111_BASE_ADDR 0xf2030300
36#define SMC91111_REG_SIZE 16
37#define SMC91111_IRQ 27
38#define IDE_XLINUX_MUX_BASE 0xf2040000
39#define IDE_DMA_ADDR 0xfce00000
40
41#ifdef MAX_HWIFS
42#undef MAX_HWIFS
43#endif
44#define MAX_HWIFS 1
45
46#define _IO_BASE 0
47#define _ISA_MEM_BASE 0
48#define PCI_DRAM_OFFSET 0
49
50#define BASE_BAUD (378000000 / 18 / 16)
51
52#define PPC4xx_MACHINE_NAME "IBM Redwood6"
53
54#endif /* __ASM_REDWOOD5_H__ */
55#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c
new file mode 100644
index 000000000000..d8019eec4704
--- /dev/null
+++ b/arch/ppc/platforms/4xx/sycamore.c
@@ -0,0 +1,278 @@
1/*
2 * arch/ppc/platforms/4xx/sycamore.c
3 *
4 * Architecture- / platform-specific boot-time initialization code for
5 * IBM PowerPC 4xx based boards.
6 *
7 * Author: Armin Kuster <akuster@mvista.com>
8 *
9 * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/smp.h>
17#include <linux/threads.h>
18#include <linux/param.h>
19#include <linux/string.h>
20#include <linux/pci.h>
21#include <linux/rtc.h>
22
23#include <asm/ocp.h>
24#include <asm/ppc4xx_pic.h>
25#include <asm/system.h>
26#include <asm/pci-bridge.h>
27#include <asm/machdep.h>
28#include <asm/page.h>
29#include <asm/time.h>
30#include <asm/io.h>
31#include <asm/ibm_ocp_pci.h>
32#include <asm/todc.h>
33
34#undef DEBUG
35
36#ifdef DEBUG
37#define DBG(x...) printk(x)
38#else
39#define DBG(x...)
40#endif
41
42void *kb_cs;
43void *kb_data;
44void *sycamore_rtc_base;
45
46/*
47 * Define external IRQ senses and polarities.
48 */
49unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
50 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 7 */
51 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 8 */
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 9 */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 10 */
54 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 11 */
55 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 12 */
56 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 0 */
57 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 1 */
58 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 2 */
59 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 3 */
60 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 4 */
61 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 5 */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext Int 6 */
63};
64
65
66/* Some IRQs unique to Sycamore.
67 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
68 */
69int __init
70ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
71{
72 static char pci_irq_table[][4] =
73 /*
74 * PCI IDSEL/INTPIN->INTLINE
75 * A B C D
76 */
77 {
78 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
79 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
80 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
81 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
82 };
83
84 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
85 return PCI_IRQ_TABLE_LOOKUP;
86};
87
88void __init
89sycamore_setup_arch(void)
90{
91#define SYCAMORE_PS2_BASE 0xF0100000
92#define SYCAMORE_FPGA_BASE 0xF0300000
93
94 void *fpga_brdc;
95 unsigned char fpga_brdc_data;
96 void *fpga_enable;
97 void *fpga_polarity;
98 void *fpga_status;
99 void *fpga_trigger;
100
101 ppc4xx_setup_arch();
102
103 ibm_ocp_set_emac(0, 1);
104
105 kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
106 if (!kb_data) {
107 printk(KERN_CRIT
108 "sycamore_setup_arch() kb_data ioremap failed\n");
109 return;
110 }
111
112 kb_cs = kb_data + 1;
113
114 fpga_status = ioremap(SYCAMORE_FPGA_BASE, 8);
115 if (!fpga_status) {
116 printk(KERN_CRIT
117 "sycamore_setup_arch() fpga_status ioremap failed\n");
118 return;
119 }
120
121 fpga_enable = fpga_status + 1;
122 fpga_polarity = fpga_status + 2;
123 fpga_trigger = fpga_status + 3;
124 fpga_brdc = fpga_status + 4;
125
126 /* split the keyboard and mouse interrupts */
127 fpga_brdc_data = readb(fpga_brdc);
128 fpga_brdc_data |= 0x80;
129 writeb(fpga_brdc_data, fpga_brdc);
130
131 writeb(0x3, fpga_enable);
132
133 writeb(0x3, fpga_polarity);
134
135 writeb(0x3, fpga_trigger);
136
137 /* RTC step for the sycamore */
138 sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
139 TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
140 sycamore_rtc_base, 8);
141
142 /* Identify the system */
143 printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
144 printk(KERN_INFO
145 "Port by MontaVista Software, Inc. (source@mvista.com)\n");
146}
147
148void __init
149bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
150{
151#ifdef CONFIG_PCI
152 unsigned int bar_response, bar;
153 /*
154 * Expected PCI mapping:
155 *
156 * PLB addr PCI memory addr
157 * --------------------- ---------------------
158 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
159 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
160 *
161 * PLB addr PCI io addr
162 * --------------------- ---------------------
163 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
164 *
165 * The following code is simplified by assuming that the bootrom
166 * has been well behaved in following this mapping.
167 */
168
169#ifdef DEBUG
170 int i;
171
172 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
173 printk("PCI bridge regs before fixup \n");
174 for (i = 0; i <= 3; i++) {
175 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
176 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
177 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
178 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
179 }
180 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
181 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
182 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
183 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
184
185#endif
186
187 /* added for IBM boot rom version 1.15 bios bar changes -AK */
188
189 /* Disable region first */
190 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
191 /* PLB starting addr, PCI: 0x80000000 */
192 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
193 /* PCI start addr, 0x80000000 */
194 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
195 /* 512MB range of PLB to PCI */
196 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
197 /* Enable no pre-fetch, enable region */
198 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
199 (PPC405_PCI_UPPER_MEM -
200 PPC405_PCI_MEM_BASE)) | 0x01));
201
202 /* Enable inbound region one - 1GB size */
203 out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
204
205 /* Disable outbound region one */
206 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
207 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
208 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
209 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
210 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
211
212 /* Disable inbound region two */
213 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
214
215 /* Disable outbound region two */
216 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
217 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
218 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
219 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
220 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
221
222 /* Zero config bars */
223 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
224 early_write_config_dword(hose, hose->first_busno,
225 PCI_FUNC(hose->first_busno), bar,
226 0x00000000);
227 early_read_config_dword(hose, hose->first_busno,
228 PCI_FUNC(hose->first_busno), bar,
229 &bar_response);
230 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
231 hose->first_busno, PCI_SLOT(hose->first_busno),
232 PCI_FUNC(hose->first_busno), bar, bar_response);
233 }
234 /* end work arround */
235
236#ifdef DEBUG
237 printk("PCI bridge regs after fixup \n");
238 for (i = 0; i <= 3; i++) {
239 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
240 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
241 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
242 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
243 }
244 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
245 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
246 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
247 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
248
249#endif
250#endif
251
252}
253
254void __init
255sycamore_map_io(void)
256{
257 ppc4xx_map_io();
258 io_block_mapping(SYCAMORE_RTC_VADDR,
259 SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
260}
261
262void __init
263platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
264 unsigned long r6, unsigned long r7)
265{
266 ppc4xx_init(r3, r4, r5, r6, r7);
267
268 ppc_md.setup_arch = sycamore_setup_arch;
269 ppc_md.setup_io_mappings = sycamore_map_io;
270
271#ifdef CONFIG_GEN_RTC
272 ppc_md.time_init = todc_time_init;
273 ppc_md.set_rtc_time = todc_set_rtc_time;
274 ppc_md.get_rtc_time = todc_get_rtc_time;
275 ppc_md.nvram_read_val = todc_direct_read_val;
276 ppc_md.nvram_write_val = todc_direct_write_val;
277#endif
278}
diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h
new file mode 100644
index 000000000000..3e7b4e2c8c57
--- /dev/null
+++ b/arch/ppc/platforms/4xx/sycamore.h
@@ -0,0 +1,67 @@
1/*
2 * arch/ppc/platforms/4xx/sycamore.h
3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC
5 * 405GPr "Sycamore" evaluation board.
6 *
7 * Author: Armin Kuster <akuster@mvista.com>
8 *
9 * 2000 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifdef __KERNEL__
16#ifndef __ASM_SYCAMORE_H__
17#define __ASM_SYCAMORE_H__
18
19#include <platforms/4xx/ibm405gpr.h>
20
21#ifndef __ASSEMBLY__
22/*
23 * Data structure defining board information maintained by the boot
24 * ROM on IBM's "Sycamore" evaluation board. An effort has been made to
25 * keep the field names consistent with the 8xx 'bd_t' board info
26 * structures.
27 */
28
29typedef struct board_info {
30 unsigned char bi_s_version[4]; /* Version of this structure */
31 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
32 unsigned int bi_memsize; /* DRAM installed, in bytes */
33 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
34 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
35 unsigned int bi_intfreq; /* Processor speed, in Hz */
36 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
37 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
38} bd_t;
39
40/* Some 4xx parts use a different timebase frequency from the internal clock.
41*/
42#define bi_tbfreq bi_intfreq
43
44
45/* Memory map for the IBM "Sycamore" 405GP evaluation board.
46 * Generic 4xx plus RTC.
47 */
48
49extern void *sycamore_rtc_base;
50#define SYCAMORE_RTC_PADDR ((uint)0xf0000000)
51#define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR
52#define SYCAMORE_RTC_SIZE ((uint)8*1024)
53
54#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
55#define BASE_BAUD 201600
56#else
57#define BASE_BAUD 691200
58#endif
59
60#define SYCAMORE_PS2_BASE 0xF0100000
61#define SYCAMORE_FPGA_BASE 0xF0300000
62
63#define PPC4xx_MACHINE_NAME "IBM Sycamore"
64
65#endif /* !__ASSEMBLY__ */
66#endif /* __ASM_SYCAMORE_H__ */
67#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.c b/arch/ppc/platforms/4xx/virtex-ii_pro.c
new file mode 100644
index 000000000000..097cc9d5aca0
--- /dev/null
+++ b/arch/ppc/platforms/4xx/virtex-ii_pro.c
@@ -0,0 +1,60 @@
1/*
2 * arch/ppc/platforms/4xx/virtex-ii_pro.c
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is licensed
9 * "as is" without any warranty of any kind, whether express or implied.
10 */
11
12#include <linux/config.h>
13#include <linux/init.h>
14#include <asm/ocp.h>
15#include "virtex-ii_pro.h"
16
17/* Have OCP take care of the serial ports. */
18struct ocp_def core_ocp[] = {
19#ifdef XPAR_UARTNS550_0_BASEADDR
20 { .vendor = OCP_VENDOR_XILINX,
21 .function = OCP_FUNC_16550,
22 .index = 0,
23 .paddr = XPAR_UARTNS550_0_BASEADDR,
24 .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID,
25 .pm = OCP_CPM_NA
26 },
27#ifdef XPAR_UARTNS550_1_BASEADDR
28 { .vendor = OCP_VENDOR_XILINX,
29 .function = OCP_FUNC_16550,
30 .index = 1,
31 .paddr = XPAR_UARTNS550_1_BASEADDR,
32 .irq = XPAR_INTC_0_UARTNS550_1_VEC_ID,
33 .pm = OCP_CPM_NA
34 },
35#ifdef XPAR_UARTNS550_2_BASEADDR
36 { .vendor = OCP_VENDOR_XILINX,
37 .function = OCP_FUNC_16550,
38 .index = 2,
39 .paddr = XPAR_UARTNS550_2_BASEADDR,
40 .irq = XPAR_INTC_0_UARTNS550_2_VEC_ID,
41 .pm = OCP_CPM_NA
42 },
43#ifdef XPAR_UARTNS550_3_BASEADDR
44 { .vendor = OCP_VENDOR_XILINX,
45 .function = OCP_FUNC_16550,
46 .index = 3,
47 .paddr = XPAR_UARTNS550_3_BASEADDR,
48 .irq = XPAR_INTC_0_UARTNS550_3_VEC_ID,
49 .pm = OCP_CPM_NA
50 },
51#ifdef XPAR_UARTNS550_4_BASEADDR
52#error Edit this file to add more devices.
53#endif /* 4 */
54#endif /* 3 */
55#endif /* 2 */
56#endif /* 1 */
57#endif /* 0 */
58 { .vendor = OCP_VENDOR_INVALID
59 }
60};
diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.h b/arch/ppc/platforms/4xx/virtex-ii_pro.h
new file mode 100644
index 000000000000..9014c4887339
--- /dev/null
+++ b/arch/ppc/platforms/4xx/virtex-ii_pro.h
@@ -0,0 +1,99 @@
1/*
2 * arch/ppc/platforms/4xx/virtex-ii_pro.h
3 *
4 * Include file that defines the Xilinx Virtex-II Pro processor
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_VIRTEXIIPRO_H__
16#define __ASM_VIRTEXIIPRO_H__
17
18#include <linux/config.h>
19#include <asm/xparameters.h>
20
21/* serial defines */
22
23#define RS_TABLE_SIZE 4 /* change this and add more devices below
24 if you have more then 4 16x50 UARTs */
25
26#define BASE_BAUD (XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16)
27
28/* The serial ports in the Virtex-II Pro have each I/O byte in the
29 * LSByte of a word. This means that iomem_reg_shift needs to be 2 to
30 * change the byte offsets into word offsets. In addition the base
31 * addresses need to have 3 added to them to get to the LSByte.
32 */
33#define STD_UART_OP(num) \
34 { 0, BASE_BAUD, 0, XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \
35 ASYNC_BOOT_AUTOCONF, \
36 .iomem_base = (u8 *)XPAR_UARTNS550_##num##_BASEADDR + 3, \
37 .iomem_reg_shift = 2, \
38 .io_type = SERIAL_IO_MEM},
39
40#if defined(XPAR_INTC_0_UARTNS550_0_VEC_ID)
41#define ML300_UART0 STD_UART_OP(0)
42#else
43#define ML300_UART0
44#endif
45
46#if defined(XPAR_INTC_0_UARTNS550_1_VEC_ID)
47#define ML300_UART1 STD_UART_OP(1)
48#else
49#define ML300_UART1
50#endif
51
52#if defined(XPAR_INTC_0_UARTNS550_2_VEC_ID)
53#define ML300_UART2 STD_UART_OP(2)
54#else
55#define ML300_UART2
56#endif
57
58#if defined(XPAR_INTC_0_UARTNS550_3_VEC_ID)
59#define ML300_UART3 STD_UART_OP(3)
60#else
61#define ML300_UART3
62#endif
63
64#if defined(XPAR_INTC_0_UARTNS550_4_VEC_ID)
65#error Edit this file to add more devices.
66#elif defined(XPAR_INTC_0_UARTNS550_3_VEC_ID)
67#define NR_SER_PORTS 4
68#elif defined(XPAR_INTC_0_UARTNS550_2_VEC_ID)
69#define NR_SER_PORTS 3
70#elif defined(XPAR_INTC_0_UARTNS550_1_VEC_ID)
71#define NR_SER_PORTS 2
72#elif defined(XPAR_INTC_0_UARTNS550_0_VEC_ID)
73#define NR_SER_PORTS 1
74#else
75#define NR_SER_PORTS 0
76#endif
77
78#if defined(CONFIG_UART0_TTYS0)
79#define SERIAL_PORT_DFNS \
80 ML300_UART0 \
81 ML300_UART1 \
82 ML300_UART2 \
83 ML300_UART3
84#endif
85
86#if defined(CONFIG_UART0_TTYS1)
87#define SERIAL_PORT_DFNS \
88 ML300_UART1 \
89 ML300_UART0 \
90 ML300_UART2 \
91 ML300_UART3
92#endif
93
94#define DCRN_CPMFR_BASE 0
95
96#include <asm/ibm405.h>
97
98#endif /* __ASM_VIRTEXIIPRO_H__ */
99#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c
new file mode 100644
index 000000000000..a33eda4b7489
--- /dev/null
+++ b/arch/ppc/platforms/4xx/walnut.c
@@ -0,0 +1,249 @@
1/*
2 * arch/ppc/platforms/4xx/walnut.c
3 *
4 * Architecture- / platform-specific boot-time initialization code for
5 * IBM PowerPC 4xx based boards. Adapted from original
6 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
7 * <dan@net4x.com>.
8 *
9 * Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
10 *
11 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16#include <linux/config.h>
17#include <linux/init.h>
18#include <linux/smp.h>
19#include <linux/threads.h>
20#include <linux/param.h>
21#include <linux/string.h>
22#include <linux/pci.h>
23#include <linux/rtc.h>
24
25#include <asm/system.h>
26#include <asm/pci-bridge.h>
27#include <asm/machdep.h>
28#include <asm/page.h>
29#include <asm/time.h>
30#include <asm/io.h>
31#include <asm/ocp.h>
32#include <asm/ibm_ocp_pci.h>
33#include <asm/todc.h>
34
35#undef DEBUG
36
37#ifdef DEBUG
38#define DBG(x...) printk(x)
39#else
40#define DBG(x...)
41#endif
42
43void *kb_cs;
44void *kb_data;
45void *walnut_rtc_base;
46
47/* Some IRQs unique to Walnut.
48 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
49 */
50int __init
51ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
52{
53 static char pci_irq_table[][4] =
54 /*
55 * PCI IDSEL/INTPIN->INTLINE
56 * A B C D
57 */
58 {
59 {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
60 {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
61 {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
62 {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
63 };
64
65 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
66 return PCI_IRQ_TABLE_LOOKUP;
67};
68
69void __init
70walnut_setup_arch(void)
71{
72
73 void *fpga_brdc;
74 unsigned char fpga_brdc_data;
75 void *fpga_enable;
76 void *fpga_polarity;
77 void *fpga_status;
78 void *fpga_trigger;
79
80 ppc4xx_setup_arch();
81
82 ibm_ocp_set_emac(0, 0);
83
84 kb_data = ioremap(WALNUT_PS2_BASE, 8);
85 if (!kb_data) {
86 printk(KERN_CRIT
87 "walnut_setup_arch() kb_data ioremap failed\n");
88 return;
89 }
90
91 kb_cs = kb_data + 1;
92
93 fpga_status = ioremap(WALNUT_FPGA_BASE, 8);
94 if (!fpga_status) {
95 printk(KERN_CRIT
96 "walnut_setup_arch() fpga_status ioremap failed\n");
97 return;
98 }
99
100 fpga_enable = fpga_status + 1;
101 fpga_polarity = fpga_status + 2;
102 fpga_trigger = fpga_status + 3;
103 fpga_brdc = fpga_status + 4;
104
105 /* split the keyboard and mouse interrupts */
106 fpga_brdc_data = readb(fpga_brdc);
107 fpga_brdc_data |= 0x80;
108 writeb(fpga_brdc_data, fpga_brdc);
109
110 writeb(0x3, fpga_enable);
111
112 writeb(0x3, fpga_polarity);
113
114 writeb(0x3, fpga_trigger);
115
116 /* RTC step for the walnut */
117 walnut_rtc_base = (void *) WALNUT_RTC_VADDR;
118 TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base,
119 walnut_rtc_base, 8);
120 /* Identify the system */
121 printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. (source@mvista.com)\n");
122}
123
124void __init
125bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
126{
127#ifdef CONFIG_PCI
128 unsigned int bar_response, bar;
129 /*
130 * Expected PCI mapping:
131 *
132 * PLB addr PCI memory addr
133 * --------------------- ---------------------
134 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
135 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
136 *
137 * PLB addr PCI io addr
138 * --------------------- ---------------------
139 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
140 *
141 * The following code is simplified by assuming that the bootrom
142 * has been well behaved in following this mapping.
143 */
144
145#ifdef DEBUG
146 int i;
147
148 printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
149 printk("PCI bridge regs before fixup \n");
150 for (i = 0; i <= 3; i++) {
151 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
152 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
153 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
154 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
155 }
156 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
157 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
158 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
159 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
160
161#endif
162
163 /* added for IBM boot rom version 1.15 bios bar changes -AK */
164
165 /* Disable region first */
166 out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
167 /* PLB starting addr, PCI: 0x80000000 */
168 out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
169 /* PCI start addr, 0x80000000 */
170 out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
171 /* 512MB range of PLB to PCI */
172 out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
173 /* Enable no pre-fetch, enable region */
174 out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
175 (PPC405_PCI_UPPER_MEM -
176 PPC405_PCI_MEM_BASE)) | 0x01));
177
178 /* Disable region one */
179 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
180 out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
181 out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
182 out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
183 out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
184 out_le32((void *) &(pcip->ptm1ms), 0x00000000);
185
186 /* Disable region two */
187 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
188 out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
189 out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
190 out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
191 out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
192 out_le32((void *) &(pcip->ptm2ms), 0x00000000);
193
194 /* Zero config bars */
195 for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
196 early_write_config_dword(hose, hose->first_busno,
197 PCI_FUNC(hose->first_busno), bar,
198 0x00000000);
199 early_read_config_dword(hose, hose->first_busno,
200 PCI_FUNC(hose->first_busno), bar,
201 &bar_response);
202 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
203 hose->first_busno, PCI_SLOT(hose->first_busno),
204 PCI_FUNC(hose->first_busno), bar, bar_response);
205 }
206 /* end work arround */
207
208#ifdef DEBUG
209 printk("PCI bridge regs after fixup \n");
210 for (i = 0; i <= 3; i++) {
211 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
212 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
213 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
214 printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
215 }
216 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
217 printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
218 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
219 printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
220
221#endif
222#endif
223}
224
225void __init
226walnut_map_io(void)
227{
228 ppc4xx_map_io();
229 io_block_mapping(WALNUT_RTC_VADDR,
230 WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO);
231}
232
233void __init
234platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
235 unsigned long r6, unsigned long r7)
236{
237 ppc4xx_init(r3, r4, r5, r6, r7);
238
239 ppc_md.setup_arch = walnut_setup_arch;
240 ppc_md.setup_io_mappings = walnut_map_io;
241
242#ifdef CONFIG_GEN_RTC
243 ppc_md.time_init = todc_time_init;
244 ppc_md.set_rtc_time = todc_set_rtc_time;
245 ppc_md.get_rtc_time = todc_get_rtc_time;
246 ppc_md.nvram_read_val = todc_direct_read_val;
247 ppc_md.nvram_write_val = todc_direct_write_val;
248#endif
249}
diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h
new file mode 100644
index 000000000000..04cfbf3696b9
--- /dev/null
+++ b/arch/ppc/platforms/4xx/walnut.h
@@ -0,0 +1,72 @@
1/*
2 * arch/ppc/platforms/4xx/walnut.h
3 *
4 * Macros, definitions, and data structures specific to the IBM PowerPC
5 * 405GP "Walnut" evaluation board.
6 *
7 * Authors: Grant Erickson <grant@lcse.umn.edu>, Frank Rowand
8 * <frank_rowand@mvista.com>, Debbie Chu <debbie_chu@mvista.com> or
9 * source@mvista.com
10 *
11 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
12 *
13 * 2000 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
16 * or implied.
17 */
18
19#ifdef __KERNEL__
20#ifndef __ASM_WALNUT_H__
21#define __ASM_WALNUT_H__
22
23/* We have a 405GP core */
24#include <platforms/4xx/ibm405gp.h>
25
26#ifndef __ASSEMBLY__
27/*
28 * Data structure defining board information maintained by the boot
29 * ROM on IBM's "Walnut" evaluation board. An effort has been made to
30 * keep the field names consistent with the 8xx 'bd_t' board info
31 * structures.
32 */
33
34typedef struct board_info {
35 unsigned char bi_s_version[4]; /* Version of this structure */
36 unsigned char bi_r_version[30]; /* Version of the IBM ROM */
37 unsigned int bi_memsize; /* DRAM installed, in bytes */
38 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
39 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
40 unsigned int bi_intfreq; /* Processor speed, in Hz */
41 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
42 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
43} bd_t;
44
45/* Some 4xx parts use a different timebase frequency from the internal clock.
46*/
47#define bi_tbfreq bi_intfreq
48
49
50/* Memory map for the IBM "Walnut" 405GP evaluation board.
51 * Generic 4xx plus RTC.
52 */
53
54extern void *walnut_rtc_base;
55#define WALNUT_RTC_PADDR ((uint)0xf0000000)
56#define WALNUT_RTC_VADDR WALNUT_RTC_PADDR
57#define WALNUT_RTC_SIZE ((uint)8*1024)
58
59#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
60#define BASE_BAUD 201600
61#else
62#define BASE_BAUD 691200
63#endif
64
65#define WALNUT_PS2_BASE 0xF0100000
66#define WALNUT_FPGA_BASE 0xF0300000
67
68#define PPC4xx_MACHINE_NAME "IBM Walnut"
69
70#endif /* !__ASSEMBLY__ */
71#endif /* __ASM_WALNUT_H__ */
72#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c
new file mode 100644
index 000000000000..0b1b77d986bf
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xilinx_ml300.c
@@ -0,0 +1,146 @@
1/*
2 * arch/ppc/platforms/4xx/xilinx_ml300.c
3 *
4 * Xilinx ML300 evaluation board initialization
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/tty.h>
18#include <linux/serial.h>
19#include <linux/serial_core.h>
20#include <linux/serialP.h>
21#include <asm/io.h>
22#include <asm/machdep.h>
23#include <asm/ocp.h>
24
25#include <platforms/4xx/virtex-ii_pro.h> /* for NR_SER_PORTS */
26
27/*
28 * As an overview of how the following functions (platform_init,
29 * ml300_map_io, ml300_setup_arch and ml300_init_IRQ) fit into the
30 * kernel startup procedure, here's a call tree:
31 *
32 * start_here arch/ppc/kernel/head_4xx.S
33 * early_init arch/ppc/kernel/setup.c
34 * machine_init arch/ppc/kernel/setup.c
35 * platform_init this file
36 * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c
37 * parse_bootinfo
38 * find_bootinfo
39 * "setup some default ppc_md pointers"
40 * MMU_init arch/ppc/mm/init.c
41 * *ppc_md.setup_io_mappings == ml300_map_io this file
42 * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c
43 * start_kernel init/main.c
44 * setup_arch arch/ppc/kernel/setup.c
45 * #if defined(CONFIG_KGDB)
46 * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
47 * #endif
48 * *ppc_md.setup_arch == ml300_setup_arch this file
49 * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c
50 * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c
51 * init_IRQ arch/ppc/kernel/irq.c
52 * *ppc_md.init_IRQ == ml300_init_IRQ this file
53 * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c
54 * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c
55 */
56
57#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
58
59static volatile unsigned *powerdown_base =
60 (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
61
62static void
63xilinx_power_off(void)
64{
65 local_irq_disable();
66 out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
67 while (1) ;
68}
69#endif
70
71void __init
72ml300_map_io(void)
73{
74 ppc4xx_map_io();
75
76#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
77 powerdown_base = ioremap((unsigned long) powerdown_base,
78 XPAR_POWER_0_POWERDOWN_HIGHADDR -
79 XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
80#endif
81}
82
83static void __init
84ml300_early_serial_map(void)
85{
86#ifdef CONFIG_SERIAL_8250
87 struct serial_state old_ports[] = { SERIAL_PORT_DFNS };
88 struct uart_port port;
89 int i;
90
91 /* Setup ioremapped serial port access */
92 for (i = 0; i < ARRAY_SIZE(old_ports); i++ ) {
93 memset(&port, 0, sizeof(port));
94 port.membase = ioremap((phys_addr_t)(old_ports[i].iomem_base), 16);
95 port.irq = old_ports[i].irq;
96 port.uartclk = old_ports[i].baud_base * 16;
97 port.regshift = old_ports[i].iomem_reg_shift;
98 port.iotype = SERIAL_IO_MEM;
99 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
100 port.line = i;
101
102 if (early_serial_setup(&port) != 0) {
103 printk("Early serial init of port %d failed\n", i);
104 }
105 }
106#endif /* CONFIG_SERIAL_8250 */
107}
108
109void __init
110ml300_setup_arch(void)
111{
112 ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */
113
114 ml300_early_serial_map();
115
116 /* Identify the system */
117 printk(KERN_INFO "Xilinx Virtex-II Pro port\n");
118 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
119}
120
121/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
122void __init
123ml300_init_irq(void)
124{
125 ppc4xx_init_IRQ();
126}
127
128void __init
129platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
130 unsigned long r6, unsigned long r7)
131{
132 ppc4xx_init(r3, r4, r5, r6, r7);
133
134 ppc_md.setup_arch = ml300_setup_arch;
135 ppc_md.setup_io_mappings = ml300_map_io;
136 ppc_md.init_IRQ = ml300_init_irq;
137
138#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
139 ppc_md.power_off = xilinx_power_off;
140#endif
141
142#ifdef CONFIG_KGDB
143 ppc_md.early_serial_map = ml300_early_serial_map;
144#endif
145}
146
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.h b/arch/ppc/platforms/4xx/xilinx_ml300.h
new file mode 100644
index 000000000000..f8c588412336
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xilinx_ml300.h
@@ -0,0 +1,47 @@
1/*
2 * arch/ppc/platforms/4xx/xilinx_ml300.h
3 *
4 * Include file that defines the Xilinx ML300 evaluation board
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_XILINX_ML300_H__
16#define __ASM_XILINX_ML300_H__
17
18/* ML300 has a Xilinx Virtex-II Pro processor */
19#include <platforms/4xx/virtex-ii_pro.h>
20
21#ifndef __ASSEMBLY__
22
23#include <linux/types.h>
24
25typedef struct board_info {
26 unsigned int bi_memsize; /* DRAM installed, in bytes */
27 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
28 unsigned int bi_intfreq; /* Processor speed, in Hz */
29 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
30 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
31} bd_t;
32
33/* Some 4xx parts use a different timebase frequency from the internal clock.
34*/
35#define bi_tbfreq bi_intfreq
36
37#endif /* !__ASSEMBLY__ */
38
39/* We don't need anything mapped. Size of zero will accomplish that. */
40#define PPC4xx_ONB_IO_PADDR 0u
41#define PPC4xx_ONB_IO_VADDR 0u
42#define PPC4xx_ONB_IO_SIZE 0u
43
44#define PPC4xx_MACHINE_NAME "Xilinx ML300"
45
46#endif /* __ASM_XILINX_ML300_H__ */
47#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
new file mode 100644
index 000000000000..97e3f4d4bd54
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
@@ -0,0 +1,310 @@
1/*******************************************************************
2*
3* Author: Xilinx, Inc.
4*
5*
6* This program is free software; you can redistribute it and/or modify it
7* under the terms of the GNU General Public License as published by the
8* Free Software Foundation; either version 2 of the License, or (at your
9* option) any later version.
10*
11*
12* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
13* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
14* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
15* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
16* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
17* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
18* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
19* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
20* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
21* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
22* FITNESS FOR A PARTICULAR PURPOSE.
23*
24*
25* Xilinx hardware products are not intended for use in life support
26* appliances, devices, or systems. Use in such applications is
27* expressly prohibited.
28*
29*
30* (c) Copyright 2002-2004 Xilinx Inc.
31* All rights reserved.
32*
33*
34* You should have received a copy of the GNU General Public License along
35* with this program; if not, write to the Free Software Foundation, Inc.,
36* 675 Mass Ave, Cambridge, MA 02139, USA.
37*
38* Description: Driver parameters
39*
40*******************************************************************/
41
42#define XPAR_XPCI_NUM_INSTANCES 1
43#define XPAR_XPCI_CLOCK_HZ 33333333
44#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0
45#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000
46#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF
47#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000
48#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004
49#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000
50#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000
51#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF
52#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000
53#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF
54
55/******************************************************************/
56
57#define XPAR_XEMAC_NUM_INSTANCES 1
58#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
59#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
60#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
61#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
62#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
63#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
64
65/******************************************************************/
66
67#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0
68#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000
69#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7)
70#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1
71#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8)
72#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F)
73#define XPAR_XGPIO_NUM_INSTANCES 2
74
75/******************************************************************/
76
77#define XPAR_XIIC_NUM_INSTANCES 1
78#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
79#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
80#define XPAR_OPB_IIC_0_DEVICE_ID 0
81#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
82
83/******************************************************************/
84
85#define XPAR_XUARTNS550_NUM_INSTANCES 2
86#define XPAR_XUARTNS550_CLOCK_HZ 100000000
87#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
88#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
89#define XPAR_OPB_UART16550_0_DEVICE_ID 0
90#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000
91#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF
92#define XPAR_OPB_UART16550_1_DEVICE_ID 1
93
94/******************************************************************/
95
96#define XPAR_XSPI_NUM_INSTANCES 1
97#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000
98#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F
99#define XPAR_OPB_SPI_0_DEVICE_ID 0
100#define XPAR_OPB_SPI_0_FIFO_EXIST 1
101#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0
102#define XPAR_OPB_SPI_0_NUM_SS_BITS 1
103
104/******************************************************************/
105
106#define XPAR_XPS2_NUM_INSTANCES 2
107#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
108#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
109#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
110#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
111#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
112#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
113
114/******************************************************************/
115
116#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
117#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000
118#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007
119#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0
120
121/******************************************************************/
122
123#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
124#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
125#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000
126#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF
127#define XPAR_PLB_DDR_0_BASEADDR 0x00000000
128#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF
129
130/******************************************************************/
131
132#define XPAR_XINTC_HAS_IPR 1
133#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18
134#define XPAR_XINTC_USE_DCR 0
135#define XPAR_XINTC_NUM_INSTANCES 1
136#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0
137#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF
138#define XPAR_DCR_INTC_0_DEVICE_ID 0
139#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000
140
141/******************************************************************/
142
143#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0
144#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1
145#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2
146#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3
147#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4
148#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5
149#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6
150#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7
151#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
152#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9
153#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10
154#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11
155#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12
156#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13
157#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14
158#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15
159#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16
160#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17
161
162/******************************************************************/
163
164#define XPAR_XTFT_NUM_INSTANCES 1
165#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
166#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
167#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
168
169/******************************************************************/
170
171#define XPAR_XSYSACE_MEM_WIDTH 8
172#define XPAR_XSYSACE_NUM_INSTANCES 1
173#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
174#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
175#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
176#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8
177
178/******************************************************************/
179
180#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
181
182/******************************************************************/
183
184/******************************************************************/
185
186/* Linux Redefines */
187
188/******************************************************************/
189
190#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
191#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
192#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
193#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
194#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000)
195#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR
196#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
197#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID
198
199/******************************************************************/
200
201#define XPAR_GPIO_0_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_0
202#define XPAR_GPIO_0_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_0
203#define XPAR_GPIO_0_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_0
204#define XPAR_GPIO_1_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_1
205#define XPAR_GPIO_1_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_1
206#define XPAR_GPIO_1_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_1
207
208/******************************************************************/
209
210#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
211#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
212#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
213#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
214
215/******************************************************************/
216
217#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
218#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
219#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
220
221/******************************************************************/
222
223#define XPAR_INTC_0_BASEADDR XPAR_DCR_INTC_0_BASEADDR
224#define XPAR_INTC_0_HIGHADDR XPAR_DCR_INTC_0_HIGHADDR
225#define XPAR_INTC_0_KIND_OF_INTR XPAR_DCR_INTC_0_KIND_OF_INTR
226#define XPAR_INTC_0_DEVICE_ID XPAR_DCR_INTC_0_DEVICE_ID
227
228/******************************************************************/
229
230#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
231#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
232#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
233#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
234#define XPAR_INTC_0_UARTNS550_1_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR
235#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
236#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
237#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR
238#define XPAR_INTC_0_TOUCHSCREEN_0_VEC_ID XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR
239#define XPAR_INTC_0_PCI_0_VEC_ID_A XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
240#define XPAR_INTC_0_PCI_0_VEC_ID_B XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
241#define XPAR_INTC_0_PCI_0_VEC_ID_C XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
242#define XPAR_INTC_0_PCI_0_VEC_ID_D XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
243
244/******************************************************************/
245
246#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
247#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
248#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
249#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
250#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
251#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
252
253/******************************************************************/
254
255#define XPAR_SPI_0_BASEADDR XPAR_OPB_SPI_0_BASEADDR
256#define XPAR_SPI_0_HIGHADDR XPAR_OPB_SPI_0_HIGHADDR
257#define XPAR_SPI_0_DEVICE_ID XPAR_OPB_SPI_0_DEVICE_ID
258
259/******************************************************************/
260
261#define XPAR_TOUCHSCREEN_0_BASEADDR XPAR_OPB_TSD_REF_0_BASEADDR
262#define XPAR_TOUCHSCREEN_0_HIGHADDR XPAR_OPB_TSD_REF_0_HIGHADDR
263#define XPAR_TOUCHSCREEN_0_DEVICE_ID XPAR_OPB_TSD_REF_0_DEVICE_ID
264
265/******************************************************************/
266
267#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
268
269/******************************************************************/
270
271#define XPAR_PCI_0_BASEADDR XPAR_OPB_PCI_REF_0_BASEADDR
272#define XPAR_PCI_0_HIGHADDR XPAR_OPB_PCI_REF_0_HIGHADDR
273#define XPAR_PCI_0_CONFIG_ADDR XPAR_OPB_PCI_REF_0_CONFIG_ADDR
274#define XPAR_PCI_0_CONFIG_DATA XPAR_OPB_PCI_REF_0_CONFIG_DATA
275#define XPAR_PCI_0_LCONFIG_ADDR XPAR_OPB_PCI_REF_0_LCONFIG_ADDR
276#define XPAR_PCI_0_MEM_BASEADDR XPAR_OPB_PCI_REF_0_MEM_BASEADDR
277#define XPAR_PCI_0_MEM_HIGHADDR XPAR_OPB_PCI_REF_0_MEM_HIGHADDR
278#define XPAR_PCI_0_IO_BASEADDR XPAR_OPB_PCI_REF_0_IO_BASEADDR
279#define XPAR_PCI_0_IO_HIGHADDR XPAR_OPB_PCI_REF_0_IO_HIGHADDR
280#define XPAR_PCI_0_CLOCK_FREQ_HZ XPAR_XPCI_CLOCK_HZ
281#define XPAR_PCI_0_DEVICE_ID XPAR_OPB_PCI_REF_0_DEVICE_ID
282
283/******************************************************************/
284
285#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
286#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
287#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
288#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
289#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
290#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
291
292/******************************************************************/
293
294#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
295#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
296#define XPAR_DDR_0_SIZE 0x08000000
297
298/******************************************************************/
299
300#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
301#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
302#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
303
304/******************************************************************/
305
306#define XPAR_POWER_0_POWERDOWN_BASEADDR 0x90000004
307#define XPAR_POWER_0_POWERDOWN_HIGHADDR 0x90000007
308#define XPAR_POWER_0_POWERDOWN_VALUE 0xFF
309
310/******************************************************************/
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 18:47:52 -0500