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authorStefan Roese <sr@denx.de>2007-03-16 16:06:00 -0400
committerPaul Mackerras <paulus@samba.org>2007-03-25 22:35:11 -0400
commitec5f77e789a02adf7c45f03a76455b4e71ae1c5b (patch)
treef52a07dbd3ba810d16cd645950159a62c4c70d70 /arch/ppc/platforms/4xx
parentf6f7dde3f778b318aca71220834482d4ea2d7738 (diff)
[POWERPC] ppc: Fix PCIX configuration of Ocotea & Taishan for > 512MB DDR
Change the configuration of the PCIX PCI->PLB inbound memory window to be 2GB instead of 512kB. The comment already mentioned 2GB, but the code unfortunately didn't reflect this. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/platforms/4xx')
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c2
-rw-r--r--arch/ppc/platforms/4xx/taishan.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index 84e999d9a7bb..c8017c9f1326 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -178,7 +178,7 @@ ocotea_setup_pcix(void)
178 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ 178 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
179 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); 179 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
180 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); 180 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
181 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA); 181 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
182 182
183 eieio(); 183 eieio();
184} 184}
diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c
index bb0253eef45a..5d9af8ddb155 100644
--- a/arch/ppc/platforms/4xx/taishan.c
+++ b/arch/ppc/platforms/4xx/taishan.c
@@ -235,7 +235,7 @@ taishan_setup_pcix(void)
235 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ 235 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
236 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); 236 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
237 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); 237 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
238 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA); 238 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
239 PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH); 239 PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
240 240
241 iounmap(pcix_reg_base); 241 iounmap(pcix_reg_base);