[PATCH] ppc32: Add 440SPe support

Add support for the AMCC PowerPC 440SPe SoC, including PCI Express in root
port mode.

Signed-off-by: Roland Dreier <rolandd@cisco.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

4 files changed, 221 insertions, 2 deletions

diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index 76f4476cab44..108d5a730f84 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -124,9 +124,13 @@ config 440SP
         depends on LUAN
         default y
 
+config 440SPE
+        bool
+        default n
+
 config 440
         bool
-        depends on 440GP || 440SP || 440EP
+        depends on 440GP || 440SP || 440SPE || 440EP
         default y
 
 config 440A
@@ -168,7 +172,7 @@ config XILINX_OCP
 
 config IBM_EMAC4
         bool
-        depends on 440GX || 440SP
+        depends on 440GX || 440SP || 440SPE
         default y
 
 config BIOS_FIXUP
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index 1dd6d7fd6a9a..694accdb59f7 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_440EP)		+= ibm440ep.o
 obj-$(CONFIG_440GP)             += ibm440gp.o
 obj-$(CONFIG_440GX)             += ibm440gx.o
 obj-$(CONFIG_440SP)             += ibm440sp.o
+obj-$(CONFIG_440SPE)            += ppc440spe.o
 obj-$(CONFIG_405EP)             += ibm405ep.o
 obj-$(CONFIG_405GPR)            += ibm405gpr.o
 obj-$(CONFIG_VIRTEX_II_PRO)     += virtex-ii_pro.o
diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c
new file mode 100644
index 000000000000..6139a0b3393e
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ppc440spe.c
@@ -0,0 +1,148 @@
+/*
+ * arch/ppc/platforms/4xx/ppc440spe.c
+ *
+ * PPC440SPe I/O descriptions
+ *
+ * Roland Dreier <rolandd@cisco.com>
+ * Copyright (c) 2005 Cisco Systems.  All rights reserved.
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2002-2005 MontaVista Software Inc.
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003, 2004 Zultys Technologies
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <platforms/4xx/ppc440spe.h>
+#include <asm/ocp.h>
+#include <asm/ppc4xx_pic.h>
+
+static struct ocp_func_emac_data ppc440spe_emac0_def = {
+        .rgmii_idx      = -1,           /* No RGMII */
+        .rgmii_mux      = -1,           /* No RGMII */
+        .zmii_idx       = -1,           /* No ZMII */
+        .zmii_mux       = -1,           /* No ZMII */
+        .mal_idx        = 0,            /* MAL device index */
+        .mal_rx_chan    = 0,            /* MAL rx channel number */
+        .mal_tx_chan    = 0,            /* MAL tx channel number */
+        .wol_irq        = 61,           /* WOL interrupt number */
+        .mdio_idx       = -1,           /* No shared MDIO */
+        .tah_idx        = -1,           /* No TAH */
+};
+OCP_SYSFS_EMAC_DATA()
+
+static struct ocp_func_mal_data ppc440spe_mal0_def = {
+        .num_tx_chans   = 1,            /* Number of TX channels */
+        .num_rx_chans   = 1,            /* Number of RX channels */
+        .txeob_irq      = 38,           /* TX End Of Buffer IRQ  */
+        .rxeob_irq      = 39,           /* RX End Of Buffer IRQ  */
+        .txde_irq       = 34,           /* TX Descriptor Error IRQ */
+        .rxde_irq       = 35,           /* RX Descriptor Error IRQ */
+        .serr_irq       = 33,           /* MAL System Error IRQ    */
+        .dcr_base       = DCRN_MAL_BASE /* MAL0_CFG DCR number */
+};
+OCP_SYSFS_MAL_DATA()
+
+static struct ocp_func_iic_data ppc440spe_iic0_def = {
+        .fast_mode      = 0,            /* Use standad mode (100Khz) */
+};
+
+static struct ocp_func_iic_data ppc440spe_iic1_def = {
+        .fast_mode      = 0,            /* Use standad mode (100Khz) */
+};
+OCP_SYSFS_IIC_DATA()
+
+struct ocp_def core_ocp[] = {
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_16550,
+          .index        = 0,
+          .paddr        = PPC440SPE_UART0_ADDR,
+          .irq          = UART0_INT,
+          .pm           = IBM_CPM_UART0,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_16550,
+          .index        = 1,
+          .paddr        = PPC440SPE_UART1_ADDR,
+          .irq          = UART1_INT,
+          .pm           = IBM_CPM_UART1,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_16550,
+          .index        = 2,
+          .paddr        = PPC440SPE_UART2_ADDR,
+          .irq          = UART2_INT,
+          .pm           = IBM_CPM_UART2,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_IIC,
+          .index        = 0,
+          .paddr        = 0x00000004f0000400ULL,
+          .irq          = 2,
+          .pm           = IBM_CPM_IIC0,
+          .additions    = &ppc440spe_iic0_def,
+          .show         = &ocp_show_iic_data
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_IIC,
+          .index        = 1,
+          .paddr        = 0x00000004f0000500ULL,
+          .irq          = 3,
+          .pm           = IBM_CPM_IIC1,
+          .additions    = &ppc440spe_iic1_def,
+          .show         = &ocp_show_iic_data
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_GPIO,
+          .index        = 0,
+          .paddr        = 0x00000004f0000700ULL,
+          .irq          = OCP_IRQ_NA,
+          .pm           = IBM_CPM_GPIO0,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_MAL,
+          .paddr        = OCP_PADDR_NA,
+          .irq          = OCP_IRQ_NA,
+          .pm           = OCP_CPM_NA,
+          .additions    = &ppc440spe_mal0_def,
+          .show         = &ocp_show_mal_data,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_EMAC,
+          .index        = 0,
+          .paddr        = 0x00000004f0000800ULL,
+          .irq          = 60,
+          .pm           = OCP_CPM_NA,
+          .additions    = &ppc440spe_emac0_def,
+          .show         = &ocp_show_emac_data,
+        },
+        { .vendor       = OCP_VENDOR_INVALID
+        }
+};
+
+/* Polarity and triggering settings for internal interrupt sources */
+struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
+        { .polarity     = 0xffffffff,
+          .triggering   = 0x010f0004,
+          .ext_irq_mask = 0x00000000,
+        },
+        { .polarity     = 0xffffffff,
+          .triggering   = 0x001f8040,
+          .ext_irq_mask = 0x00007c30,   /* IRQ6 - IRQ7, IRQ8 - IRQ12 */
+        },
+        { .polarity     = 0xffffffff,
+          .triggering   = 0x00000000,
+          .ext_irq_mask = 0x000000fc,   /* IRQ0 - IRQ5 */
+        },
+        { .polarity     = 0xffffffff,
+          .triggering   = 0x00000000,
+          .ext_irq_mask = 0x00000000,
+        },
+};
diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h
new file mode 100644
index 000000000000..2216846973b8
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ppc440spe.h
@@ -0,0 +1,66 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440spe.h
+ *
+ * PPC440SPe definitions
+ *
+ * Roland Dreier <rolandd@cisco.com>
+ * Copyright (c) 2005 Cisco Systems.  All rights reserved.
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2004-2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __PPC_PLATFORMS_PPC440SPE_H
+#define __PPC_PLATFORMS_PPC440SPE_H
+
+#include <linux/config.h>
+
+#include <asm/ibm44x.h>
+
+/* UART */
+#define PPC440SPE_UART0_ADDR    0x00000004f0000200ULL
+#define PPC440SPE_UART1_ADDR    0x00000004f0000300ULL
+#define PPC440SPE_UART2_ADDR    0x00000004f0000600ULL
+#define UART0_INT               0
+#define UART1_INT               1
+#define UART2_INT               37
+
+/* Clock and Power Management */
+#define IBM_CPM_IIC0            0x80000000      /* IIC interface */
+#define IBM_CPM_IIC1            0x40000000      /* IIC interface */
+#define IBM_CPM_PCI             0x20000000      /* PCI bridge */
+#define IBM_CPM_CPU                 0x02000000  /* processor core */
+#define IBM_CPM_DMA                 0x01000000  /* DMA controller */
+#define IBM_CPM_BGO                 0x00800000  /* PLB to OPB bus arbiter */
+#define IBM_CPM_BGI                 0x00400000  /* OPB to PLB bridge */
+#define IBM_CPM_EBC                 0x00200000  /* External Bux Controller */
+#define IBM_CPM_EBM                 0x00100000  /* Ext Bus Master Interface */
+#define IBM_CPM_DMC                 0x00080000  /* SDRAM peripheral controller */
+#define IBM_CPM_PLB                 0x00040000  /* PLB bus arbiter */
+#define IBM_CPM_SRAM            0x00020000      /* SRAM memory controller */
+#define IBM_CPM_PPM                 0x00002000  /* PLB Performance Monitor */
+#define IBM_CPM_UIC1            0x00001000      /* Universal Interrupt Controller */
+#define IBM_CPM_GPIO0           0x00000800      /* General Purpose IO (??) */
+#define IBM_CPM_GPT                 0x00000400  /* General Purpose Timers  */
+#define IBM_CPM_UART0           0x00000200      /* serial port 0 */
+#define IBM_CPM_UART1           0x00000100      /* serial port 1 */
+#define IBM_CPM_UART2           0x00000100      /* serial port 1 */
+#define IBM_CPM_UIC0            0x00000080      /* Universal Interrupt Controller */
+#define IBM_CPM_TMRCLK          0x00000040      /* CPU timers */
+#define IBM_CPM_EMAC0           0x00000020      /* EMAC 0     */
+
+#define DFLT_IBM4xx_PM          ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
+                                | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
+                                | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
+                                | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
+                                | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
+                                | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
+                                | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
+#endif /* __PPC_PLATFORMS_PPC440SP_H */
+#endif /* __KERNEL__ */