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authorEugene Surovegin <ebs@ebshome.net>2005-07-30 01:59:19 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-07-30 13:14:46 -0400
commit5ce17b18e16177dd6409dabd38df5c2c9b58fc2d (patch)
treecbc4e6bac2af443d9c2746c260275fc0b4d9c70b /arch/ppc/platforms/4xx
parente310fd43256b3cf4d37f6447b8f7413ca744657a (diff)
[PATCH] ppc32: fix 44x early serial debug for configurations with more than 512M of RAM
Fix 44x early serial debugging for big RAM configurations (more than 512M). We cannot use default OpenBIOS virtual mapping, because it interferes with pinned TLB entry. While we are at it, move early UART mapping to TLB slot 0, so it can survive longer during boot process (slot 1 is used by the first ioremap call, effectively killing UART mapping if it occupies this slot). Also, change UART TLB entry size to 4K (256M is too much for a bunch of registers :). Squash some warnings on the way. Tested on Ebony and Ocotea with 1G of RAM. Thanks to Scott Coulter <scott.coulter@cyclone.com> for diagnosing this problem. Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/platforms/4xx')
-rw-r--r--arch/ppc/platforms/4xx/ebony.c6
-rw-r--r--arch/ppc/platforms/4xx/ebony.h13
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c4
-rw-r--r--arch/ppc/platforms/4xx/ocotea.h13
4 files changed, 31 insertions, 5 deletions
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
index cd11734ef7c5..509e69a095f0 100644
--- a/arch/ppc/platforms/4xx/ebony.c
+++ b/arch/ppc/platforms/4xx/ebony.c
@@ -7,7 +7,7 @@
7 * Copyright 2002-2005 MontaVista Software Inc. 7 * Copyright 2002-2005 MontaVista Software Inc.
8 * 8 *
9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 9 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
10 * Copyright (c) 2003, 2004 Zultys Technologies 10 * Copyright (c) 2003-2005 Zultys Technologies
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
@@ -50,6 +50,7 @@
50#include <asm/bootinfo.h> 50#include <asm/bootinfo.h>
51#include <asm/ppc4xx_pic.h> 51#include <asm/ppc4xx_pic.h>
52#include <asm/ppcboot.h> 52#include <asm/ppcboot.h>
53#include <asm/tlbflush.h>
53 54
54#include <syslib/gen550.h> 55#include <syslib/gen550.h>
55#include <syslib/ibm440gp_common.h> 56#include <syslib/ibm440gp_common.h>
@@ -248,6 +249,9 @@ ebony_early_serial_map(void)
248#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 249#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
249 /* Configure debug serial access */ 250 /* Configure debug serial access */
250 gen550_init(0, &port); 251 gen550_init(0, &port);
252
253 /* Purge TLB entry added in head_44x.S for early serial access */
254 _tlbie(UART0_IO_BASE);
251#endif 255#endif
252 256
253 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8); 257 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
index 47c391c9174d..d08faa46a0ae 100644
--- a/arch/ppc/platforms/4xx/ebony.h
+++ b/arch/ppc/platforms/4xx/ebony.h
@@ -56,9 +56,18 @@
56 * Serial port defines 56 * Serial port defines
57 */ 57 */
58 58
59/* OpenBIOS defined UART mappings, used before early_serial_setup */ 59#if defined(__BOOTER__)
60/* OpenBIOS defined UART mappings, used by bootloader shim */
60#define UART0_IO_BASE 0xE0000200 61#define UART0_IO_BASE 0xE0000200
61#define UART1_IO_BASE 0xE0000300 62#define UART1_IO_BASE 0xE0000300
63#else
64/* head_44x.S created UART mapping, used before early_serial_setup.
65 * We cannot use default OpenBIOS UART mappings because they
66 * don't work for configurations with more than 512M RAM. --ebs
67 */
68#define UART0_IO_BASE 0xF0000200
69#define UART1_IO_BASE 0xF0000300
70#endif
62 71
63/* external Epson SG-615P */ 72/* external Epson SG-615P */
64#define BASE_BAUD 691200 73#define BASE_BAUD 691200
@@ -66,7 +75,7 @@
66#define STD_UART_OP(num) \ 75#define STD_UART_OP(num) \
67 { 0, BASE_BAUD, 0, UART##num##_INT, \ 76 { 0, BASE_BAUD, 0, UART##num##_INT, \
68 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 77 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
69 iomem_base: UART##num##_IO_BASE, \ 78 iomem_base: (void*)UART##num##_IO_BASE, \
70 io_type: SERIAL_IO_MEM}, 79 io_type: SERIAL_IO_MEM},
71 80
72#define SERIAL_PORT_DFNS \ 81#define SERIAL_PORT_DFNS \
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index 5f82a6bc7046..8fc34a344769 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -48,6 +48,7 @@
48#include <asm/bootinfo.h> 48#include <asm/bootinfo.h>
49#include <asm/ppc4xx_pic.h> 49#include <asm/ppc4xx_pic.h>
50#include <asm/ppcboot.h> 50#include <asm/ppcboot.h>
51#include <asm/tlbflush.h>
51 52
52#include <syslib/gen550.h> 53#include <syslib/gen550.h>
53#include <syslib/ibm440gx_common.h> 54#include <syslib/ibm440gx_common.h>
@@ -266,6 +267,9 @@ ocotea_early_serial_map(void)
266#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) 267#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
267 /* Configure debug serial access */ 268 /* Configure debug serial access */
268 gen550_init(0, &port); 269 gen550_init(0, &port);
270
271 /* Purge TLB entry added in head_44x.S for early serial access */
272 _tlbie(UART0_IO_BASE);
269#endif 273#endif
270 274
271 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); 275 port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
index 202dc8251190..33251153ac5f 100644
--- a/arch/ppc/platforms/4xx/ocotea.h
+++ b/arch/ppc/platforms/4xx/ocotea.h
@@ -55,15 +55,24 @@
55 */ 55 */
56#define RS_TABLE_SIZE 2 56#define RS_TABLE_SIZE 2
57 57
58/* OpenBIOS defined UART mappings, used before early_serial_setup */ 58#if defined(__BOOTER__)
59/* OpenBIOS defined UART mappings, used by bootloader shim */
59#define UART0_IO_BASE 0xE0000200 60#define UART0_IO_BASE 0xE0000200
60#define UART1_IO_BASE 0xE0000300 61#define UART1_IO_BASE 0xE0000300
62#else
63/* head_44x.S created UART mapping, used before early_serial_setup.
64 * We cannot use default OpenBIOS UART mappings because they
65 * don't work for configurations with more than 512M RAM. --ebs
66 */
67#define UART0_IO_BASE 0xF0000200
68#define UART1_IO_BASE 0xF0000300
69#endif
61 70
62#define BASE_BAUD 11059200/16 71#define BASE_BAUD 11059200/16
63#define STD_UART_OP(num) \ 72#define STD_UART_OP(num) \
64 { 0, BASE_BAUD, 0, UART##num##_INT, \ 73 { 0, BASE_BAUD, 0, UART##num##_INT, \
65 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 74 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
66 iomem_base: UART##num##_IO_BASE, \ 75 iomem_base: (void*)UART##num##_IO_BASE, \
67 io_type: SERIAL_IO_MEM}, 76 io_type: SERIAL_IO_MEM},
68 77
69#define SERIAL_PORT_DFNS \ 78#define SERIAL_PORT_DFNS \