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authorPaul Mackerras <paulus@samba.org>2008-06-09 00:01:46 -0400
committerPaul Mackerras <paulus@samba.org>2008-06-10 07:40:22 -0400
commit917f0af9e5a9ceecf9e72537fabb501254ba321d (patch)
tree1ef207755c6d83ce4af93ef2b5e4645eebd65886 /arch/ppc/platforms/4xx/xparameters
parent0f3d6bcd391b058c619fc30e8022e8a29fbf4bef (diff)
powerpc: Remove arch/ppc and include/asm-ppc
All the maintained platforms are now in arch/powerpc, so the old arch/ppc stuff can now go away. Acked-by: Adrian Bunk <bunk@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Jochen Friedrich <jochen@scram.de> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Sean MacLennan <smaclennan@pikatech.com> Acked-by: Segher Boessenkool <segher@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/platforms/4xx/xparameters')
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters.h104
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h310
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h243
3 files changed, 0 insertions, 657 deletions
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h
deleted file mode 100644
index 650888b00fb0..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/xparameters/xparameters.h
3 *
4 * This file includes the correct xparameters.h for the CONFIG'ed board plus
5 * fixups to translate board specific XPAR values to a common set of names
6 *
7 * Author: MontaVista Software, Inc.
8 * source@mvista.com
9 *
10 * 2004 (c) MontaVista Software, Inc. This file is licensed under the terms
11 * of the GNU General Public License version 2. This program is licensed
12 * "as is" without any warranty of any kind, whether express or implied.
13 */
14
15
16#if defined(CONFIG_XILINX_ML300)
17 #include "xparameters_ml300.h"
18 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
19 XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
20 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
21 XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
22#elif defined(CONFIG_XILINX_ML403)
23 #include "xparameters_ml403.h"
24 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
25 XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
26 #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
27 XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
28#else
29 /* Add other board xparameter includes here before the #else */
30 #error No xparameters_*.h file included
31#endif
32
33#ifndef SERIAL_PORT_DFNS
34 /* zImage serial port definitions */
35 #define RS_TABLE_SIZE 1
36 #define SERIAL_PORT_DFNS { \
37 .baud_base = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16, \
38 .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, \
39 .flags = ASYNC_BOOT_AUTOCONF, \
40 .iomem_base = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3, \
41 .iomem_reg_shift = 2, \
42 .io_type = SERIAL_IO_MEM, \
43 },
44#endif
45
46/*
47 * A few reasonable defaults for the #defines which could be missing depending
48 * on the IP version or variant (e.g. OPB vs PLB)
49 */
50
51#ifndef XPAR_EMAC_0_CAM_EXIST
52#define XPAR_EMAC_0_CAM_EXIST 0
53#endif
54#ifndef XPAR_EMAC_0_JUMBO_EXIST
55#define XPAR_EMAC_0_JUMBO_EXIST 0
56#endif
57#ifndef XPAR_EMAC_0_TX_DRE_TYPE
58#define XPAR_EMAC_0_TX_DRE_TYPE 0
59#endif
60#ifndef XPAR_EMAC_0_RX_DRE_TYPE
61#define XPAR_EMAC_0_RX_DRE_TYPE 0
62#endif
63#ifndef XPAR_EMAC_0_TX_INCLUDE_CSUM
64#define XPAR_EMAC_0_TX_INCLUDE_CSUM 0
65#endif
66#ifndef XPAR_EMAC_0_RX_INCLUDE_CSUM
67#define XPAR_EMAC_0_RX_INCLUDE_CSUM 0
68#endif
69
70#ifndef XPAR_EMAC_1_CAM_EXIST
71#define XPAR_EMAC_1_CAM_EXIST 0
72#endif
73#ifndef XPAR_EMAC_1_JUMBO_EXIST
74#define XPAR_EMAC_1_JUMBO_EXIST 0
75#endif
76#ifndef XPAR_EMAC_1_TX_DRE_TYPE
77#define XPAR_EMAC_1_TX_DRE_TYPE 0
78#endif
79#ifndef XPAR_EMAC_1_RX_DRE_TYPE
80#define XPAR_EMAC_1_RX_DRE_TYPE 0
81#endif
82#ifndef XPAR_EMAC_1_TX_INCLUDE_CSUM
83#define XPAR_EMAC_1_TX_INCLUDE_CSUM 0
84#endif
85#ifndef XPAR_EMAC_1_RX_INCLUDE_CSUM
86#define XPAR_EMAC_1_RX_INCLUDE_CSUM 0
87#endif
88
89#ifndef XPAR_GPIO_0_IS_DUAL
90#define XPAR_GPIO_0_IS_DUAL 0
91#endif
92#ifndef XPAR_GPIO_1_IS_DUAL
93#define XPAR_GPIO_1_IS_DUAL 0
94#endif
95#ifndef XPAR_GPIO_2_IS_DUAL
96#define XPAR_GPIO_2_IS_DUAL 0
97#endif
98#ifndef XPAR_GPIO_3_IS_DUAL
99#define XPAR_GPIO_3_IS_DUAL 0
100#endif
101#ifndef XPAR_GPIO_4_IS_DUAL
102#define XPAR_GPIO_4_IS_DUAL 0
103#endif
104
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
deleted file mode 100644
index 97e3f4d4bd54..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
+++ /dev/null
@@ -1,310 +0,0 @@
1/*******************************************************************
2*
3* Author: Xilinx, Inc.
4*
5*
6* This program is free software; you can redistribute it and/or modify it
7* under the terms of the GNU General Public License as published by the
8* Free Software Foundation; either version 2 of the License, or (at your
9* option) any later version.
10*
11*
12* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
13* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
14* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
15* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
16* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
17* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
18* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
19* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
20* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
21* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
22* FITNESS FOR A PARTICULAR PURPOSE.
23*
24*
25* Xilinx hardware products are not intended for use in life support
26* appliances, devices, or systems. Use in such applications is
27* expressly prohibited.
28*
29*
30* (c) Copyright 2002-2004 Xilinx Inc.
31* All rights reserved.
32*
33*
34* You should have received a copy of the GNU General Public License along
35* with this program; if not, write to the Free Software Foundation, Inc.,
36* 675 Mass Ave, Cambridge, MA 02139, USA.
37*
38* Description: Driver parameters
39*
40*******************************************************************/
41
42#define XPAR_XPCI_NUM_INSTANCES 1
43#define XPAR_XPCI_CLOCK_HZ 33333333
44#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0
45#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000
46#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF
47#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000
48#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004
49#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000
50#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000
51#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF
52#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000
53#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF
54
55/******************************************************************/
56
57#define XPAR_XEMAC_NUM_INSTANCES 1
58#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
59#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
60#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
61#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
62#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
63#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
64
65/******************************************************************/
66
67#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0
68#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000
69#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7)
70#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1
71#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8)
72#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F)
73#define XPAR_XGPIO_NUM_INSTANCES 2
74
75/******************************************************************/
76
77#define XPAR_XIIC_NUM_INSTANCES 1
78#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
79#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
80#define XPAR_OPB_IIC_0_DEVICE_ID 0
81#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
82
83/******************************************************************/
84
85#define XPAR_XUARTNS550_NUM_INSTANCES 2
86#define XPAR_XUARTNS550_CLOCK_HZ 100000000
87#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
88#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
89#define XPAR_OPB_UART16550_0_DEVICE_ID 0
90#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000
91#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF
92#define XPAR_OPB_UART16550_1_DEVICE_ID 1
93
94/******************************************************************/
95
96#define XPAR_XSPI_NUM_INSTANCES 1
97#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000
98#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F
99#define XPAR_OPB_SPI_0_DEVICE_ID 0
100#define XPAR_OPB_SPI_0_FIFO_EXIST 1
101#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0
102#define XPAR_OPB_SPI_0_NUM_SS_BITS 1
103
104/******************************************************************/
105
106#define XPAR_XPS2_NUM_INSTANCES 2
107#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
108#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
109#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
110#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
111#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
112#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
113
114/******************************************************************/
115
116#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
117#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000
118#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007
119#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0
120
121/******************************************************************/
122
123#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
124#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
125#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000
126#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF
127#define XPAR_PLB_DDR_0_BASEADDR 0x00000000
128#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF
129
130/******************************************************************/
131
132#define XPAR_XINTC_HAS_IPR 1
133#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18
134#define XPAR_XINTC_USE_DCR 0
135#define XPAR_XINTC_NUM_INSTANCES 1
136#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0
137#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF
138#define XPAR_DCR_INTC_0_DEVICE_ID 0
139#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000
140
141/******************************************************************/
142
143#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0
144#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1
145#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2
146#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3
147#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4
148#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5
149#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6
150#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7
151#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
152#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9
153#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10
154#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11
155#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12
156#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13
157#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14
158#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15
159#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16
160#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17
161
162/******************************************************************/
163
164#define XPAR_XTFT_NUM_INSTANCES 1
165#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
166#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
167#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
168
169/******************************************************************/
170
171#define XPAR_XSYSACE_MEM_WIDTH 8
172#define XPAR_XSYSACE_NUM_INSTANCES 1
173#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
174#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
175#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
176#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8
177
178/******************************************************************/
179
180#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
181
182/******************************************************************/
183
184/******************************************************************/
185
186/* Linux Redefines */
187
188/******************************************************************/
189
190#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
191#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
192#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
193#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
194#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000)
195#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR
196#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
197#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID
198
199/******************************************************************/
200
201#define XPAR_GPIO_0_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_0
202#define XPAR_GPIO_0_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_0
203#define XPAR_GPIO_0_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_0
204#define XPAR_GPIO_1_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_1
205#define XPAR_GPIO_1_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_1
206#define XPAR_GPIO_1_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_1
207
208/******************************************************************/
209
210#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
211#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
212#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
213#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
214
215/******************************************************************/
216
217#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
218#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
219#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
220
221/******************************************************************/
222
223#define XPAR_INTC_0_BASEADDR XPAR_DCR_INTC_0_BASEADDR
224#define XPAR_INTC_0_HIGHADDR XPAR_DCR_INTC_0_HIGHADDR
225#define XPAR_INTC_0_KIND_OF_INTR XPAR_DCR_INTC_0_KIND_OF_INTR
226#define XPAR_INTC_0_DEVICE_ID XPAR_DCR_INTC_0_DEVICE_ID
227
228/******************************************************************/
229
230#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
231#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
232#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
233#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
234#define XPAR_INTC_0_UARTNS550_1_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR
235#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
236#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
237#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR
238#define XPAR_INTC_0_TOUCHSCREEN_0_VEC_ID XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR
239#define XPAR_INTC_0_PCI_0_VEC_ID_A XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
240#define XPAR_INTC_0_PCI_0_VEC_ID_B XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
241#define XPAR_INTC_0_PCI_0_VEC_ID_C XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
242#define XPAR_INTC_0_PCI_0_VEC_ID_D XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
243
244/******************************************************************/
245
246#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
247#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
248#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
249#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
250#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
251#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
252
253/******************************************************************/
254
255#define XPAR_SPI_0_BASEADDR XPAR_OPB_SPI_0_BASEADDR
256#define XPAR_SPI_0_HIGHADDR XPAR_OPB_SPI_0_HIGHADDR
257#define XPAR_SPI_0_DEVICE_ID XPAR_OPB_SPI_0_DEVICE_ID
258
259/******************************************************************/
260
261#define XPAR_TOUCHSCREEN_0_BASEADDR XPAR_OPB_TSD_REF_0_BASEADDR
262#define XPAR_TOUCHSCREEN_0_HIGHADDR XPAR_OPB_TSD_REF_0_HIGHADDR
263#define XPAR_TOUCHSCREEN_0_DEVICE_ID XPAR_OPB_TSD_REF_0_DEVICE_ID
264
265/******************************************************************/
266
267#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
268
269/******************************************************************/
270
271#define XPAR_PCI_0_BASEADDR XPAR_OPB_PCI_REF_0_BASEADDR
272#define XPAR_PCI_0_HIGHADDR XPAR_OPB_PCI_REF_0_HIGHADDR
273#define XPAR_PCI_0_CONFIG_ADDR XPAR_OPB_PCI_REF_0_CONFIG_ADDR
274#define XPAR_PCI_0_CONFIG_DATA XPAR_OPB_PCI_REF_0_CONFIG_DATA
275#define XPAR_PCI_0_LCONFIG_ADDR XPAR_OPB_PCI_REF_0_LCONFIG_ADDR
276#define XPAR_PCI_0_MEM_BASEADDR XPAR_OPB_PCI_REF_0_MEM_BASEADDR
277#define XPAR_PCI_0_MEM_HIGHADDR XPAR_OPB_PCI_REF_0_MEM_HIGHADDR
278#define XPAR_PCI_0_IO_BASEADDR XPAR_OPB_PCI_REF_0_IO_BASEADDR
279#define XPAR_PCI_0_IO_HIGHADDR XPAR_OPB_PCI_REF_0_IO_HIGHADDR
280#define XPAR_PCI_0_CLOCK_FREQ_HZ XPAR_XPCI_CLOCK_HZ
281#define XPAR_PCI_0_DEVICE_ID XPAR_OPB_PCI_REF_0_DEVICE_ID
282
283/******************************************************************/
284
285#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
286#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
287#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
288#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
289#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
290#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
291
292/******************************************************************/
293
294#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
295#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
296#define XPAR_DDR_0_SIZE 0x08000000
297
298/******************************************************************/
299
300#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
301#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
302#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
303
304/******************************************************************/
305
306#define XPAR_POWER_0_POWERDOWN_BASEADDR 0x90000004
307#define XPAR_POWER_0_POWERDOWN_HIGHADDR 0x90000007
308#define XPAR_POWER_0_POWERDOWN_VALUE 0xFF
309
310/******************************************************************/
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
deleted file mode 100644
index 5cacdcb3964d..000000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
+++ /dev/null
@@ -1,243 +0,0 @@
1
2/*******************************************************************
3*
4* CAUTION: This file is automatically generated by libgen.
5* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
6* DO NOT EDIT.
7*
8* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
9*
10* Description: Driver parameters
11*
12*******************************************************************/
13
14#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000
15#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF
16
17/******************************************************************/
18
19#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000
20#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF
21#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000
22#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF
23#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
24#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
25#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000
26#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF
27#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000
28#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF
29
30/******************************************************************/
31
32#define XPAR_XEMAC_NUM_INSTANCES 1
33#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
34#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
35#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
36#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
37#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
38#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
39
40/******************************************************************/
41
42#define XPAR_XUARTNS550_NUM_INSTANCES 1
43#define XPAR_XUARTNS550_CLOCK_HZ 100000000
44#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
45#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
46#define XPAR_OPB_UART16550_0_DEVICE_ID 0
47
48/******************************************************************/
49
50#define XPAR_XGPIO_NUM_INSTANCES 3
51#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000
52#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF
53#define XPAR_OPB_GPIO_0_DEVICE_ID 0
54#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0
55#define XPAR_OPB_GPIO_0_IS_DUAL 1
56#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000
57#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF
58#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1
59#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0
60#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1
61#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000
62#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF
63#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2
64#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0
65#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0
66
67/******************************************************************/
68
69#define XPAR_XPS2_NUM_INSTANCES 2
70#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
71#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
72#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
73#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
74#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
75#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
76
77/******************************************************************/
78
79#define XPAR_XIIC_NUM_INSTANCES 1
80#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
81#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
82#define XPAR_OPB_IIC_0_DEVICE_ID 0
83#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
84#define XPAR_OPB_IIC_0_GPO_WIDTH 1
85
86/******************************************************************/
87
88#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10
89#define XPAR_XINTC_HAS_IPR 1
90#define XPAR_XINTC_USE_DCR 0
91#define XPAR_XINTC_NUM_INSTANCES 1
92#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0
93#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF
94#define XPAR_OPB_INTC_0_DEVICE_ID 0
95#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000
96
97/******************************************************************/
98
99#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0
100#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF
101#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
102#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001
103#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0
104#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002
105#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1
106#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004
107#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2
108#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008
109#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3
110#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010
111#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4
112#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020
113#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5
114#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040
115#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6
116#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080
117#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7
118#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100
119#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
120#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200
121#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9
122
123/******************************************************************/
124
125#define XPAR_XTFT_NUM_INSTANCES 1
126#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
127#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
128#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
129
130/******************************************************************/
131
132#define XPAR_XSYSACE_MEM_WIDTH 16
133#define XPAR_XSYSACE_NUM_INSTANCES 1
134#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
135#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
136#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
137#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16
138
139/******************************************************************/
140
141#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
142
143/******************************************************************/
144
145
146/******************************************************************/
147
148/* Linux Redefines */
149
150/******************************************************************/
151
152#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
153#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
154#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
155#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
156
157/******************************************************************/
158
159#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR
160#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR
161#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR
162#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
163
164/******************************************************************/
165
166#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
167#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
168#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
169#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
170#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
171#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
172
173/******************************************************************/
174
175#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
176
177/******************************************************************/
178
179#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
180#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
181#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
182#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
183#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
184#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
185
186/******************************************************************/
187
188#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0
189#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0
190#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0
191#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1
192#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1
193#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1
194#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0
195#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0
196#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0
197#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1
198#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1
199#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1
200#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR
201#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR
202#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID
203
204/******************************************************************/
205
206#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
207#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
208#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
209#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
210#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
211#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
212
213/******************************************************************/
214
215#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
216#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
217#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
218
219/******************************************************************/
220
221#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
222#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
223#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
224#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
225
226/******************************************************************/
227
228#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
229#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
230#define XPAR_DDR_0_SIZE 0x4000000
231
232/******************************************************************/
233
234#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
235#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
236#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
237
238/******************************************************************/
239
240#define XPAR_PCI_0_CLOCK_FREQ_HZ 0
241
242/******************************************************************/
243
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 09:59:53 -0500